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Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
49b1f4b4 | 2 | * Frame buffer driver for Trident TGUI, Blade and Image series |
1da177e4 | 3 | * |
245a2c2c | 4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> |
1da177e4 LT |
5 | * |
6 | * | |
7 | * CREDITS:(in order of appearance) | |
245a2c2c KH |
8 | * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video |
9 | * Special thanks ;) to Mattia Crivellini <tia@mclink.it> | |
10 | * much inspired by the XFree86 4.x Trident driver sources | |
11 | * by Alan Hourihane the FreeVGA project | |
12 | * Francesco Salvestrini <salvestrini@users.sf.net> XP support, | |
13 | * code, suggestions | |
1da177e4 | 14 | * TODO: |
245a2c2c | 15 | * timing value tweaking so it looks good on every monitor in every mode |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/fb.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/pci.h> | |
22 | ||
23 | #include <linux/delay.h> | |
10172ed6 | 24 | #include <video/vga.h> |
1da177e4 LT |
25 | #include <video/trident.h> |
26 | ||
1da177e4 | 27 | struct tridentfb_par { |
245a2c2c | 28 | void __iomem *io_virt; /* iospace virtual memory address */ |
ea8ee55c | 29 | u32 pseudo_pal[16]; |
122e8ad3 | 30 | int chip_id; |
6eed8e1e | 31 | int flatpanel; |
d9cad04b KH |
32 | void (*init_accel) (struct tridentfb_par *, int, int); |
33 | void (*wait_engine) (struct tridentfb_par *); | |
34 | void (*fill_rect) | |
35 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
36 | void (*copy_rect) | |
37 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
5cf13845 | 38 | unsigned char eng_oper; /* engine operation... */ |
1da177e4 LT |
39 | }; |
40 | ||
1da177e4 LT |
41 | static struct fb_ops tridentfb_ops; |
42 | ||
1da177e4 | 43 | static struct fb_fix_screeninfo tridentfb_fix = { |
245a2c2c | 44 | .id = "Trident", |
1da177e4 LT |
45 | .type = FB_TYPE_PACKED_PIXELS, |
46 | .ypanstep = 1, | |
47 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
48 | .accel = FB_ACCEL_NONE, | |
49 | }; | |
50 | ||
1da177e4 LT |
51 | /* defaults which are normally overriden by user values */ |
52 | ||
53 | /* video mode */ | |
5cf13845 | 54 | static char *mode_option __devinitdata = "640x480-8@60"; |
6eed8e1e | 55 | static int bpp __devinitdata = 8; |
1da177e4 | 56 | |
6eed8e1e | 57 | static int noaccel __devinitdata; |
1da177e4 LT |
58 | |
59 | static int center; | |
60 | static int stretch; | |
61 | ||
6eed8e1e KH |
62 | static int fp __devinitdata; |
63 | static int crt __devinitdata; | |
1da177e4 | 64 | |
6eed8e1e KH |
65 | static int memsize __devinitdata; |
66 | static int memdiff __devinitdata; | |
1da177e4 LT |
67 | static int nativex; |
68 | ||
07f41e45 KH |
69 | module_param(mode_option, charp, 0); |
70 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
9e3f0ca8 KH |
71 | module_param_named(mode, mode_option, charp, 0); |
72 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
1da177e4 LT |
73 | module_param(bpp, int, 0); |
74 | module_param(center, int, 0); | |
75 | module_param(stretch, int, 0); | |
76 | module_param(noaccel, int, 0); | |
77 | module_param(memsize, int, 0); | |
78 | module_param(memdiff, int, 0); | |
79 | module_param(nativex, int, 0); | |
80 | module_param(fp, int, 0); | |
6eed8e1e | 81 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); |
1da177e4 | 82 | module_param(crt, int, 0); |
6eed8e1e | 83 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); |
1da177e4 | 84 | |
5cf13845 | 85 | static inline int is_oldclock(int id) |
6bdf1035 | 86 | { |
a0d92256 KH |
87 | return (id == TGUI9440) || |
88 | (id == TGUI9660) || | |
0e73a47f KH |
89 | (id == CYBER9320); |
90 | } | |
91 | ||
5cf13845 | 92 | static inline int is_oldprotect(int id) |
0e73a47f | 93 | { |
5cf13845 | 94 | return is_oldclock(id) || |
0e73a47f | 95 | (id == PROVIDIA9685) || |
0e73a47f KH |
96 | (id == CYBER9382) || |
97 | (id == CYBER9385); | |
6bdf1035 KH |
98 | } |
99 | ||
5cf13845 | 100 | static inline int is_blade(int id) |
e0759a5f KH |
101 | { |
102 | return (id == BLADE3D) || | |
103 | (id == CYBERBLADEE4) || | |
104 | (id == CYBERBLADEi7) || | |
105 | (id == CYBERBLADEi7D) || | |
106 | (id == CYBERBLADEi1) || | |
107 | (id == CYBERBLADEi1D) || | |
108 | (id == CYBERBLADEAi1) || | |
109 | (id == CYBERBLADEAi1D); | |
110 | } | |
111 | ||
5cf13845 | 112 | static inline int is_xp(int id) |
e0759a5f KH |
113 | { |
114 | return (id == CYBERBLADEXPAi1) || | |
115 | (id == CYBERBLADEXPm8) || | |
116 | (id == CYBERBLADEXPm16); | |
117 | } | |
118 | ||
5cf13845 | 119 | static inline int is3Dchip(int id) |
1da177e4 | 120 | { |
5cf13845 | 121 | return is_blade(id) || is_xp(id) || |
245a2c2c KH |
122 | (id == CYBER9397) || (id == CYBER9397DVD) || |
123 | (id == CYBER9520) || (id == CYBER9525DVD) || | |
5cf13845 | 124 | (id == IMAGE975) || (id == IMAGE985); |
1da177e4 LT |
125 | } |
126 | ||
5cf13845 | 127 | static inline int iscyber(int id) |
1da177e4 LT |
128 | { |
129 | switch (id) { | |
245a2c2c KH |
130 | case CYBER9388: |
131 | case CYBER9382: | |
132 | case CYBER9385: | |
133 | case CYBER9397: | |
134 | case CYBER9397DVD: | |
135 | case CYBER9520: | |
136 | case CYBER9525DVD: | |
137 | case CYBERBLADEE4: | |
138 | case CYBERBLADEi7D: | |
139 | case CYBERBLADEi1: | |
140 | case CYBERBLADEi1D: | |
141 | case CYBERBLADEAi1: | |
142 | case CYBERBLADEAi1D: | |
143 | case CYBERBLADEXPAi1: | |
144 | return 1; | |
1da177e4 | 145 | |
245a2c2c | 146 | case CYBER9320: |
245a2c2c | 147 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ |
245a2c2c KH |
148 | default: |
149 | /* case CYBERBLDAEXPm8: Strange */ | |
150 | /* case CYBERBLDAEXPm16: Strange */ | |
151 | return 0; | |
1da177e4 LT |
152 | } |
153 | } | |
154 | ||
306fa6f6 KH |
155 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) |
156 | { | |
157 | fb_writeb(val, p->io_virt + reg); | |
158 | } | |
1da177e4 | 159 | |
306fa6f6 KH |
160 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) |
161 | { | |
162 | return fb_readb(p->io_virt + reg); | |
163 | } | |
1da177e4 | 164 | |
306fa6f6 KH |
165 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) |
166 | { | |
167 | fb_writel(v, par->io_virt + r); | |
168 | } | |
169 | ||
170 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) | |
171 | { | |
172 | return fb_readl(par->io_virt + r); | |
173 | } | |
1da177e4 | 174 | |
1da177e4 LT |
175 | /* |
176 | * Blade specific acceleration. | |
177 | */ | |
178 | ||
245a2c2c | 179 | #define point(x, y) ((y) << 16 | (x)) |
1da177e4 | 180 | |
306fa6f6 | 181 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 182 | { |
245a2c2c | 183 | int v1 = (pitch >> 3) << 20; |
49b1f4b4 KH |
184 | int tmp = bpp == 24 ? 2 : (bpp >> 4); |
185 | int v2 = v1 | (tmp << 29); | |
186 | ||
306fa6f6 KH |
187 | writemmr(par, 0x21C0, v2); |
188 | writemmr(par, 0x21C4, v2); | |
189 | writemmr(par, 0x21B8, v2); | |
190 | writemmr(par, 0x21BC, v2); | |
191 | writemmr(par, 0x21D0, v1); | |
192 | writemmr(par, 0x21D4, v1); | |
193 | writemmr(par, 0x21C8, v1); | |
194 | writemmr(par, 0x21CC, v1); | |
195 | writemmr(par, 0x216C, 0); | |
1da177e4 LT |
196 | } |
197 | ||
306fa6f6 | 198 | static void blade_wait_engine(struct tridentfb_par *par) |
1da177e4 | 199 | { |
49b1f4b4 KH |
200 | while (readmmr(par, STATUS) & 0xFA800000) |
201 | cpu_relax(); | |
1da177e4 LT |
202 | } |
203 | ||
306fa6f6 KH |
204 | static void blade_fill_rect(struct tridentfb_par *par, |
205 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 206 | { |
49b1f4b4 KH |
207 | writemmr(par, COLOR, c); |
208 | writemmr(par, ROP, rop ? ROP_X : ROP_S); | |
306fa6f6 | 209 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); |
1da177e4 | 210 | |
49b1f4b4 KH |
211 | writemmr(par, DST1, point(x, y)); |
212 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 LT |
213 | } |
214 | ||
306fa6f6 KH |
215 | static void blade_copy_rect(struct tridentfb_par *par, |
216 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 217 | { |
1da177e4 | 218 | int direction = 2; |
49b1f4b4 KH |
219 | u32 s1 = point(x1, y1); |
220 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
221 | u32 d1 = point(x2, y2); | |
222 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 LT |
223 | |
224 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
245a2c2c | 225 | direction = 0; |
1da177e4 | 226 | |
306fa6f6 KH |
227 | writemmr(par, ROP, ROP_S); |
228 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | |
1da177e4 | 229 | |
49b1f4b4 KH |
230 | writemmr(par, SRC1, direction ? s2 : s1); |
231 | writemmr(par, SRC2, direction ? s1 : s2); | |
232 | writemmr(par, DST1, direction ? d2 : d1); | |
233 | writemmr(par, DST2, direction ? d1 : d2); | |
1da177e4 LT |
234 | } |
235 | ||
1da177e4 LT |
236 | /* |
237 | * BladeXP specific acceleration functions | |
238 | */ | |
239 | ||
306fa6f6 | 240 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 241 | { |
49b1f4b4 KH |
242 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
243 | int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); | |
1da177e4 LT |
244 | |
245 | switch (pitch << (bpp >> 3)) { | |
245a2c2c KH |
246 | case 8192: |
247 | case 512: | |
248 | x |= 0x00; | |
249 | break; | |
250 | case 1024: | |
251 | x |= 0x04; | |
252 | break; | |
253 | case 2048: | |
254 | x |= 0x08; | |
255 | break; | |
256 | case 4096: | |
257 | x |= 0x0C; | |
258 | break; | |
1da177e4 LT |
259 | } |
260 | ||
306fa6f6 | 261 | t_outb(par, x, 0x2125); |
1da177e4 | 262 | |
5cf13845 | 263 | par->eng_oper = x | 0x40; |
1da177e4 | 264 | |
306fa6f6 KH |
265 | writemmr(par, 0x2154, v1); |
266 | writemmr(par, 0x2150, v1); | |
267 | t_outb(par, 3, 0x2126); | |
1da177e4 LT |
268 | } |
269 | ||
306fa6f6 | 270 | static void xp_wait_engine(struct tridentfb_par *par) |
1da177e4 | 271 | { |
5cf13845 KH |
272 | int count = 0; |
273 | int timeout = 0; | |
1da177e4 | 274 | |
49b1f4b4 | 275 | while (t_inb(par, STATUS) & 0x80) { |
1da177e4 LT |
276 | count++; |
277 | if (count == 10000000) { | |
278 | /* Timeout */ | |
279 | count = 9990000; | |
280 | timeout++; | |
281 | if (timeout == 8) { | |
282 | /* Reset engine */ | |
49b1f4b4 | 283 | t_outb(par, 0x00, STATUS); |
1da177e4 LT |
284 | return; |
285 | } | |
286 | } | |
49b1f4b4 | 287 | cpu_relax(); |
1da177e4 LT |
288 | } |
289 | } | |
290 | ||
306fa6f6 KH |
291 | static void xp_fill_rect(struct tridentfb_par *par, |
292 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 293 | { |
306fa6f6 KH |
294 | writemmr(par, 0x2127, ROP_P); |
295 | writemmr(par, 0x2158, c); | |
49b1f4b4 KH |
296 | writemmr(par, DRAWFL, 0x4000); |
297 | writemmr(par, OLDDIM, point(h, w)); | |
298 | writemmr(par, OLDDST, point(y, x)); | |
299 | t_outb(par, 0x01, OLDCMD); | |
5cf13845 | 300 | t_outb(par, par->eng_oper, 0x2125); |
1da177e4 LT |
301 | } |
302 | ||
306fa6f6 KH |
303 | static void xp_copy_rect(struct tridentfb_par *par, |
304 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 305 | { |
245a2c2c | 306 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; |
5cf13845 | 307 | int direction = 0x0004; |
245a2c2c | 308 | |
1da177e4 LT |
309 | if ((x1 < x2) && (y1 == y2)) { |
310 | direction |= 0x0200; | |
311 | x1_tmp = x1 + w - 1; | |
312 | x2_tmp = x2 + w - 1; | |
313 | } else { | |
314 | x1_tmp = x1; | |
315 | x2_tmp = x2; | |
316 | } | |
245a2c2c | 317 | |
1da177e4 LT |
318 | if (y1 < y2) { |
319 | direction |= 0x0100; | |
320 | y1_tmp = y1 + h - 1; | |
321 | y2_tmp = y2 + h - 1; | |
245a2c2c | 322 | } else { |
1da177e4 LT |
323 | y1_tmp = y1; |
324 | y2_tmp = y2; | |
325 | } | |
326 | ||
49b1f4b4 | 327 | writemmr(par, DRAWFL, direction); |
306fa6f6 | 328 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
329 | writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); |
330 | writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); | |
331 | writemmr(par, OLDDIM, point(h, w)); | |
332 | t_outb(par, 0x01, OLDCMD); | |
1da177e4 LT |
333 | } |
334 | ||
1da177e4 LT |
335 | /* |
336 | * Image specific acceleration functions | |
337 | */ | |
306fa6f6 | 338 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 339 | { |
49b1f4b4 KH |
340 | int tmp = bpp == 24 ? 2: (bpp >> 4); |
341 | ||
306fa6f6 KH |
342 | writemmr(par, 0x2120, 0xF0000000); |
343 | writemmr(par, 0x2120, 0x40000000 | tmp); | |
344 | writemmr(par, 0x2120, 0x80000000); | |
345 | writemmr(par, 0x2144, 0x00000000); | |
346 | writemmr(par, 0x2148, 0x00000000); | |
347 | writemmr(par, 0x2150, 0x00000000); | |
348 | writemmr(par, 0x2154, 0x00000000); | |
349 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); | |
350 | writemmr(par, 0x216C, 0x00000000); | |
351 | writemmr(par, 0x2170, 0x00000000); | |
352 | writemmr(par, 0x217C, 0x00000000); | |
353 | writemmr(par, 0x2120, 0x10000000); | |
354 | writemmr(par, 0x2130, (2047 << 16) | 2047); | |
1da177e4 LT |
355 | } |
356 | ||
306fa6f6 | 357 | static void image_wait_engine(struct tridentfb_par *par) |
1da177e4 | 358 | { |
49b1f4b4 KH |
359 | while (readmmr(par, 0x2164) & 0xF0000000) |
360 | cpu_relax(); | |
1da177e4 LT |
361 | } |
362 | ||
306fa6f6 KH |
363 | static void image_fill_rect(struct tridentfb_par *par, |
364 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 365 | { |
306fa6f6 KH |
366 | writemmr(par, 0x2120, 0x80000000); |
367 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
1da177e4 | 368 | |
306fa6f6 | 369 | writemmr(par, 0x2144, c); |
1da177e4 | 370 | |
49b1f4b4 KH |
371 | writemmr(par, DST1, point(x, y)); |
372 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 | 373 | |
306fa6f6 | 374 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); |
1da177e4 LT |
375 | } |
376 | ||
306fa6f6 KH |
377 | static void image_copy_rect(struct tridentfb_par *par, |
378 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 379 | { |
2c86a0c2 | 380 | int direction = 0x4; |
49b1f4b4 KH |
381 | u32 s1 = point(x1, y1); |
382 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
383 | u32 d1 = point(x2, y2); | |
384 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 | 385 | |
245a2c2c KH |
386 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
387 | direction = 0; | |
388 | ||
306fa6f6 KH |
389 | writemmr(par, 0x2120, 0x80000000); |
390 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
245a2c2c | 391 | |
49b1f4b4 KH |
392 | writemmr(par, SRC1, direction ? s2 : s1); |
393 | writemmr(par, SRC2, direction ? s1 : s2); | |
394 | writemmr(par, DST1, direction ? d2 : d1); | |
395 | writemmr(par, DST2, direction ? d1 : d2); | |
306fa6f6 KH |
396 | writemmr(par, 0x2124, |
397 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | |
245a2c2c | 398 | } |
1da177e4 | 399 | |
bcac2d5f KH |
400 | /* |
401 | * TGUI 9440/96XX acceleration | |
402 | */ | |
403 | ||
404 | static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
405 | { | |
49b1f4b4 | 406 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
bcac2d5f KH |
407 | |
408 | /* disable clipping */ | |
409 | writemmr(par, 0x2148, 0); | |
410 | writemmr(par, 0x214C, point(4095, 2047)); | |
411 | ||
bcac2d5f KH |
412 | switch ((pitch * bpp) / 8) { |
413 | case 8192: | |
414 | case 512: | |
415 | x |= 0x00; | |
416 | break; | |
417 | case 1024: | |
418 | x |= 0x04; | |
419 | break; | |
420 | case 2048: | |
421 | x |= 0x08; | |
422 | break; | |
423 | case 4096: | |
424 | x |= 0x0C; | |
425 | break; | |
426 | } | |
427 | ||
428 | fb_writew(x, par->io_virt + 0x2122); | |
429 | } | |
430 | ||
431 | static void tgui_fill_rect(struct tridentfb_par *par, | |
432 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
433 | { | |
434 | t_outb(par, ROP_P, 0x2127); | |
49b1f4b4 KH |
435 | writemmr(par, OLDCLR, c); |
436 | writemmr(par, DRAWFL, 0x4020); | |
437 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
438 | writemmr(par, OLDDST, point(x, y)); | |
439 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
440 | } |
441 | ||
442 | static void tgui_copy_rect(struct tridentfb_par *par, | |
443 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
444 | { | |
445 | int flags = 0; | |
446 | u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | |
447 | ||
448 | if ((x1 < x2) && (y1 == y2)) { | |
449 | flags |= 0x0200; | |
450 | x1_tmp = x1 + w - 1; | |
451 | x2_tmp = x2 + w - 1; | |
452 | } else { | |
453 | x1_tmp = x1; | |
454 | x2_tmp = x2; | |
455 | } | |
456 | ||
457 | if (y1 < y2) { | |
458 | flags |= 0x0100; | |
459 | y1_tmp = y1 + h - 1; | |
460 | y2_tmp = y2 + h - 1; | |
461 | } else { | |
462 | y1_tmp = y1; | |
463 | y2_tmp = y2; | |
464 | } | |
465 | ||
49b1f4b4 | 466 | writemmr(par, DRAWFL, 0x4 | flags); |
bcac2d5f | 467 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
468 | writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); |
469 | writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); | |
470 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
471 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
472 | } |
473 | ||
1da177e4 LT |
474 | /* |
475 | * Accel functions called by the upper layers | |
476 | */ | |
477 | #ifdef CONFIG_FB_TRIDENT_ACCEL | |
245a2c2c KH |
478 | static void tridentfb_fillrect(struct fb_info *info, |
479 | const struct fb_fillrect *fr) | |
1da177e4 | 480 | { |
306fa6f6 | 481 | struct tridentfb_par *par = info->par; |
49b1f4b4 | 482 | int col; |
245a2c2c | 483 | |
01a2d9ed KH |
484 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
485 | cfb_fillrect(info, fr); | |
486 | return; | |
487 | } | |
49b1f4b4 KH |
488 | if (info->var.bits_per_pixel == 8) { |
489 | col = fr->color; | |
245a2c2c KH |
490 | col |= col << 8; |
491 | col |= col << 16; | |
49b1f4b4 | 492 | } else |
245a2c2c | 493 | col = ((u32 *)(info->pseudo_palette))[fr->color]; |
245a2c2c | 494 | |
49b1f4b4 | 495 | par->wait_engine(par); |
d9cad04b | 496 | par->fill_rect(par, fr->dx, fr->dy, fr->width, |
306fa6f6 | 497 | fr->height, col, fr->rop); |
1da177e4 | 498 | } |
49b1f4b4 | 499 | |
245a2c2c KH |
500 | static void tridentfb_copyarea(struct fb_info *info, |
501 | const struct fb_copyarea *ca) | |
1da177e4 | 502 | { |
306fa6f6 KH |
503 | struct tridentfb_par *par = info->par; |
504 | ||
01a2d9ed KH |
505 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
506 | cfb_copyarea(info, ca); | |
507 | return; | |
508 | } | |
49b1f4b4 | 509 | par->wait_engine(par); |
d9cad04b | 510 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, |
306fa6f6 | 511 | ca->width, ca->height); |
49b1f4b4 KH |
512 | } |
513 | ||
514 | static int tridentfb_sync(struct fb_info *info) | |
515 | { | |
516 | struct tridentfb_par *par = info->par; | |
517 | ||
01a2d9ed KH |
518 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) |
519 | par->wait_engine(par); | |
49b1f4b4 | 520 | return 0; |
1da177e4 | 521 | } |
49b1f4b4 KH |
522 | #else |
523 | #define tridentfb_fillrect cfb_fillrect | |
524 | #define tridentfb_copyarea cfb_copyarea | |
1da177e4 LT |
525 | #endif /* CONFIG_FB_TRIDENT_ACCEL */ |
526 | ||
1da177e4 LT |
527 | /* |
528 | * Hardware access functions | |
529 | */ | |
530 | ||
306fa6f6 | 531 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) |
1da177e4 | 532 | { |
10172ed6 | 533 | return vga_mm_rcrt(par->io_virt, reg); |
1da177e4 LT |
534 | } |
535 | ||
306fa6f6 KH |
536 | static inline void write3X4(struct tridentfb_par *par, int reg, |
537 | unsigned char val) | |
1da177e4 | 538 | { |
10172ed6 | 539 | vga_mm_wcrt(par->io_virt, reg, val); |
1da177e4 LT |
540 | } |
541 | ||
10172ed6 KH |
542 | static inline unsigned char read3CE(struct tridentfb_par *par, |
543 | unsigned char reg) | |
1da177e4 | 544 | { |
10172ed6 | 545 | return vga_mm_rgfx(par->io_virt, reg); |
1da177e4 LT |
546 | } |
547 | ||
306fa6f6 KH |
548 | static inline void writeAttr(struct tridentfb_par *par, int reg, |
549 | unsigned char val) | |
1da177e4 | 550 | { |
10172ed6 KH |
551 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
552 | vga_mm_wattr(par->io_virt, reg, val); | |
1da177e4 LT |
553 | } |
554 | ||
306fa6f6 KH |
555 | static inline void write3CE(struct tridentfb_par *par, int reg, |
556 | unsigned char val) | |
1da177e4 | 557 | { |
10172ed6 | 558 | vga_mm_wgfx(par->io_virt, reg, val); |
1da177e4 LT |
559 | } |
560 | ||
13b0de49 | 561 | static void enable_mmio(struct tridentfb_par *par) |
1da177e4 LT |
562 | { |
563 | /* Goto New Mode */ | |
10172ed6 | 564 | vga_io_rseq(0x0B); |
1da177e4 LT |
565 | |
566 | /* Unprotect registers */ | |
10172ed6 | 567 | vga_io_wseq(NewMode1, 0x80); |
13b0de49 KH |
568 | if (!is_oldprotect(par->chip_id)) |
569 | vga_io_wseq(Protection, 0x92); | |
245a2c2c | 570 | |
1da177e4 | 571 | /* Enable MMIO */ |
245a2c2c | 572 | outb(PCIReg, 0x3D4); |
1da177e4 | 573 | outb(inb(0x3D5) | 0x01, 0x3D5); |
e8ed857c KH |
574 | } |
575 | ||
306fa6f6 | 576 | static void disable_mmio(struct tridentfb_par *par) |
e8ed857c | 577 | { |
e8ed857c | 578 | /* Goto New Mode */ |
10172ed6 | 579 | vga_mm_rseq(par->io_virt, 0x0B); |
e8ed857c KH |
580 | |
581 | /* Unprotect registers */ | |
10172ed6 | 582 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); |
13b0de49 KH |
583 | if (!is_oldprotect(par->chip_id)) |
584 | vga_mm_wseq(par->io_virt, Protection, 0x92); | |
e8ed857c KH |
585 | |
586 | /* Disable MMIO */ | |
306fa6f6 KH |
587 | t_outb(par, PCIReg, 0x3D4); |
588 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); | |
1da177e4 LT |
589 | } |
590 | ||
5cf13845 | 591 | static inline void crtc_unlock(struct tridentfb_par *par) |
306fa6f6 | 592 | { |
10172ed6 KH |
593 | write3X4(par, VGA_CRTC_V_SYNC_END, |
594 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | |
306fa6f6 | 595 | } |
1da177e4 LT |
596 | |
597 | /* Return flat panel's maximum x resolution */ | |
306fa6f6 | 598 | static int __devinit get_nativex(struct tridentfb_par *par) |
1da177e4 | 599 | { |
245a2c2c | 600 | int x, y, tmp; |
1da177e4 LT |
601 | |
602 | if (nativex) | |
603 | return nativex; | |
604 | ||
306fa6f6 | 605 | tmp = (read3CE(par, VertStretch) >> 4) & 3; |
1da177e4 LT |
606 | |
607 | switch (tmp) { | |
245a2c2c KH |
608 | case 0: |
609 | x = 1280; y = 1024; | |
610 | break; | |
611 | case 2: | |
612 | x = 1024; y = 768; | |
613 | break; | |
614 | case 3: | |
615 | x = 800; y = 600; | |
616 | break; | |
617 | case 4: | |
618 | x = 1400; y = 1050; | |
619 | break; | |
620 | case 1: | |
621 | default: | |
622 | x = 640; y = 480; | |
623 | break; | |
1da177e4 LT |
624 | } |
625 | ||
626 | output("%dx%d flat panel found\n", x, y); | |
627 | return x; | |
628 | } | |
629 | ||
630 | /* Set pitch */ | |
5cf13845 | 631 | static inline void set_lwidth(struct tridentfb_par *par, int width) |
1da177e4 | 632 | { |
10172ed6 | 633 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); |
306fa6f6 KH |
634 | write3X4(par, AddColReg, |
635 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | |
1da177e4 LT |
636 | } |
637 | ||
638 | /* For resolutions smaller than FP resolution stretch */ | |
306fa6f6 | 639 | static void screen_stretch(struct tridentfb_par *par) |
1da177e4 | 640 | { |
122e8ad3 | 641 | if (par->chip_id != CYBERBLADEXPAi1) |
306fa6f6 | 642 | write3CE(par, BiosReg, 0); |
245a2c2c | 643 | else |
306fa6f6 KH |
644 | write3CE(par, BiosReg, 8); |
645 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); | |
646 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); | |
1da177e4 LT |
647 | } |
648 | ||
649 | /* For resolutions smaller than FP resolution center */ | |
5cf13845 | 650 | static inline void screen_center(struct tridentfb_par *par) |
1da177e4 | 651 | { |
306fa6f6 KH |
652 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); |
653 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); | |
1da177e4 LT |
654 | } |
655 | ||
656 | /* Address of first shown pixel in display memory */ | |
306fa6f6 | 657 | static void set_screen_start(struct tridentfb_par *par, int base) |
1da177e4 | 658 | { |
306fa6f6 | 659 | u8 tmp; |
10172ed6 KH |
660 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); |
661 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); | |
306fa6f6 KH |
662 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; |
663 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); | |
664 | tmp = read3X4(par, CRTHiOrd) & 0xF8; | |
665 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | |
1da177e4 LT |
666 | } |
667 | ||
1da177e4 | 668 | /* Set dotclock frequency */ |
306fa6f6 | 669 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) |
1da177e4 | 670 | { |
245a2c2c | 671 | int m, n, k; |
6bdf1035 KH |
672 | unsigned long fi, d, di; |
673 | unsigned char best_m = 0, best_n = 0, best_k = 0; | |
674 | unsigned char hi, lo; | |
6280fd4f | 675 | unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1; |
1da177e4 | 676 | |
3f275ea3 | 677 | d = 20000; |
6280fd4f KH |
678 | for (k = shift; k >= 0; k--) |
679 | for (m = 1; m < 32; m++) { | |
680 | n = ((m + 2) << shift) - 8; | |
34dec243 | 681 | for (n = (n < 0 ? 0 : n); n < 122; n++) { |
3f275ea3 | 682 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; |
34dec243 | 683 | di = abs(fi - freq); |
6280fd4f | 684 | if (di < d || (di == d && k == best_k)) { |
245a2c2c | 685 | d = di; |
6bdf1035 KH |
686 | best_n = n; |
687 | best_m = m; | |
688 | best_k = k; | |
245a2c2c | 689 | } |
3f275ea3 KH |
690 | if (fi > freq) |
691 | break; | |
245a2c2c | 692 | } |
34dec243 | 693 | } |
6bdf1035 KH |
694 | |
695 | if (is_oldclock(par->chip_id)) { | |
696 | lo = best_n | (best_m << 7); | |
697 | hi = (best_m >> 1) | (best_k << 4); | |
698 | } else { | |
699 | lo = best_n; | |
700 | hi = best_m | (best_k << 6); | |
701 | } | |
702 | ||
122e8ad3 | 703 | if (is3Dchip(par->chip_id)) { |
10172ed6 KH |
704 | vga_mm_wseq(par->io_virt, ClockHigh, hi); |
705 | vga_mm_wseq(par->io_virt, ClockLow, lo); | |
1da177e4 | 706 | } else { |
c1724fec KH |
707 | t_outb(par, lo, 0x43C8); |
708 | t_outb(par, hi, 0x43C9); | |
1da177e4 | 709 | } |
245a2c2c | 710 | debug("VCLK = %X %X\n", hi, lo); |
1da177e4 LT |
711 | } |
712 | ||
713 | /* Set number of lines for flat panels*/ | |
306fa6f6 | 714 | static void set_number_of_lines(struct tridentfb_par *par, int lines) |
1da177e4 | 715 | { |
306fa6f6 | 716 | int tmp = read3CE(par, CyberEnhance) & 0x8F; |
1da177e4 LT |
717 | if (lines > 1024) |
718 | tmp |= 0x50; | |
719 | else if (lines > 768) | |
720 | tmp |= 0x30; | |
721 | else if (lines > 600) | |
722 | tmp |= 0x20; | |
723 | else if (lines > 480) | |
724 | tmp |= 0x10; | |
306fa6f6 | 725 | write3CE(par, CyberEnhance, tmp); |
1da177e4 LT |
726 | } |
727 | ||
728 | /* | |
729 | * If we see that FP is active we assume we have one. | |
6eed8e1e | 730 | * Otherwise we have a CRT display. User can override. |
1da177e4 | 731 | */ |
6eed8e1e | 732 | static int __devinit is_flatpanel(struct tridentfb_par *par) |
1da177e4 LT |
733 | { |
734 | if (fp) | |
6eed8e1e | 735 | return 1; |
122e8ad3 | 736 | if (crt || !iscyber(par->chip_id)) |
6eed8e1e KH |
737 | return 0; |
738 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; | |
1da177e4 LT |
739 | } |
740 | ||
741 | /* Try detecting the video memory size */ | |
306fa6f6 | 742 | static unsigned int __devinit get_memsize(struct tridentfb_par *par) |
1da177e4 LT |
743 | { |
744 | unsigned char tmp, tmp2; | |
745 | unsigned int k; | |
746 | ||
747 | /* If memory size provided by user */ | |
748 | if (memsize) | |
749 | k = memsize * Kb; | |
750 | else | |
122e8ad3 | 751 | switch (par->chip_id) { |
245a2c2c KH |
752 | case CYBER9525DVD: |
753 | k = 2560 * Kb; | |
754 | break; | |
1da177e4 | 755 | default: |
306fa6f6 | 756 | tmp = read3X4(par, SPR) & 0x0F; |
1da177e4 LT |
757 | switch (tmp) { |
758 | ||
245a2c2c | 759 | case 0x01: |
b614ce8b | 760 | k = 512 * Kb; |
245a2c2c KH |
761 | break; |
762 | case 0x02: | |
763 | k = 6 * Mb; /* XP */ | |
764 | break; | |
765 | case 0x03: | |
766 | k = 1 * Mb; | |
767 | break; | |
768 | case 0x04: | |
769 | k = 8 * Mb; | |
770 | break; | |
771 | case 0x06: | |
772 | k = 10 * Mb; /* XP */ | |
773 | break; | |
774 | case 0x07: | |
775 | k = 2 * Mb; | |
776 | break; | |
777 | case 0x08: | |
778 | k = 12 * Mb; /* XP */ | |
779 | break; | |
780 | case 0x0A: | |
781 | k = 14 * Mb; /* XP */ | |
782 | break; | |
783 | case 0x0C: | |
784 | k = 16 * Mb; /* XP */ | |
785 | break; | |
786 | case 0x0E: /* XP */ | |
787 | ||
10172ed6 | 788 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); |
245a2c2c KH |
789 | switch (tmp2) { |
790 | case 0x00: | |
791 | k = 20 * Mb; | |
792 | break; | |
793 | case 0x01: | |
794 | k = 24 * Mb; | |
795 | break; | |
796 | case 0x10: | |
797 | k = 28 * Mb; | |
798 | break; | |
799 | case 0x11: | |
800 | k = 32 * Mb; | |
801 | break; | |
802 | default: | |
803 | k = 1 * Mb; | |
804 | break; | |
805 | } | |
806 | break; | |
807 | ||
808 | case 0x0F: | |
809 | k = 4 * Mb; | |
810 | break; | |
811 | default: | |
812 | k = 1 * Mb; | |
1da177e4 | 813 | break; |
1da177e4 | 814 | } |
245a2c2c | 815 | } |
1da177e4 LT |
816 | |
817 | k -= memdiff * Kb; | |
245a2c2c | 818 | output("framebuffer size = %d Kb\n", k / Kb); |
1da177e4 LT |
819 | return k; |
820 | } | |
821 | ||
822 | /* See if we can handle the video mode described in var */ | |
245a2c2c KH |
823 | static int tridentfb_check_var(struct fb_var_screeninfo *var, |
824 | struct fb_info *info) | |
1da177e4 | 825 | { |
6eed8e1e | 826 | struct tridentfb_par *par = info->par; |
1da177e4 | 827 | int bpp = var->bits_per_pixel; |
bcac2d5f | 828 | int line_length; |
74a933fe | 829 | int ramdac = 230000; /* 230MHz for most 3D chips */ |
1da177e4 LT |
830 | debug("enter\n"); |
831 | ||
832 | /* check color depth */ | |
245a2c2c | 833 | if (bpp == 24) |
1da177e4 | 834 | bpp = var->bits_per_pixel = 32; |
49b1f4b4 KH |
835 | if (bpp != 8 && bpp != 16 && bpp != 32) |
836 | return -EINVAL; | |
54f019e5 KH |
837 | if (par->chip_id == TGUI9440 && bpp == 32) |
838 | return -EINVAL; | |
245a2c2c | 839 | /* check whether resolution fits on panel and in memory */ |
6eed8e1e | 840 | if (par->flatpanel && nativex && var->xres > nativex) |
1da177e4 | 841 | return -EINVAL; |
74a933fe KH |
842 | /* various resolution checks */ |
843 | var->xres = (var->xres + 7) & ~0x7; | |
49b1f4b4 | 844 | if (var->xres > var->xres_virtual) |
74a933fe | 845 | var->xres_virtual = var->xres; |
49b1f4b4 KH |
846 | if (var->yres > var->yres_virtual) |
847 | var->yres_virtual = var->yres; | |
848 | if (var->xres_virtual > 4095 || var->yres > 2048) | |
849 | return -EINVAL; | |
850 | /* prevent from position overflow for acceleration */ | |
851 | if (var->yres_virtual > 0xffff) | |
852 | return -EINVAL; | |
bcac2d5f | 853 | line_length = var->xres_virtual * bpp / 8; |
01a2d9ed KH |
854 | |
855 | if (!is3Dchip(par->chip_id) && | |
856 | !(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
bcac2d5f KH |
857 | /* acceleration requires line length to be power of 2 */ |
858 | if (line_length <= 512) | |
859 | var->xres_virtual = 512 * 8 / bpp; | |
860 | else if (line_length <= 1024) | |
861 | var->xres_virtual = 1024 * 8 / bpp; | |
862 | else if (line_length <= 2048) | |
863 | var->xres_virtual = 2048 * 8 / bpp; | |
864 | else if (line_length <= 4096) | |
865 | var->xres_virtual = 4096 * 8 / bpp; | |
866 | else if (line_length <= 8192) | |
867 | var->xres_virtual = 8192 * 8 / bpp; | |
49b1f4b4 KH |
868 | else |
869 | return -EINVAL; | |
bcac2d5f KH |
870 | |
871 | line_length = var->xres_virtual * bpp / 8; | |
872 | } | |
01a2d9ed | 873 | |
f330c4b1 KH |
874 | /* datasheet specifies how to set panning only up to 4 MB */ |
875 | if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) | |
876 | var->yres_virtual = ((4 << 20) / line_length) + var->yres; | |
877 | ||
bcac2d5f | 878 | if (line_length * var->yres_virtual > info->fix.smem_len) |
1da177e4 LT |
879 | return -EINVAL; |
880 | ||
881 | switch (bpp) { | |
245a2c2c KH |
882 | case 8: |
883 | var->red.offset = 0; | |
a4af1798 KH |
884 | var->red.length = 8; |
885 | var->green = var->red; | |
886 | var->blue = var->red; | |
245a2c2c KH |
887 | break; |
888 | case 16: | |
889 | var->red.offset = 11; | |
890 | var->green.offset = 5; | |
891 | var->blue.offset = 0; | |
892 | var->red.length = 5; | |
893 | var->green.length = 6; | |
894 | var->blue.length = 5; | |
895 | break; | |
896 | case 32: | |
897 | var->red.offset = 16; | |
898 | var->green.offset = 8; | |
899 | var->blue.offset = 0; | |
900 | var->red.length = 8; | |
901 | var->green.length = 8; | |
902 | var->blue.length = 8; | |
903 | break; | |
904 | default: | |
905 | return -EINVAL; | |
1da177e4 | 906 | } |
74a933fe KH |
907 | |
908 | if (is_xp(par->chip_id)) | |
909 | ramdac = 350000; | |
910 | ||
911 | switch (par->chip_id) { | |
912 | case TGUI9440: | |
54f019e5 | 913 | ramdac = (bpp >= 16) ? 45000 : 90000; |
74a933fe KH |
914 | break; |
915 | case CYBER9320: | |
916 | case TGUI9660: | |
917 | ramdac = 135000; | |
918 | break; | |
919 | case PROVIDIA9685: | |
920 | case CYBER9388: | |
921 | case CYBER9382: | |
922 | case CYBER9385: | |
923 | ramdac = 170000; | |
924 | break; | |
925 | } | |
926 | ||
927 | /* The clock is doubled for 32 bpp */ | |
928 | if (bpp == 32) | |
929 | ramdac /= 2; | |
930 | ||
931 | if (PICOS2KHZ(var->pixclock) > ramdac) | |
932 | return -EINVAL; | |
933 | ||
1da177e4 LT |
934 | debug("exit\n"); |
935 | ||
936 | return 0; | |
937 | ||
938 | } | |
245a2c2c | 939 | |
1da177e4 LT |
940 | /* Pan the display */ |
941 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | |
245a2c2c | 942 | struct fb_info *info) |
1da177e4 | 943 | { |
306fa6f6 | 944 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
945 | unsigned int offset; |
946 | ||
947 | debug("enter\n"); | |
bcac2d5f | 948 | offset = (var->xoffset + (var->yoffset * var->xres_virtual)) |
245a2c2c | 949 | * var->bits_per_pixel / 32; |
306fa6f6 | 950 | set_screen_start(par, offset); |
1da177e4 LT |
951 | debug("exit\n"); |
952 | return 0; | |
953 | } | |
954 | ||
5cf13845 | 955 | static inline void shadowmode_on(struct tridentfb_par *par) |
306fa6f6 KH |
956 | { |
957 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | |
958 | } | |
959 | ||
5cf13845 | 960 | static inline void shadowmode_off(struct tridentfb_par *par) |
306fa6f6 KH |
961 | { |
962 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | |
963 | } | |
1da177e4 LT |
964 | |
965 | /* Set the hardware to the requested video mode */ | |
966 | static int tridentfb_set_par(struct fb_info *info) | |
967 | { | |
5cf13845 | 968 | struct tridentfb_par *par = info->par; |
245a2c2c KH |
969 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; |
970 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | |
971 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 LT |
972 | int bpp = var->bits_per_pixel; |
973 | unsigned char tmp; | |
3f275ea3 KH |
974 | unsigned long vclk; |
975 | ||
1da177e4 | 976 | debug("enter\n"); |
245a2c2c | 977 | hdispend = var->xres / 8 - 1; |
34dec243 KH |
978 | hsyncstart = (var->xres + var->right_margin) / 8; |
979 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; | |
7f762d23 KH |
980 | htotal = (var->xres + var->left_margin + var->right_margin + |
981 | var->hsync_len) / 8 - 5; | |
0e73a47f | 982 | hblankstart = hdispend + 1; |
7f762d23 | 983 | hblankend = htotal + 3; |
1da177e4 | 984 | |
1da177e4 LT |
985 | vdispend = var->yres - 1; |
986 | vsyncstart = var->yres + var->lower_margin; | |
7f762d23 KH |
987 | vsyncend = vsyncstart + var->vsync_len; |
988 | vtotal = var->upper_margin + vsyncend - 2; | |
0e73a47f | 989 | vblankstart = vdispend + 1; |
7f762d23 | 990 | vblankend = vtotal; |
1da177e4 | 991 | |
34dec243 KH |
992 | if (info->var.vmode & FB_VMODE_INTERLACED) { |
993 | vtotal /= 2; | |
994 | vdispend /= 2; | |
995 | vsyncstart /= 2; | |
996 | vsyncend /= 2; | |
997 | vblankstart /= 2; | |
998 | vblankend /= 2; | |
999 | } | |
1000 | ||
13b0de49 | 1001 | enable_mmio(par); |
306fa6f6 KH |
1002 | crtc_unlock(par); |
1003 | write3CE(par, CyberControl, 8); | |
34dec243 KH |
1004 | tmp = 0xEB; |
1005 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | |
1006 | tmp &= ~0x40; | |
1007 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | |
1008 | tmp &= ~0x80; | |
1da177e4 | 1009 | |
6eed8e1e | 1010 | if (par->flatpanel && var->xres < nativex) { |
1da177e4 LT |
1011 | /* |
1012 | * on flat panels with native size larger | |
1013 | * than requested resolution decide whether | |
1014 | * we stretch or center | |
1015 | */ | |
34dec243 | 1016 | t_outb(par, tmp | 0xC0, VGA_MIS_W); |
1da177e4 | 1017 | |
306fa6f6 | 1018 | shadowmode_on(par); |
1da177e4 | 1019 | |
245a2c2c | 1020 | if (center) |
306fa6f6 | 1021 | screen_center(par); |
1da177e4 | 1022 | else if (stretch) |
306fa6f6 | 1023 | screen_stretch(par); |
1da177e4 LT |
1024 | |
1025 | } else { | |
34dec243 | 1026 | t_outb(par, tmp, VGA_MIS_W); |
306fa6f6 | 1027 | write3CE(par, CyberControl, 8); |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | /* vertical timing values */ | |
10172ed6 KH |
1031 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); |
1032 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); | |
1033 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); | |
1034 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); | |
1035 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); | |
7f762d23 | 1036 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); |
1da177e4 LT |
1037 | |
1038 | /* horizontal timing values */ | |
10172ed6 KH |
1039 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); |
1040 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); | |
1041 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); | |
1042 | write3X4(par, VGA_CRTC_H_SYNC_END, | |
306fa6f6 | 1043 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); |
10172ed6 | 1044 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); |
7f762d23 | 1045 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); |
1da177e4 LT |
1046 | |
1047 | /* higher bits of vertical timing values */ | |
1048 | tmp = 0x10; | |
1049 | if (vtotal & 0x100) tmp |= 0x01; | |
1050 | if (vdispend & 0x100) tmp |= 0x02; | |
1051 | if (vsyncstart & 0x100) tmp |= 0x04; | |
1052 | if (vblankstart & 0x100) tmp |= 0x08; | |
1053 | ||
1054 | if (vtotal & 0x200) tmp |= 0x20; | |
1055 | if (vdispend & 0x200) tmp |= 0x40; | |
1056 | if (vsyncstart & 0x200) tmp |= 0x80; | |
10172ed6 | 1057 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); |
1da177e4 | 1058 | |
7f762d23 KH |
1059 | tmp = read3X4(par, CRTHiOrd) & 0x07; |
1060 | tmp |= 0x08; /* line compare bit 10 */ | |
1da177e4 LT |
1061 | if (vtotal & 0x400) tmp |= 0x80; |
1062 | if (vblankstart & 0x400) tmp |= 0x40; | |
1063 | if (vsyncstart & 0x400) tmp |= 0x20; | |
1064 | if (vdispend & 0x400) tmp |= 0x10; | |
306fa6f6 | 1065 | write3X4(par, CRTHiOrd, tmp); |
1da177e4 | 1066 | |
7f762d23 KH |
1067 | tmp = (htotal >> 8) & 0x01; |
1068 | tmp |= (hdispend >> 7) & 0x02; | |
1069 | tmp |= (hsyncstart >> 5) & 0x08; | |
1070 | tmp |= (hblankstart >> 4) & 0x10; | |
306fa6f6 | 1071 | write3X4(par, HorizOverflow, tmp); |
245a2c2c | 1072 | |
1da177e4 LT |
1073 | tmp = 0x40; |
1074 | if (vblankstart & 0x200) tmp |= 0x20; | |
245a2c2c | 1075 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ |
10172ed6 | 1076 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); |
1da177e4 | 1077 | |
10172ed6 KH |
1078 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); |
1079 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); | |
1080 | write3X4(par, VGA_CRTC_MODE, 0xC3); | |
1da177e4 | 1081 | |
306fa6f6 | 1082 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ |
1da177e4 | 1083 | |
245a2c2c | 1084 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; |
306fa6f6 KH |
1085 | /* enable access extended memory */ |
1086 | write3X4(par, CRTCModuleTest, tmp); | |
34dec243 KH |
1087 | tmp = read3CE(par, MiscIntContReg) & ~0x4; |
1088 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
1089 | tmp |= 0x4; | |
1090 | write3CE(par, MiscIntContReg, tmp); | |
1da177e4 | 1091 | |
306fa6f6 KH |
1092 | /* enable GE for text acceleration */ |
1093 | write3X4(par, GraphEngReg, 0x80); | |
1da177e4 | 1094 | |
1da177e4 | 1095 | switch (bpp) { |
245a2c2c KH |
1096 | case 8: |
1097 | tmp = 0x00; | |
1098 | break; | |
1099 | case 16: | |
1100 | tmp = 0x05; | |
1101 | break; | |
1102 | case 24: | |
1103 | tmp = 0x29; | |
1104 | break; | |
1105 | case 32: | |
1106 | tmp = 0x09; | |
1107 | break; | |
1da177e4 LT |
1108 | } |
1109 | ||
306fa6f6 | 1110 | write3X4(par, PixelBusReg, tmp); |
1da177e4 | 1111 | |
0e73a47f KH |
1112 | tmp = read3X4(par, DRAMControl); |
1113 | if (!is_oldprotect(par->chip_id)) | |
1114 | tmp |= 0x10; | |
122e8ad3 | 1115 | if (iscyber(par->chip_id)) |
245a2c2c | 1116 | tmp |= 0x20; |
306fa6f6 | 1117 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ |
1da177e4 | 1118 | |
306fa6f6 | 1119 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); |
0e73a47f KH |
1120 | if (!is_xp(par->chip_id)) |
1121 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); | |
306fa6f6 | 1122 | /* MMIO & PCI read and write burst enable */ |
13b0de49 | 1123 | if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) |
a0d92256 | 1124 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); |
1da177e4 | 1125 | |
10172ed6 KH |
1126 | vga_mm_wseq(par->io_virt, 0, 3); |
1127 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | |
306fa6f6 | 1128 | /* enable 4 maps because needed in chain4 mode */ |
10172ed6 KH |
1129 | vga_mm_wseq(par->io_virt, 2, 0x0F); |
1130 | vga_mm_wseq(par->io_virt, 3, 0); | |
1131 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | |
1da177e4 | 1132 | |
54f019e5 KH |
1133 | /* convert from picoseconds to kHz */ |
1134 | vclk = PICOS2KHZ(info->var.pixclock); | |
1135 | ||
306fa6f6 | 1136 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ |
65e93e03 | 1137 | tmp = read3CE(par, MiscExtFunc) & 0xF0; |
54f019e5 | 1138 | if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { |
65e93e03 | 1139 | tmp |= 8; |
54f019e5 KH |
1140 | vclk *= 2; |
1141 | } | |
1142 | set_vclk(par, vclk); | |
65e93e03 | 1143 | write3CE(par, MiscExtFunc, tmp | 0x12); |
306fa6f6 KH |
1144 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ |
1145 | write3CE(par, 0x6, 0x05); /* graphics mode */ | |
1146 | write3CE(par, 0x7, 0x0F); /* planes? */ | |
1da177e4 | 1147 | |
306fa6f6 KH |
1148 | /* graphics mode and support 256 color modes */ |
1149 | writeAttr(par, 0x10, 0x41); | |
1150 | writeAttr(par, 0x12, 0x0F); /* planes */ | |
1151 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | |
1da177e4 | 1152 | |
245a2c2c KH |
1153 | /* colors */ |
1154 | for (tmp = 0; tmp < 0x10; tmp++) | |
306fa6f6 | 1155 | writeAttr(par, tmp, tmp); |
10172ed6 KH |
1156 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
1157 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ | |
1da177e4 LT |
1158 | |
1159 | switch (bpp) { | |
245a2c2c KH |
1160 | case 8: |
1161 | tmp = 0; | |
1162 | break; | |
245a2c2c KH |
1163 | case 16: |
1164 | tmp = 0x30; | |
1165 | break; | |
1166 | case 24: | |
1167 | case 32: | |
1168 | tmp = 0xD0; | |
1169 | break; | |
1da177e4 LT |
1170 | } |
1171 | ||
10172ed6 KH |
1172 | t_inb(par, VGA_PEL_IW); |
1173 | t_inb(par, VGA_PEL_MSK); | |
1174 | t_inb(par, VGA_PEL_MSK); | |
1175 | t_inb(par, VGA_PEL_MSK); | |
1176 | t_inb(par, VGA_PEL_MSK); | |
1177 | t_outb(par, tmp, VGA_PEL_MSK); | |
1178 | t_inb(par, VGA_PEL_IW); | |
1da177e4 | 1179 | |
6eed8e1e | 1180 | if (par->flatpanel) |
306fa6f6 | 1181 | set_number_of_lines(par, info->var.yres); |
bcac2d5f KH |
1182 | info->fix.line_length = info->var.xres_virtual * bpp / 8; |
1183 | set_lwidth(par, info->fix.line_length / 8); | |
01a2d9ed KH |
1184 | |
1185 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1186 | par->init_accel(par, info->var.xres_virtual, bpp); | |
2c86a0c2 | 1187 | |
1da177e4 | 1188 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
245a2c2c | 1189 | info->cmap.len = (bpp == 8) ? 256 : 16; |
1da177e4 LT |
1190 | debug("exit\n"); |
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | /* Set one color register */ | |
1195 | static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
245a2c2c KH |
1196 | unsigned blue, unsigned transp, |
1197 | struct fb_info *info) | |
1da177e4 LT |
1198 | { |
1199 | int bpp = info->var.bits_per_pixel; | |
306fa6f6 | 1200 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1201 | |
1202 | if (regno >= info->cmap.len) | |
1203 | return 1; | |
1204 | ||
973d9ab2 | 1205 | if (bpp == 8) { |
10172ed6 KH |
1206 | t_outb(par, 0xFF, VGA_PEL_MSK); |
1207 | t_outb(par, regno, VGA_PEL_IW); | |
1da177e4 | 1208 | |
10172ed6 KH |
1209 | t_outb(par, red >> 10, VGA_PEL_D); |
1210 | t_outb(par, green >> 10, VGA_PEL_D); | |
1211 | t_outb(par, blue >> 10, VGA_PEL_D); | |
1da177e4 | 1212 | |
973d9ab2 AD |
1213 | } else if (regno < 16) { |
1214 | if (bpp == 16) { /* RGB 565 */ | |
1215 | u32 col; | |
1216 | ||
1217 | col = (red & 0xF800) | ((green & 0xFC00) >> 5) | | |
1218 | ((blue & 0xF800) >> 11); | |
1219 | col |= col << 16; | |
1220 | ((u32 *)(info->pseudo_palette))[regno] = col; | |
1221 | } else if (bpp == 32) /* ARGB 8888 */ | |
5cf13845 | 1222 | ((u32 *)info->pseudo_palette)[regno] = |
245a2c2c KH |
1223 | ((transp & 0xFF00) << 16) | |
1224 | ((red & 0xFF00) << 8) | | |
973d9ab2 | 1225 | ((green & 0xFF00)) | |
245a2c2c | 1226 | ((blue & 0xFF00) >> 8); |
973d9ab2 | 1227 | } |
1da177e4 | 1228 | |
1da177e4 LT |
1229 | return 0; |
1230 | } | |
1231 | ||
5cf13845 | 1232 | /* Try blanking the screen. For flat panels it does nothing */ |
1da177e4 LT |
1233 | static int tridentfb_blank(int blank_mode, struct fb_info *info) |
1234 | { | |
245a2c2c | 1235 | unsigned char PMCont, DPMSCont; |
306fa6f6 | 1236 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1237 | |
1238 | debug("enter\n"); | |
6eed8e1e | 1239 | if (par->flatpanel) |
1da177e4 | 1240 | return 0; |
306fa6f6 KH |
1241 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ |
1242 | PMCont = t_inb(par, 0x83C6) & 0xFC; | |
1243 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; | |
245a2c2c | 1244 | switch (blank_mode) { |
1da177e4 LT |
1245 | case FB_BLANK_UNBLANK: |
1246 | /* Screen: On, HSync: On, VSync: On */ | |
1247 | case FB_BLANK_NORMAL: | |
1248 | /* Screen: Off, HSync: On, VSync: On */ | |
1249 | PMCont |= 0x03; | |
1250 | DPMSCont |= 0x00; | |
1251 | break; | |
1252 | case FB_BLANK_HSYNC_SUSPEND: | |
1253 | /* Screen: Off, HSync: Off, VSync: On */ | |
1254 | PMCont |= 0x02; | |
1255 | DPMSCont |= 0x01; | |
1256 | break; | |
1257 | case FB_BLANK_VSYNC_SUSPEND: | |
1258 | /* Screen: Off, HSync: On, VSync: Off */ | |
1259 | PMCont |= 0x02; | |
1260 | DPMSCont |= 0x02; | |
1261 | break; | |
1262 | case FB_BLANK_POWERDOWN: | |
1263 | /* Screen: Off, HSync: Off, VSync: Off */ | |
1264 | PMCont |= 0x00; | |
1265 | DPMSCont |= 0x03; | |
1266 | break; | |
245a2c2c | 1267 | } |
1da177e4 | 1268 | |
306fa6f6 KH |
1269 | write3CE(par, PowerStatus, DPMSCont); |
1270 | t_outb(par, 4, 0x83C8); | |
1271 | t_outb(par, PMCont, 0x83C6); | |
1da177e4 LT |
1272 | |
1273 | debug("exit\n"); | |
1274 | ||
1275 | /* let fbcon do a softblank for us */ | |
1276 | return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; | |
1277 | } | |
1278 | ||
245a2c2c KH |
1279 | static struct fb_ops tridentfb_ops = { |
1280 | .owner = THIS_MODULE, | |
1281 | .fb_setcolreg = tridentfb_setcolreg, | |
1282 | .fb_pan_display = tridentfb_pan_display, | |
1283 | .fb_blank = tridentfb_blank, | |
1284 | .fb_check_var = tridentfb_check_var, | |
1285 | .fb_set_par = tridentfb_set_par, | |
1286 | .fb_fillrect = tridentfb_fillrect, | |
1287 | .fb_copyarea = tridentfb_copyarea, | |
1288 | .fb_imageblit = cfb_imageblit, | |
49b1f4b4 KH |
1289 | #ifdef CONFIG_FB_TRIDENT_ACCEL |
1290 | .fb_sync = tridentfb_sync, | |
bcac2d5f | 1291 | #endif |
245a2c2c KH |
1292 | }; |
1293 | ||
e09ed099 KH |
1294 | static int __devinit trident_pci_probe(struct pci_dev *dev, |
1295 | const struct pci_device_id *id) | |
1da177e4 LT |
1296 | { |
1297 | int err; | |
1298 | unsigned char revision; | |
e09ed099 KH |
1299 | struct fb_info *info; |
1300 | struct tridentfb_par *default_par; | |
122e8ad3 KH |
1301 | int chip3D; |
1302 | int chip_id; | |
1da177e4 LT |
1303 | |
1304 | err = pci_enable_device(dev); | |
1305 | if (err) | |
1306 | return err; | |
1307 | ||
e09ed099 KH |
1308 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); |
1309 | if (!info) | |
1310 | return -ENOMEM; | |
1311 | default_par = info->par; | |
1312 | ||
1da177e4 LT |
1313 | chip_id = id->device; |
1314 | ||
245a2c2c | 1315 | if (chip_id == CYBERBLADEi1) |
9fa68eae KP |
1316 | output("*** Please do use cyblafb, Cyberblade/i1 support " |
1317 | "will soon be removed from tridentfb!\n"); | |
1318 | ||
01a2d9ed KH |
1319 | #ifndef CONFIG_FB_TRIDENT_ACCEL |
1320 | noaccel = 1; | |
1321 | #endif | |
9fa68eae | 1322 | |
1da177e4 | 1323 | /* If PCI id is 0x9660 then further detect chip type */ |
245a2c2c | 1324 | |
1da177e4 | 1325 | if (chip_id == TGUI9660) { |
10172ed6 | 1326 | revision = vga_io_rseq(RevisionID); |
245a2c2c | 1327 | |
1da177e4 | 1328 | switch (revision) { |
0e73a47f KH |
1329 | case 0x21: |
1330 | chip_id = PROVIDIA9685; | |
1331 | break; | |
245a2c2c KH |
1332 | case 0x22: |
1333 | case 0x23: | |
1334 | chip_id = CYBER9397; | |
1335 | break; | |
1336 | case 0x2A: | |
1337 | chip_id = CYBER9397DVD; | |
1338 | break; | |
1339 | case 0x30: | |
1340 | case 0x33: | |
1341 | case 0x34: | |
1342 | case 0x35: | |
1343 | case 0x38: | |
1344 | case 0x3A: | |
1345 | case 0xB3: | |
1346 | chip_id = CYBER9385; | |
1347 | break; | |
1348 | case 0x40 ... 0x43: | |
1349 | chip_id = CYBER9382; | |
1350 | break; | |
1351 | case 0x4A: | |
1352 | chip_id = CYBER9388; | |
1353 | break; | |
1354 | default: | |
1355 | break; | |
1da177e4 LT |
1356 | } |
1357 | } | |
1358 | ||
1359 | chip3D = is3Dchip(chip_id); | |
1da177e4 LT |
1360 | |
1361 | if (is_xp(chip_id)) { | |
d9cad04b KH |
1362 | default_par->init_accel = xp_init_accel; |
1363 | default_par->wait_engine = xp_wait_engine; | |
1364 | default_par->fill_rect = xp_fill_rect; | |
1365 | default_par->copy_rect = xp_copy_rect; | |
01a2d9ed | 1366 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; |
245a2c2c | 1367 | } else if (is_blade(chip_id)) { |
d9cad04b KH |
1368 | default_par->init_accel = blade_init_accel; |
1369 | default_par->wait_engine = blade_wait_engine; | |
1370 | default_par->fill_rect = blade_fill_rect; | |
1371 | default_par->copy_rect = blade_copy_rect; | |
01a2d9ed | 1372 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; |
bcac2d5f | 1373 | } else if (chip3D) { /* 3DImage family left */ |
d9cad04b KH |
1374 | default_par->init_accel = image_init_accel; |
1375 | default_par->wait_engine = image_wait_engine; | |
1376 | default_par->fill_rect = image_fill_rect; | |
1377 | default_par->copy_rect = image_copy_rect; | |
01a2d9ed | 1378 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; |
bcac2d5f KH |
1379 | } else { /* TGUI 9440/96XX family */ |
1380 | default_par->init_accel = tgui_init_accel; | |
1381 | default_par->wait_engine = xp_wait_engine; | |
1382 | default_par->fill_rect = tgui_fill_rect; | |
1383 | default_par->copy_rect = tgui_copy_rect; | |
01a2d9ed | 1384 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; |
1da177e4 LT |
1385 | } |
1386 | ||
122e8ad3 KH |
1387 | default_par->chip_id = chip_id; |
1388 | ||
1da177e4 | 1389 | /* setup MMIO region */ |
245a2c2c | 1390 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); |
5cf13845 | 1391 | tridentfb_fix.mmio_len = pci_resource_len(dev, 1); |
1da177e4 | 1392 | |
5cf13845 KH |
1393 | if (!request_mem_region(tridentfb_fix.mmio_start, |
1394 | tridentfb_fix.mmio_len, "tridentfb")) { | |
1da177e4 | 1395 | debug("request_region failed!\n"); |
3876ae8b | 1396 | framebuffer_release(info); |
1da177e4 LT |
1397 | return -1; |
1398 | } | |
1399 | ||
e09ed099 KH |
1400 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, |
1401 | tridentfb_fix.mmio_len); | |
1da177e4 | 1402 | |
e09ed099 | 1403 | if (!default_par->io_virt) { |
1da177e4 | 1404 | debug("ioremap failed\n"); |
e8ed857c KH |
1405 | err = -1; |
1406 | goto out_unmap1; | |
1da177e4 LT |
1407 | } |
1408 | ||
13b0de49 | 1409 | enable_mmio(default_par); |
bcac2d5f | 1410 | |
1da177e4 | 1411 | /* setup framebuffer memory */ |
245a2c2c | 1412 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); |
e09ed099 | 1413 | tridentfb_fix.smem_len = get_memsize(default_par); |
245a2c2c | 1414 | |
5cf13845 KH |
1415 | if (!request_mem_region(tridentfb_fix.smem_start, |
1416 | tridentfb_fix.smem_len, "tridentfb")) { | |
1da177e4 | 1417 | debug("request_mem_region failed!\n"); |
e09ed099 | 1418 | disable_mmio(info->par); |
a02f6402 | 1419 | err = -1; |
e8ed857c | 1420 | goto out_unmap1; |
1da177e4 LT |
1421 | } |
1422 | ||
e09ed099 KH |
1423 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, |
1424 | tridentfb_fix.smem_len); | |
1da177e4 | 1425 | |
e09ed099 | 1426 | if (!info->screen_base) { |
1da177e4 | 1427 | debug("ioremap failed\n"); |
a02f6402 | 1428 | err = -1; |
e8ed857c | 1429 | goto out_unmap2; |
1da177e4 LT |
1430 | } |
1431 | ||
6eed8e1e | 1432 | default_par->flatpanel = is_flatpanel(default_par); |
1da177e4 | 1433 | |
6eed8e1e | 1434 | if (default_par->flatpanel) |
e09ed099 | 1435 | nativex = get_nativex(default_par); |
1da177e4 | 1436 | |
e09ed099 KH |
1437 | info->fix = tridentfb_fix; |
1438 | info->fbops = &tridentfb_ops; | |
aa0aa8ab | 1439 | info->pseudo_palette = default_par->pseudo_pal; |
1da177e4 | 1440 | |
e09ed099 | 1441 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
01a2d9ed KH |
1442 | if (!noaccel && default_par->init_accel) { |
1443 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | |
1444 | info->flags |= FBINFO_HWACCEL_COPYAREA; | |
1445 | info->flags |= FBINFO_HWACCEL_FILLRECT; | |
1446 | } else | |
1447 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1448 | ||
ea8ee55c | 1449 | if (!fb_find_mode(&info->var, info, |
07f41e45 | 1450 | mode_option, NULL, 0, NULL, bpp)) { |
a02f6402 | 1451 | err = -EINVAL; |
e8ed857c | 1452 | goto out_unmap2; |
a02f6402 | 1453 | } |
e09ed099 | 1454 | err = fb_alloc_cmap(&info->cmap, 256, 0); |
e8ed857c KH |
1455 | if (err < 0) |
1456 | goto out_unmap2; | |
1457 | ||
ea8ee55c | 1458 | info->var.activate |= FB_ACTIVATE_NOW; |
e09ed099 KH |
1459 | info->device = &dev->dev; |
1460 | if (register_framebuffer(info) < 0) { | |
5cf13845 | 1461 | printk(KERN_ERR "tridentfb: could not register framebuffer\n"); |
e09ed099 | 1462 | fb_dealloc_cmap(&info->cmap); |
a02f6402 | 1463 | err = -EINVAL; |
e8ed857c | 1464 | goto out_unmap2; |
1da177e4 LT |
1465 | } |
1466 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | |
ea8ee55c KH |
1467 | info->node, info->fix.id, info->var.xres, |
1468 | info->var.yres, info->var.bits_per_pixel); | |
e09ed099 KH |
1469 | |
1470 | pci_set_drvdata(dev, info); | |
1da177e4 | 1471 | return 0; |
a02f6402 | 1472 | |
e8ed857c | 1473 | out_unmap2: |
e09ed099 KH |
1474 | if (info->screen_base) |
1475 | iounmap(info->screen_base); | |
e8ed857c | 1476 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e09ed099 | 1477 | disable_mmio(info->par); |
e8ed857c | 1478 | out_unmap1: |
e09ed099 KH |
1479 | if (default_par->io_virt) |
1480 | iounmap(default_par->io_virt); | |
e8ed857c | 1481 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 | 1482 | framebuffer_release(info); |
a02f6402 | 1483 | return err; |
1da177e4 LT |
1484 | } |
1485 | ||
245a2c2c | 1486 | static void __devexit trident_pci_remove(struct pci_dev *dev) |
1da177e4 | 1487 | { |
e09ed099 KH |
1488 | struct fb_info *info = pci_get_drvdata(dev); |
1489 | struct tridentfb_par *par = info->par; | |
1490 | ||
1491 | unregister_framebuffer(info); | |
1da177e4 | 1492 | iounmap(par->io_virt); |
e09ed099 | 1493 | iounmap(info->screen_base); |
1da177e4 | 1494 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e8ed857c | 1495 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 KH |
1496 | pci_set_drvdata(dev, NULL); |
1497 | framebuffer_release(info); | |
1da177e4 LT |
1498 | } |
1499 | ||
1500 | /* List of boards that we are trying to support */ | |
1501 | static struct pci_device_id trident_devices[] = { | |
245a2c2c KH |
1502 | {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1503 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1504 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1505 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1506 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1507 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1508 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1509 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
a0d92256 | 1510 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
245a2c2c KH |
1511 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1512 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1513 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1514 | {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1515 | {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1516 | {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1517 | {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1518 | {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1519 | {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1520 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1521 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1522 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 | 1523 | {0,} |
245a2c2c KH |
1524 | }; |
1525 | ||
1526 | MODULE_DEVICE_TABLE(pci, trident_devices); | |
1da177e4 LT |
1527 | |
1528 | static struct pci_driver tridentfb_pci_driver = { | |
245a2c2c KH |
1529 | .name = "tridentfb", |
1530 | .id_table = trident_devices, | |
1531 | .probe = trident_pci_probe, | |
1532 | .remove = __devexit_p(trident_pci_remove) | |
1da177e4 LT |
1533 | }; |
1534 | ||
1535 | /* | |
1536 | * Parse user specified options (`video=trident:') | |
1537 | * example: | |
245a2c2c | 1538 | * video=trident:800x600,bpp=16,noaccel |
1da177e4 LT |
1539 | */ |
1540 | #ifndef MODULE | |
07f41e45 | 1541 | static int __init tridentfb_setup(char *options) |
1da177e4 | 1542 | { |
245a2c2c | 1543 | char *opt; |
1da177e4 LT |
1544 | if (!options || !*options) |
1545 | return 0; | |
245a2c2c KH |
1546 | while ((opt = strsep(&options, ",")) != NULL) { |
1547 | if (!*opt) | |
1548 | continue; | |
1549 | if (!strncmp(opt, "noaccel", 7)) | |
1da177e4 | 1550 | noaccel = 1; |
245a2c2c | 1551 | else if (!strncmp(opt, "fp", 2)) |
6eed8e1e | 1552 | fp = 1; |
245a2c2c | 1553 | else if (!strncmp(opt, "crt", 3)) |
6eed8e1e | 1554 | fp = 0; |
245a2c2c KH |
1555 | else if (!strncmp(opt, "bpp=", 4)) |
1556 | bpp = simple_strtoul(opt + 4, NULL, 0); | |
1557 | else if (!strncmp(opt, "center", 6)) | |
1da177e4 | 1558 | center = 1; |
245a2c2c | 1559 | else if (!strncmp(opt, "stretch", 7)) |
1da177e4 | 1560 | stretch = 1; |
245a2c2c KH |
1561 | else if (!strncmp(opt, "memsize=", 8)) |
1562 | memsize = simple_strtoul(opt + 8, NULL, 0); | |
1563 | else if (!strncmp(opt, "memdiff=", 8)) | |
1564 | memdiff = simple_strtoul(opt + 8, NULL, 0); | |
1565 | else if (!strncmp(opt, "nativex=", 8)) | |
1566 | nativex = simple_strtoul(opt + 8, NULL, 0); | |
1da177e4 | 1567 | else |
07f41e45 | 1568 | mode_option = opt; |
1da177e4 LT |
1569 | } |
1570 | return 0; | |
1571 | } | |
1572 | #endif | |
1573 | ||
1574 | static int __init tridentfb_init(void) | |
1575 | { | |
1576 | #ifndef MODULE | |
1577 | char *option = NULL; | |
1578 | ||
1579 | if (fb_get_options("tridentfb", &option)) | |
1580 | return -ENODEV; | |
1581 | tridentfb_setup(option); | |
1582 | #endif | |
1da177e4 LT |
1583 | return pci_register_driver(&tridentfb_pci_driver); |
1584 | } | |
1585 | ||
1586 | static void __exit tridentfb_exit(void) | |
1587 | { | |
1588 | pci_unregister_driver(&tridentfb_pci_driver); | |
1589 | } | |
1590 | ||
1da177e4 LT |
1591 | module_init(tridentfb_init); |
1592 | module_exit(tridentfb_exit); | |
1593 | ||
1594 | MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); | |
1595 | MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); | |
1596 | MODULE_LICENSE("GPL"); | |
1597 |