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d61e0bf3 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #include "global.h" | |
23 | ||
d61e0bf3 | 24 | static struct pll_map pll_value[] = { |
0306ab11 HW |
25 | {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, |
26 | CX700_25_175M, VX855_25_175M}, | |
27 | {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, | |
28 | CX700_29_581M, VX855_29_581M}, | |
29 | {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, | |
30 | CX700_26_880M, VX855_26_880M}, | |
31 | {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, | |
32 | CX700_31_490M, VX855_31_490M}, | |
33 | {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, | |
34 | CX700_31_500M, VX855_31_500M}, | |
35 | {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, | |
36 | CX700_31_728M, VX855_31_728M}, | |
37 | {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, | |
38 | CX700_32_668M, VX855_32_668M}, | |
39 | {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, | |
40 | CX700_36_000M, VX855_36_000M}, | |
41 | {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, | |
42 | CX700_40_000M, VX855_40_000M}, | |
43 | {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, | |
44 | CX700_41_291M, VX855_41_291M}, | |
45 | {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, | |
46 | CX700_43_163M, VX855_43_163M}, | |
47 | {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, | |
48 | CX700_45_250M, VX855_45_250M}, | |
49 | {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, | |
50 | CX700_46_000M, VX855_46_000M}, | |
51 | {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, | |
52 | CX700_46_996M, VX855_46_996M}, | |
53 | {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, | |
54 | CX700_48_000M, VX855_48_000M}, | |
55 | {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, | |
56 | CX700_48_875M, VX855_48_875M}, | |
57 | {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, | |
58 | CX700_49_500M, VX855_49_500M}, | |
59 | {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, | |
60 | CX700_52_406M, VX855_52_406M}, | |
61 | {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, | |
62 | CX700_52_977M, VX855_52_977M}, | |
63 | {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, | |
64 | CX700_56_250M, VX855_56_250M}, | |
c205d932 | 65 | {CLK_57_275M, 0, 0, 0, VX855_57_275M}, |
0306ab11 HW |
66 | {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, |
67 | CX700_60_466M, VX855_60_466M}, | |
68 | {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, | |
69 | CX700_61_500M, VX855_61_500M}, | |
70 | {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, | |
71 | CX700_65_000M, VX855_65_000M}, | |
72 | {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, | |
73 | CX700_65_178M, VX855_65_178M}, | |
74 | {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, | |
75 | CX700_66_750M, VX855_66_750M}, | |
76 | {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, | |
77 | CX700_68_179M, VX855_68_179M}, | |
78 | {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, | |
79 | CX700_69_924M, VX855_69_924M}, | |
80 | {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, | |
81 | CX700_70_159M, VX855_70_159M}, | |
82 | {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, | |
83 | CX700_72_000M, VX855_72_000M}, | |
84 | {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, | |
85 | CX700_78_750M, VX855_78_750M}, | |
86 | {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, | |
87 | CX700_80_136M, VX855_80_136M}, | |
88 | {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, | |
89 | CX700_83_375M, VX855_83_375M}, | |
90 | {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, | |
91 | CX700_83_950M, VX855_83_950M}, | |
92 | {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, | |
93 | CX700_84_750M, VX855_84_750M}, | |
94 | {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, | |
95 | CX700_85_860M, VX855_85_860M}, | |
96 | {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, | |
97 | CX700_88_750M, VX855_88_750M}, | |
98 | {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, | |
99 | CX700_94_500M, VX855_94_500M}, | |
100 | {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, | |
101 | CX700_97_750M, VX855_97_750M}, | |
d61e0bf3 | 102 | {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M, |
0306ab11 | 103 | CX700_101_000M, VX855_101_000M}, |
d61e0bf3 | 104 | {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M, |
0306ab11 | 105 | CX700_106_500M, VX855_106_500M}, |
d61e0bf3 | 106 | {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M, |
0306ab11 | 107 | CX700_108_000M, VX855_108_000M}, |
d61e0bf3 | 108 | {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M, |
0306ab11 | 109 | CX700_113_309M, VX855_113_309M}, |
d61e0bf3 | 110 | {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M, |
0306ab11 | 111 | CX700_118_840M, VX855_118_840M}, |
d61e0bf3 | 112 | {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M, |
0306ab11 | 113 | CX700_119_000M, VX855_119_000M}, |
d61e0bf3 | 114 | {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M, |
0306ab11 | 115 | CX700_121_750M, 0}, |
d61e0bf3 | 116 | {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M, |
0306ab11 | 117 | CX700_125_104M, 0}, |
d61e0bf3 | 118 | {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M, |
0306ab11 | 119 | CX700_133_308M, 0}, |
d61e0bf3 | 120 | {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M, |
0306ab11 | 121 | CX700_135_000M, VX855_135_000M}, |
d61e0bf3 | 122 | {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M, |
0306ab11 | 123 | CX700_136_700M, VX855_136_700M}, |
d61e0bf3 | 124 | {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M, |
0306ab11 | 125 | CX700_138_400M, VX855_138_400M}, |
d61e0bf3 | 126 | {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M, |
0306ab11 | 127 | CX700_146_760M, VX855_146_760M}, |
d61e0bf3 | 128 | {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M, |
0306ab11 | 129 | CX700_153_920M, VX855_153_920M}, |
d61e0bf3 | 130 | {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M, |
0306ab11 | 131 | CX700_156_000M, VX855_156_000M}, |
d61e0bf3 | 132 | {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M, |
0306ab11 | 133 | CX700_157_500M, VX855_157_500M}, |
d61e0bf3 | 134 | {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M, |
0306ab11 | 135 | CX700_162_000M, VX855_162_000M}, |
d61e0bf3 | 136 | {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M, |
0306ab11 | 137 | CX700_187_000M, VX855_187_000M}, |
d61e0bf3 | 138 | {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M, |
0306ab11 | 139 | CX700_193_295M, VX855_193_295M}, |
d61e0bf3 | 140 | {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M, |
0306ab11 | 141 | CX700_202_500M, VX855_202_500M}, |
d61e0bf3 | 142 | {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M, |
0306ab11 | 143 | CX700_204_000M, VX855_204_000M}, |
d61e0bf3 | 144 | {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M, |
0306ab11 | 145 | CX700_218_500M, VX855_218_500M}, |
d61e0bf3 | 146 | {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M, |
0306ab11 | 147 | CX700_234_000M, VX855_234_000M}, |
d61e0bf3 | 148 | {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M, |
0306ab11 | 149 | CX700_267_250M, VX855_267_250M}, |
d61e0bf3 | 150 | {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M, |
0306ab11 HW |
151 | CX700_297_500M, VX855_297_500M}, |
152 | {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, | |
153 | CX700_74_481M, VX855_74_481M}, | |
d61e0bf3 | 154 | {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M, |
0306ab11 | 155 | CX700_172_798M, VX855_172_798M}, |
d61e0bf3 | 156 | {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M, |
0306ab11 HW |
157 | CX700_122_614M, VX855_122_614M}, |
158 | {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, | |
159 | CX700_74_270M, 0}, | |
d61e0bf3 | 160 | {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M, |
0306ab11 | 161 | CX700_148_500M, VX855_148_500M} |
d61e0bf3 JC |
162 | }; |
163 | ||
164 | static struct fifo_depth_select display_fifo_depth_reg = { | |
165 | /* IGA1 FIFO Depth_Select */ | |
166 | {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } }, | |
167 | /* IGA2 FIFO Depth_Select */ | |
168 | {IGA2_FIFO_DEPTH_SELECT_REG_NUM, | |
169 | {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } } | |
170 | }; | |
171 | ||
172 | static struct fifo_threshold_select fifo_threshold_select_reg = { | |
173 | /* IGA1 FIFO Threshold Select */ | |
174 | {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } }, | |
175 | /* IGA2 FIFO Threshold Select */ | |
176 | {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } } | |
177 | }; | |
178 | ||
179 | static struct fifo_high_threshold_select fifo_high_threshold_select_reg = { | |
180 | /* IGA1 FIFO High Threshold Select */ | |
181 | {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } }, | |
182 | /* IGA2 FIFO High Threshold Select */ | |
183 | {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } } | |
184 | }; | |
185 | ||
186 | static struct display_queue_expire_num display_queue_expire_num_reg = { | |
187 | /* IGA1 Display Queue Expire Num */ | |
188 | {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } }, | |
189 | /* IGA2 Display Queue Expire Num */ | |
190 | {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } } | |
191 | }; | |
192 | ||
193 | /* Definition Fetch Count Registers*/ | |
194 | static struct fetch_count fetch_count_reg = { | |
195 | /* IGA1 Fetch Count Register */ | |
196 | {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } }, | |
197 | /* IGA2 Fetch Count Register */ | |
198 | {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } } | |
199 | }; | |
200 | ||
201 | static struct iga1_crtc_timing iga1_crtc_reg = { | |
202 | /* IGA1 Horizontal Total */ | |
203 | {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } }, | |
204 | /* IGA1 Horizontal Addressable Video */ | |
205 | {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } }, | |
206 | /* IGA1 Horizontal Blank Start */ | |
207 | {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } }, | |
208 | /* IGA1 Horizontal Blank End */ | |
209 | {IGA1_HOR_BLANK_END_REG_NUM, | |
210 | {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } }, | |
211 | /* IGA1 Horizontal Sync Start */ | |
212 | {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } }, | |
213 | /* IGA1 Horizontal Sync End */ | |
214 | {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } }, | |
215 | /* IGA1 Vertical Total */ | |
216 | {IGA1_VER_TOTAL_REG_NUM, | |
217 | {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } }, | |
218 | /* IGA1 Vertical Addressable Video */ | |
219 | {IGA1_VER_ADDR_REG_NUM, | |
220 | {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } }, | |
221 | /* IGA1 Vertical Blank Start */ | |
222 | {IGA1_VER_BLANK_START_REG_NUM, | |
223 | {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } }, | |
224 | /* IGA1 Vertical Blank End */ | |
225 | {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } }, | |
226 | /* IGA1 Vertical Sync Start */ | |
227 | {IGA1_VER_SYNC_START_REG_NUM, | |
228 | {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } }, | |
229 | /* IGA1 Vertical Sync End */ | |
230 | {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } } | |
231 | }; | |
232 | ||
233 | static struct iga2_crtc_timing iga2_crtc_reg = { | |
234 | /* IGA2 Horizontal Total */ | |
235 | {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } }, | |
236 | /* IGA2 Horizontal Addressable Video */ | |
237 | {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } }, | |
238 | /* IGA2 Horizontal Blank Start */ | |
239 | {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } }, | |
240 | /* IGA2 Horizontal Blank End */ | |
241 | {IGA2_HOR_BLANK_END_REG_NUM, | |
242 | {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } }, | |
243 | /* IGA2 Horizontal Sync Start */ | |
244 | {IGA2_HOR_SYNC_START_REG_NUM, | |
245 | {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } }, | |
246 | /* IGA2 Horizontal Sync End */ | |
247 | {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } }, | |
248 | /* IGA2 Vertical Total */ | |
249 | {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } }, | |
250 | /* IGA2 Vertical Addressable Video */ | |
251 | {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } }, | |
252 | /* IGA2 Vertical Blank Start */ | |
253 | {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } }, | |
254 | /* IGA2 Vertical Blank End */ | |
255 | {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } }, | |
256 | /* IGA2 Vertical Sync Start */ | |
257 | {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } }, | |
258 | /* IGA2 Vertical Sync End */ | |
259 | {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } } | |
260 | }; | |
261 | ||
262 | static struct rgbLUT palLUT_table[] = { | |
263 | /* {R,G,B} */ | |
264 | /* Index 0x00~0x03 */ | |
265 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, | |
266 | 0x2A, | |
267 | 0x2A}, | |
268 | /* Index 0x04~0x07 */ | |
269 | {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, | |
270 | 0x2A, | |
271 | 0x2A}, | |
272 | /* Index 0x08~0x0B */ | |
273 | {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, | |
274 | 0x3F, | |
275 | 0x3F}, | |
276 | /* Index 0x0C~0x0F */ | |
277 | {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, | |
278 | 0x3F, | |
279 | 0x3F}, | |
280 | /* Index 0x10~0x13 */ | |
281 | {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, | |
282 | 0x0B, | |
283 | 0x0B}, | |
284 | /* Index 0x14~0x17 */ | |
285 | {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, | |
286 | 0x18, | |
287 | 0x18}, | |
288 | /* Index 0x18~0x1B */ | |
289 | {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, | |
290 | 0x28, | |
291 | 0x28}, | |
292 | /* Index 0x1C~0x1F */ | |
293 | {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, | |
294 | 0x3F, | |
295 | 0x3F}, | |
296 | /* Index 0x20~0x23 */ | |
297 | {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, | |
298 | 0x00, | |
299 | 0x3F}, | |
300 | /* Index 0x24~0x27 */ | |
301 | {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, | |
302 | 0x00, | |
303 | 0x10}, | |
304 | /* Index 0x28~0x2B */ | |
305 | {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, | |
306 | 0x2F, | |
307 | 0x00}, | |
308 | /* Index 0x2C~0x2F */ | |
309 | {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, | |
310 | 0x3F, | |
311 | 0x00}, | |
312 | /* Index 0x30~0x33 */ | |
313 | {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, | |
314 | 0x3F, | |
315 | 0x2F}, | |
316 | /* Index 0x34~0x37 */ | |
317 | {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, | |
318 | 0x10, | |
319 | 0x3F}, | |
320 | /* Index 0x38~0x3B */ | |
321 | {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, | |
322 | 0x1F, | |
323 | 0x3F}, | |
324 | /* Index 0x3C~0x3F */ | |
325 | {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, | |
326 | 0x1F, | |
327 | 0x27}, | |
328 | /* Index 0x40~0x43 */ | |
329 | {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, | |
330 | 0x3F, | |
331 | 0x1F}, | |
332 | /* Index 0x44~0x47 */ | |
333 | {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, | |
334 | 0x3F, | |
335 | 0x1F}, | |
336 | /* Index 0x48~0x4B */ | |
337 | {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, | |
338 | 0x3F, | |
339 | 0x37}, | |
340 | /* Index 0x4C~0x4F */ | |
341 | {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, | |
342 | 0x27, | |
343 | 0x3F}, | |
344 | /* Index 0x50~0x53 */ | |
345 | {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, | |
346 | 0x2D, | |
347 | 0x3F}, | |
348 | /* Index 0x54~0x57 */ | |
349 | {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, | |
350 | 0x2D, | |
351 | 0x31}, | |
352 | /* Index 0x58~0x5B */ | |
353 | {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, | |
354 | 0x3A, | |
355 | 0x2D}, | |
356 | /* Index 0x5C~0x5F */ | |
357 | {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, | |
358 | 0x3F, | |
359 | 0x2D}, | |
360 | /* Index 0x60~0x63 */ | |
361 | {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, | |
362 | 0x3F, | |
363 | 0x3A}, | |
364 | /* Index 0x64~0x67 */ | |
365 | {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, | |
366 | 0x31, | |
367 | 0x3F}, | |
368 | /* Index 0x68~0x6B */ | |
369 | {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, | |
370 | 0x00, | |
371 | 0x1C}, | |
372 | /* Index 0x6C~0x6F */ | |
373 | {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, | |
374 | 0x00, | |
375 | 0x07}, | |
376 | /* Index 0x70~0x73 */ | |
377 | {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, | |
378 | 0x15, | |
379 | 0x00}, | |
380 | /* Index 0x74~0x77 */ | |
381 | {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, | |
382 | 0x1C, | |
383 | 0x00}, | |
384 | /* Index 0x78~0x7B */ | |
385 | {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, | |
386 | 0x1C, | |
387 | 0x15}, | |
388 | /* Index 0x7C~0x7F */ | |
389 | {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, | |
390 | 0x07, | |
391 | 0x1C}, | |
392 | /* Index 0x80~0x83 */ | |
393 | {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, | |
394 | 0x0E, | |
395 | 0x1C}, | |
396 | /* Index 0x84~0x87 */ | |
397 | {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, | |
398 | 0x0E, | |
399 | 0x11}, | |
400 | /* Index 0x88~0x8B */ | |
401 | {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, | |
402 | 0x18, | |
403 | 0x0E}, | |
404 | /* Index 0x8C~0x8F */ | |
405 | {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, | |
406 | 0x1C, | |
407 | 0x0E}, | |
408 | /* Index 0x90~0x93 */ | |
409 | {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, | |
410 | 0x1C, | |
411 | 0x18}, | |
412 | /* Index 0x94~0x97 */ | |
413 | {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, | |
414 | 0x11, | |
415 | 0x1C}, | |
416 | /* Index 0x98~0x9B */ | |
417 | {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, | |
418 | 0x14, | |
419 | 0x1C}, | |
420 | /* Index 0x9C~0x9F */ | |
421 | {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, | |
422 | 0x14, | |
423 | 0x16}, | |
424 | /* Index 0xA0~0xA3 */ | |
425 | {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, | |
426 | 0x1A, | |
427 | 0x14}, | |
428 | /* Index 0xA4~0xA7 */ | |
429 | {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, | |
430 | 0x1C, | |
431 | 0x14}, | |
432 | /* Index 0xA8~0xAB */ | |
433 | {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, | |
434 | 0x1C, | |
435 | 0x1A}, | |
436 | /* Index 0xAC~0xAF */ | |
437 | {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, | |
438 | 0x16, | |
439 | 0x1C}, | |
440 | /* Index 0xB0~0xB3 */ | |
441 | {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, | |
442 | 0x00, | |
443 | 0x10}, | |
444 | /* Index 0xB4~0xB7 */ | |
445 | {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, | |
446 | 0x00, | |
447 | 0x04}, | |
448 | /* Index 0xB8~0xBB */ | |
449 | {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, | |
450 | 0x0C, | |
451 | 0x00}, | |
452 | /* Index 0xBC~0xBF */ | |
453 | {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, | |
454 | 0x10, | |
455 | 0x00}, | |
456 | /* Index 0xC0~0xC3 */ | |
457 | {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, | |
458 | 0x10, | |
459 | 0x0C}, | |
460 | /* Index 0xC4~0xC7 */ | |
461 | {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, | |
462 | 0x04, | |
463 | 0x10}, | |
464 | /* Index 0xC8~0xCB */ | |
465 | {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, | |
466 | 0x08, | |
467 | 0x10}, | |
468 | /* Index 0xCC~0xCF */ | |
469 | {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, | |
470 | 0x08, | |
471 | 0x0A}, | |
472 | /* Index 0xD0~0xD3 */ | |
473 | {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, | |
474 | 0x0E, | |
475 | 0x08}, | |
476 | /* Index 0xD4~0xD7 */ | |
477 | {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, | |
478 | 0x10, | |
479 | 0x08}, | |
480 | /* Index 0xD8~0xDB */ | |
481 | {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, | |
482 | 0x10, | |
483 | 0x0E}, | |
484 | /* Index 0xDC~0xDF */ | |
485 | {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, | |
486 | 0x0A, | |
487 | 0x10}, | |
488 | /* Index 0xE0~0xE3 */ | |
489 | {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, | |
490 | 0x0B, | |
491 | 0x10}, | |
492 | /* Index 0xE4~0xE7 */ | |
493 | {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, | |
494 | 0x0B, | |
495 | 0x0C}, | |
496 | /* Index 0xE8~0xEB */ | |
497 | {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, | |
498 | 0x0F, | |
499 | 0x0B}, | |
500 | /* Index 0xEC~0xEF */ | |
501 | {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, | |
502 | 0x10, | |
503 | 0x0B}, | |
504 | /* Index 0xF0~0xF3 */ | |
505 | {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, | |
506 | 0x10, | |
507 | 0x0F}, | |
508 | /* Index 0xF4~0xF7 */ | |
509 | {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, | |
510 | 0x0C, | |
511 | 0x10}, | |
512 | /* Index 0xF8~0xFB */ | |
513 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, | |
514 | 0x00, | |
515 | 0x00}, | |
516 | /* Index 0xFC~0xFF */ | |
517 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, | |
518 | 0x00, | |
519 | 0x00} | |
520 | }; | |
521 | ||
522 | static void set_crt_output_path(int set_iga); | |
523 | static void dvi_patch_skew_dvp0(void); | |
524 | static void dvi_patch_skew_dvp1(void); | |
525 | static void dvi_patch_skew_dvp_low(void); | |
526 | static void set_dvi_output_path(int set_iga, int output_interface); | |
527 | static void set_lcd_output_path(int set_iga, int output_interface); | |
d61e0bf3 | 528 | static void load_fix_bit_crtc_reg(void); |
2d280f75 HW |
529 | static void init_gfx_chip_info(struct pci_dev *pdev, |
530 | const struct pci_device_id *pdi); | |
d61e0bf3 JC |
531 | static void init_tmds_chip_info(void); |
532 | static void init_lvds_chip_info(void); | |
533 | static void device_screen_off(void); | |
534 | static void device_screen_on(void); | |
535 | static void set_display_channel(void); | |
536 | static void device_off(void); | |
537 | static void device_on(void); | |
538 | static void enable_second_display_channel(void); | |
539 | static void disable_second_display_channel(void); | |
d61e0bf3 JC |
540 | |
541 | void viafb_write_reg(u8 index, u16 io_port, u8 data) | |
542 | { | |
543 | outb(index, io_port); | |
544 | outb(data, io_port + 1); | |
545 | /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */ | |
546 | } | |
547 | u8 viafb_read_reg(int io_port, u8 index) | |
548 | { | |
549 | outb(index, io_port); | |
550 | return inb(io_port + 1); | |
551 | } | |
552 | ||
553 | void viafb_lock_crt(void) | |
554 | { | |
555 | viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); | |
556 | } | |
557 | ||
558 | void viafb_unlock_crt(void) | |
559 | { | |
560 | viafb_write_reg_mask(CR11, VIACR, 0, BIT7); | |
561 | viafb_write_reg_mask(CR47, VIACR, 0, BIT0); | |
562 | } | |
563 | ||
564 | void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask) | |
565 | { | |
566 | u8 tmp; | |
567 | ||
568 | outb(index, io_port); | |
569 | tmp = inb(io_port + 1); | |
570 | outb((data & mask) | (tmp & (~mask)), io_port + 1); | |
571 | /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */ | |
572 | } | |
573 | ||
574 | void write_dac_reg(u8 index, u8 r, u8 g, u8 b) | |
575 | { | |
576 | outb(index, LUT_INDEX_WRITE); | |
577 | outb(r, LUT_DATA); | |
578 | outb(g, LUT_DATA); | |
579 | outb(b, LUT_DATA); | |
580 | } | |
581 | ||
582 | /*Set IGA path for each device*/ | |
583 | void viafb_set_iga_path(void) | |
584 | { | |
585 | ||
586 | if (viafb_SAMM_ON == 1) { | |
587 | if (viafb_CRT_ON) { | |
588 | if (viafb_primary_dev == CRT_Device) | |
589 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
590 | else | |
591 | viaparinfo->crt_setting_info->iga_path = IGA2; | |
592 | } | |
593 | ||
594 | if (viafb_DVI_ON) { | |
595 | if (viafb_primary_dev == DVI_Device) | |
596 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
597 | else | |
598 | viaparinfo->tmds_setting_info->iga_path = IGA2; | |
599 | } | |
600 | ||
601 | if (viafb_LCD_ON) { | |
602 | if (viafb_primary_dev == LCD_Device) { | |
603 | if (viafb_dual_fb && | |
604 | (viaparinfo->chip_info->gfx_chip_name == | |
605 | UNICHROME_CLE266)) { | |
606 | viaparinfo-> | |
607 | lvds_setting_info->iga_path = IGA2; | |
608 | viaparinfo-> | |
609 | crt_setting_info->iga_path = IGA1; | |
610 | viaparinfo-> | |
611 | tmds_setting_info->iga_path = IGA1; | |
612 | } else | |
613 | viaparinfo-> | |
614 | lvds_setting_info->iga_path = IGA1; | |
615 | } else { | |
616 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
617 | } | |
618 | } | |
619 | if (viafb_LCD2_ON) { | |
620 | if (LCD2_Device == viafb_primary_dev) | |
621 | viaparinfo->lvds_setting_info2->iga_path = IGA1; | |
622 | else | |
623 | viaparinfo->lvds_setting_info2->iga_path = IGA2; | |
624 | } | |
625 | } else { | |
626 | viafb_SAMM_ON = 0; | |
627 | ||
628 | if (viafb_CRT_ON && viafb_LCD_ON) { | |
629 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
630 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
631 | } else if (viafb_CRT_ON && viafb_DVI_ON) { | |
632 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
633 | viaparinfo->tmds_setting_info->iga_path = IGA2; | |
634 | } else if (viafb_LCD_ON && viafb_DVI_ON) { | |
635 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
636 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
637 | } else if (viafb_LCD_ON && viafb_LCD2_ON) { | |
638 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
639 | viaparinfo->lvds_setting_info2->iga_path = IGA2; | |
640 | } else if (viafb_CRT_ON) { | |
641 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
642 | } else if (viafb_LCD_ON) { | |
643 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
644 | } else if (viafb_DVI_ON) { | |
645 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
646 | } | |
647 | } | |
648 | } | |
649 | ||
09cf1180 | 650 | void viafb_set_primary_address(u32 addr) |
d61e0bf3 | 651 | { |
09cf1180 FTS |
652 | DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr); |
653 | viafb_write_reg(CR0D, VIACR, addr & 0xFF); | |
654 | viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF); | |
655 | viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF); | |
656 | viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F); | |
657 | } | |
d61e0bf3 | 658 | |
09cf1180 FTS |
659 | void viafb_set_secondary_address(u32 addr) |
660 | { | |
661 | DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr); | |
662 | /* secondary display supports only quadword aligned memory */ | |
663 | viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE); | |
664 | viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF); | |
665 | viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF); | |
666 | viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07); | |
d61e0bf3 JC |
667 | } |
668 | ||
2d6e8851 FTS |
669 | void viafb_set_primary_pitch(u32 pitch) |
670 | { | |
671 | DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch); | |
672 | /* spec does not say that first adapter skips 3 bits but old | |
673 | * code did it and seems to be reasonable in analogy to 2nd adapter | |
674 | */ | |
675 | pitch = pitch >> 3; | |
676 | viafb_write_reg(0x13, VIACR, pitch & 0xFF); | |
677 | viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0); | |
678 | } | |
679 | ||
680 | void viafb_set_secondary_pitch(u32 pitch) | |
681 | { | |
682 | DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch); | |
683 | pitch = pitch >> 3; | |
684 | viafb_write_reg(0x66, VIACR, pitch & 0xFF); | |
685 | viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03); | |
686 | viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80); | |
687 | } | |
688 | ||
daacccd1 FTS |
689 | void viafb_set_primary_color_depth(u8 depth) |
690 | { | |
691 | u8 value; | |
692 | ||
693 | DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth); | |
694 | switch (depth) { | |
415559fb | 695 | case 8: |
daacccd1 FTS |
696 | value = 0x00; |
697 | break; | |
e17cea3c FTS |
698 | case 15: |
699 | value = 0x04; | |
700 | break; | |
daacccd1 FTS |
701 | case 16: |
702 | value = 0x14; | |
703 | break; | |
704 | case 24: | |
705 | value = 0x0C; | |
706 | break; | |
e17cea3c FTS |
707 | case 30: |
708 | value = 0x08; | |
709 | break; | |
daacccd1 FTS |
710 | default: |
711 | printk(KERN_WARNING "viafb_set_primary_color_depth: " | |
712 | "Unsupported depth: %d\n", depth); | |
713 | return; | |
714 | } | |
715 | ||
716 | viafb_write_reg_mask(0x15, VIASR, value, 0x1C); | |
717 | } | |
718 | ||
719 | void viafb_set_secondary_color_depth(u8 depth) | |
720 | { | |
721 | u8 value; | |
722 | ||
723 | DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth); | |
724 | switch (depth) { | |
415559fb | 725 | case 8: |
daacccd1 FTS |
726 | value = 0x00; |
727 | break; | |
728 | case 16: | |
729 | value = 0x40; | |
730 | break; | |
731 | case 24: | |
732 | value = 0xC0; | |
733 | break; | |
e17cea3c FTS |
734 | case 30: |
735 | value = 0x80; | |
736 | break; | |
daacccd1 FTS |
737 | default: |
738 | printk(KERN_WARNING "viafb_set_secondary_color_depth: " | |
739 | "Unsupported depth: %d\n", depth); | |
740 | return; | |
741 | } | |
742 | ||
743 | viafb_write_reg_mask(0x67, VIACR, value, 0xC0); | |
744 | } | |
745 | ||
415559fb FTS |
746 | static void set_color_register(u8 index, u8 red, u8 green, u8 blue) |
747 | { | |
748 | outb(0xFF, 0x3C6); /* bit mask of palette */ | |
749 | outb(index, 0x3C8); | |
750 | outb(red, 0x3C9); | |
751 | outb(green, 0x3C9); | |
752 | outb(blue, 0x3C9); | |
753 | } | |
754 | ||
755 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue) | |
756 | { | |
757 | viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); | |
758 | set_color_register(index, red, green, blue); | |
759 | } | |
760 | ||
761 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue) | |
762 | { | |
763 | viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); | |
764 | set_color_register(index, red, green, blue); | |
765 | } | |
766 | ||
d61e0bf3 JC |
767 | void viafb_set_output_path(int device, int set_iga, int output_interface) |
768 | { | |
769 | switch (device) { | |
770 | case DEVICE_CRT: | |
771 | set_crt_output_path(set_iga); | |
772 | break; | |
773 | case DEVICE_DVI: | |
774 | set_dvi_output_path(set_iga, output_interface); | |
775 | break; | |
776 | case DEVICE_LCD: | |
777 | set_lcd_output_path(set_iga, output_interface); | |
778 | break; | |
779 | } | |
780 | } | |
781 | ||
782 | static void set_crt_output_path(int set_iga) | |
783 | { | |
784 | viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5); | |
785 | ||
786 | switch (set_iga) { | |
787 | case IGA1: | |
788 | viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); | |
789 | break; | |
790 | case IGA2: | |
d61e0bf3 JC |
791 | viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); |
792 | viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); | |
d61e0bf3 JC |
793 | break; |
794 | } | |
795 | } | |
796 | ||
797 | static void dvi_patch_skew_dvp0(void) | |
798 | { | |
799 | /* Reset data driving first: */ | |
800 | viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); | |
801 | viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); | |
802 | ||
803 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
804 | case UNICHROME_P4M890: | |
805 | { | |
806 | if ((viaparinfo->tmds_setting_info->h_active == 1600) && | |
807 | (viaparinfo->tmds_setting_info->v_active == | |
808 | 1200)) | |
809 | viafb_write_reg_mask(CR96, VIACR, 0x03, | |
810 | BIT0 + BIT1 + BIT2); | |
811 | else | |
812 | viafb_write_reg_mask(CR96, VIACR, 0x07, | |
813 | BIT0 + BIT1 + BIT2); | |
814 | break; | |
815 | } | |
816 | ||
817 | case UNICHROME_P4M900: | |
818 | { | |
819 | viafb_write_reg_mask(CR96, VIACR, 0x07, | |
820 | BIT0 + BIT1 + BIT2 + BIT3); | |
821 | viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); | |
822 | viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); | |
823 | break; | |
824 | } | |
825 | ||
826 | default: | |
827 | { | |
828 | break; | |
829 | } | |
830 | } | |
831 | } | |
832 | ||
833 | static void dvi_patch_skew_dvp1(void) | |
834 | { | |
835 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
836 | case UNICHROME_CX700: | |
837 | { | |
838 | break; | |
839 | } | |
840 | ||
841 | default: | |
842 | { | |
843 | break; | |
844 | } | |
845 | } | |
846 | } | |
847 | ||
848 | static void dvi_patch_skew_dvp_low(void) | |
849 | { | |
850 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
851 | case UNICHROME_K8M890: | |
852 | { | |
853 | viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); | |
854 | break; | |
855 | } | |
856 | ||
857 | case UNICHROME_P4M900: | |
858 | { | |
859 | viafb_write_reg_mask(CR99, VIACR, 0x08, | |
860 | BIT0 + BIT1 + BIT2 + BIT3); | |
861 | break; | |
862 | } | |
863 | ||
864 | case UNICHROME_P4M890: | |
865 | { | |
866 | viafb_write_reg_mask(CR99, VIACR, 0x0F, | |
867 | BIT0 + BIT1 + BIT2 + BIT3); | |
868 | break; | |
869 | } | |
870 | ||
871 | default: | |
872 | { | |
873 | break; | |
874 | } | |
875 | } | |
876 | } | |
877 | ||
878 | static void set_dvi_output_path(int set_iga, int output_interface) | |
879 | { | |
880 | switch (output_interface) { | |
881 | case INTERFACE_DVP0: | |
882 | viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); | |
883 | ||
884 | if (set_iga == IGA1) { | |
885 | viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); | |
886 | viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + | |
887 | BIT5 + BIT7); | |
888 | } else { | |
889 | viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); | |
890 | viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 + | |
891 | BIT5 + BIT7); | |
892 | } | |
893 | ||
894 | viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6); | |
895 | ||
896 | dvi_patch_skew_dvp0(); | |
897 | break; | |
898 | ||
899 | case INTERFACE_DVP1: | |
900 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { | |
901 | if (set_iga == IGA1) | |
902 | viafb_write_reg_mask(CR93, VIACR, 0x21, | |
903 | BIT0 + BIT5 + BIT7); | |
904 | else | |
905 | viafb_write_reg_mask(CR93, VIACR, 0xA1, | |
906 | BIT0 + BIT5 + BIT7); | |
907 | } else { | |
908 | if (set_iga == IGA1) | |
909 | viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); | |
910 | else | |
911 | viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); | |
912 | } | |
913 | ||
914 | viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5); | |
915 | dvi_patch_skew_dvp1(); | |
916 | break; | |
917 | case INTERFACE_DFP_HIGH: | |
918 | if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) { | |
919 | if (set_iga == IGA1) { | |
920 | viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); | |
921 | viafb_write_reg_mask(CR97, VIACR, 0x03, | |
922 | BIT0 + BIT1 + BIT4); | |
923 | } else { | |
924 | viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); | |
925 | viafb_write_reg_mask(CR97, VIACR, 0x13, | |
926 | BIT0 + BIT1 + BIT4); | |
927 | } | |
928 | } | |
929 | viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3); | |
930 | break; | |
931 | ||
932 | case INTERFACE_DFP_LOW: | |
933 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
934 | break; | |
935 | ||
936 | if (set_iga == IGA1) { | |
937 | viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); | |
938 | viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); | |
939 | } else { | |
940 | viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); | |
941 | viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); | |
942 | } | |
943 | ||
944 | viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); | |
945 | dvi_patch_skew_dvp_low(); | |
946 | break; | |
947 | ||
948 | case INTERFACE_TMDS: | |
949 | if (set_iga == IGA1) | |
950 | viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); | |
951 | else | |
952 | viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); | |
953 | break; | |
954 | } | |
955 | ||
956 | if (set_iga == IGA2) { | |
957 | enable_second_display_channel(); | |
958 | /* Disable LCD Scaling */ | |
959 | viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); | |
960 | } | |
961 | } | |
962 | ||
963 | static void set_lcd_output_path(int set_iga, int output_interface) | |
964 | { | |
965 | DEBUG_MSG(KERN_INFO | |
966 | "set_lcd_output_path, iga:%d,out_interface:%d\n", | |
967 | set_iga, output_interface); | |
968 | switch (set_iga) { | |
969 | case IGA1: | |
970 | viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); | |
971 | viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); | |
972 | ||
973 | disable_second_display_channel(); | |
974 | break; | |
975 | ||
976 | case IGA2: | |
977 | viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); | |
978 | viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); | |
979 | ||
980 | enable_second_display_channel(); | |
981 | break; | |
d61e0bf3 JC |
982 | } |
983 | ||
984 | switch (output_interface) { | |
985 | case INTERFACE_DVP0: | |
986 | if (set_iga == IGA1) { | |
987 | viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4); | |
988 | } else { | |
989 | viafb_write_reg(CR91, VIACR, 0x00); | |
990 | viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); | |
991 | } | |
992 | break; | |
993 | ||
994 | case INTERFACE_DVP1: | |
995 | if (set_iga == IGA1) | |
996 | viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4); | |
997 | else { | |
998 | viafb_write_reg(CR91, VIACR, 0x00); | |
999 | viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); | |
1000 | } | |
1001 | break; | |
1002 | ||
1003 | case INTERFACE_DFP_HIGH: | |
1004 | if (set_iga == IGA1) | |
1005 | viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); | |
1006 | else { | |
1007 | viafb_write_reg(CR91, VIACR, 0x00); | |
1008 | viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); | |
1009 | viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4); | |
1010 | } | |
1011 | break; | |
1012 | ||
1013 | case INTERFACE_DFP_LOW: | |
1014 | if (set_iga == IGA1) | |
1015 | viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); | |
1016 | else { | |
1017 | viafb_write_reg(CR91, VIACR, 0x00); | |
1018 | viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); | |
1019 | viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4); | |
1020 | } | |
1021 | ||
1022 | break; | |
1023 | ||
1024 | case INTERFACE_DFP: | |
1025 | if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name) | |
1026 | || (UNICHROME_P4M890 == | |
1027 | viaparinfo->chip_info->gfx_chip_name)) | |
1028 | viafb_write_reg_mask(CR97, VIACR, 0x84, | |
1029 | BIT7 + BIT2 + BIT1 + BIT0); | |
1030 | if (set_iga == IGA1) { | |
1031 | viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); | |
1032 | viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); | |
1033 | } else { | |
1034 | viafb_write_reg(CR91, VIACR, 0x00); | |
1035 | viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); | |
1036 | viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); | |
1037 | } | |
1038 | break; | |
1039 | ||
1040 | case INTERFACE_LVDS0: | |
1041 | case INTERFACE_LVDS0LVDS1: | |
1042 | if (set_iga == IGA1) | |
1043 | viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4); | |
1044 | else | |
1045 | viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4); | |
1046 | ||
1047 | break; | |
1048 | ||
1049 | case INTERFACE_LVDS1: | |
1050 | if (set_iga == IGA1) | |
1051 | viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4); | |
1052 | else | |
1053 | viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4); | |
1054 | break; | |
1055 | } | |
1056 | } | |
1057 | ||
d61e0bf3 JC |
1058 | static void load_fix_bit_crtc_reg(void) |
1059 | { | |
1060 | /* always set to 1 */ | |
1061 | viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); | |
1062 | /* line compare should set all bits = 1 (extend modes) */ | |
1063 | viafb_write_reg(CR18, VIACR, 0xff); | |
1064 | /* line compare should set all bits = 1 (extend modes) */ | |
1065 | viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4); | |
1066 | /* line compare should set all bits = 1 (extend modes) */ | |
1067 | viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6); | |
1068 | /* line compare should set all bits = 1 (extend modes) */ | |
1069 | viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); | |
1070 | /* line compare should set all bits = 1 (extend modes) */ | |
1071 | viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); | |
1072 | /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ | |
1073 | /* extend mode always set to e3h */ | |
1074 | viafb_write_reg(CR17, VIACR, 0xe3); | |
1075 | /* extend mode always set to 0h */ | |
1076 | viafb_write_reg(CR08, VIACR, 0x00); | |
1077 | /* extend mode always set to 0h */ | |
1078 | viafb_write_reg(CR14, VIACR, 0x00); | |
1079 | ||
1080 | /* If K8M800, enable Prefetch Mode. */ | |
1081 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) | |
1082 | || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890)) | |
1083 | viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); | |
1084 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
1085 | && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX)) | |
1086 | viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); | |
1087 | ||
1088 | } | |
1089 | ||
1090 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, | |
1091 | struct io_register *reg, | |
1092 | int io_type) | |
1093 | { | |
1094 | int reg_mask; | |
1095 | int bit_num = 0; | |
1096 | int data; | |
1097 | int i, j; | |
1098 | int shift_next_reg; | |
1099 | int start_index, end_index, cr_index; | |
1100 | u16 get_bit; | |
1101 | ||
1102 | for (i = 0; i < viafb_load_reg_num; i++) { | |
1103 | reg_mask = 0; | |
1104 | data = 0; | |
1105 | start_index = reg[i].start_bit; | |
1106 | end_index = reg[i].end_bit; | |
1107 | cr_index = reg[i].io_addr; | |
1108 | ||
1109 | shift_next_reg = bit_num; | |
1110 | for (j = start_index; j <= end_index; j++) { | |
1111 | /*if (bit_num==8) timing_value = timing_value >>8; */ | |
1112 | reg_mask = reg_mask | (BIT0 << j); | |
1113 | get_bit = (timing_value & (BIT0 << bit_num)); | |
1114 | data = | |
1115 | data | ((get_bit >> shift_next_reg) << start_index); | |
1116 | bit_num++; | |
1117 | } | |
1118 | if (io_type == VIACR) | |
1119 | viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); | |
1120 | else | |
1121 | viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); | |
1122 | } | |
1123 | ||
1124 | } | |
1125 | ||
1126 | /* Write Registers */ | |
1127 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum) | |
1128 | { | |
1129 | int i; | |
1130 | unsigned char RegTemp; | |
1131 | ||
1132 | /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */ | |
1133 | ||
1134 | for (i = 0; i < ItemNum; i++) { | |
1135 | outb(RegTable[i].index, RegTable[i].port); | |
1136 | RegTemp = inb(RegTable[i].port + 1); | |
1137 | RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value; | |
1138 | outb(RegTemp, RegTable[i].port + 1); | |
1139 | } | |
1140 | } | |
1141 | ||
d61e0bf3 JC |
1142 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga) |
1143 | { | |
1144 | int reg_value; | |
1145 | int viafb_load_reg_num; | |
1146 | struct io_register *reg = NULL; | |
1147 | ||
1148 | switch (set_iga) { | |
d61e0bf3 JC |
1149 | case IGA1: |
1150 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | |
1151 | viafb_load_reg_num = fetch_count_reg. | |
1152 | iga1_fetch_count_reg.reg_num; | |
1153 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; | |
1154 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
4bbac05f | 1155 | break; |
d61e0bf3 JC |
1156 | case IGA2: |
1157 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | |
1158 | viafb_load_reg_num = fetch_count_reg. | |
1159 | iga2_fetch_count_reg.reg_num; | |
1160 | reg = fetch_count_reg.iga2_fetch_count_reg.reg; | |
1161 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1162 | break; | |
1163 | } | |
1164 | ||
1165 | } | |
1166 | ||
1167 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) | |
1168 | { | |
1169 | int reg_value; | |
1170 | int viafb_load_reg_num; | |
1171 | struct io_register *reg = NULL; | |
1172 | int iga1_fifo_max_depth = 0, iga1_fifo_threshold = | |
1173 | 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; | |
1174 | int iga2_fifo_max_depth = 0, iga2_fifo_threshold = | |
1175 | 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; | |
1176 | ||
1177 | if (set_iga == IGA1) { | |
1178 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { | |
1179 | iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH; | |
1180 | iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD; | |
1181 | iga1_fifo_high_threshold = | |
1182 | K800_IGA1_FIFO_HIGH_THRESHOLD; | |
1183 | /* If resolution > 1280x1024, expire length = 64, else | |
1184 | expire length = 128 */ | |
1185 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1186 | iga1_display_queue_expire_num = 16; | |
1187 | else | |
1188 | iga1_display_queue_expire_num = | |
1189 | K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1190 | ||
1191 | } | |
1192 | ||
1193 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { | |
1194 | iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH; | |
1195 | iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD; | |
1196 | iga1_fifo_high_threshold = | |
1197 | P880_IGA1_FIFO_HIGH_THRESHOLD; | |
1198 | iga1_display_queue_expire_num = | |
1199 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1200 | ||
1201 | /* If resolution > 1280x1024, expire length = 64, else | |
1202 | expire length = 128 */ | |
1203 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1204 | iga1_display_queue_expire_num = 16; | |
1205 | else | |
1206 | iga1_display_queue_expire_num = | |
1207 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1208 | } | |
1209 | ||
1210 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { | |
1211 | iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH; | |
1212 | iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD; | |
1213 | iga1_fifo_high_threshold = | |
1214 | CN700_IGA1_FIFO_HIGH_THRESHOLD; | |
1215 | ||
1216 | /* If resolution > 1280x1024, expire length = 64, | |
1217 | else expire length = 128 */ | |
1218 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1219 | iga1_display_queue_expire_num = 16; | |
1220 | else | |
1221 | iga1_display_queue_expire_num = | |
1222 | CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1223 | } | |
1224 | ||
1225 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
1226 | iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH; | |
1227 | iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD; | |
1228 | iga1_fifo_high_threshold = | |
1229 | CX700_IGA1_FIFO_HIGH_THRESHOLD; | |
1230 | iga1_display_queue_expire_num = | |
1231 | CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1232 | } | |
1233 | ||
1234 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { | |
1235 | iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH; | |
1236 | iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD; | |
1237 | iga1_fifo_high_threshold = | |
1238 | K8M890_IGA1_FIFO_HIGH_THRESHOLD; | |
1239 | iga1_display_queue_expire_num = | |
1240 | K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1241 | } | |
1242 | ||
1243 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { | |
1244 | iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH; | |
1245 | iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD; | |
1246 | iga1_fifo_high_threshold = | |
1247 | P4M890_IGA1_FIFO_HIGH_THRESHOLD; | |
1248 | iga1_display_queue_expire_num = | |
1249 | P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1250 | } | |
1251 | ||
1252 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { | |
1253 | iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH; | |
1254 | iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD; | |
1255 | iga1_fifo_high_threshold = | |
1256 | P4M900_IGA1_FIFO_HIGH_THRESHOLD; | |
1257 | iga1_display_queue_expire_num = | |
1258 | P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1259 | } | |
1260 | ||
1261 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { | |
1262 | iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH; | |
1263 | iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD; | |
1264 | iga1_fifo_high_threshold = | |
1265 | VX800_IGA1_FIFO_HIGH_THRESHOLD; | |
1266 | iga1_display_queue_expire_num = | |
1267 | VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1268 | } | |
1269 | ||
0306ab11 HW |
1270 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
1271 | iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH; | |
1272 | iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD; | |
1273 | iga1_fifo_high_threshold = | |
1274 | VX855_IGA1_FIFO_HIGH_THRESHOLD; | |
1275 | iga1_display_queue_expire_num = | |
1276 | VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1277 | } | |
1278 | ||
d61e0bf3 JC |
1279 | /* Set Display FIFO Depath Select */ |
1280 | reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); | |
1281 | viafb_load_reg_num = | |
1282 | display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; | |
1283 | reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; | |
1284 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1285 | ||
1286 | /* Set Display FIFO Threshold Select */ | |
1287 | reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); | |
1288 | viafb_load_reg_num = | |
1289 | fifo_threshold_select_reg. | |
1290 | iga1_fifo_threshold_select_reg.reg_num; | |
1291 | reg = | |
1292 | fifo_threshold_select_reg. | |
1293 | iga1_fifo_threshold_select_reg.reg; | |
1294 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1295 | ||
1296 | /* Set FIFO High Threshold Select */ | |
1297 | reg_value = | |
1298 | IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); | |
1299 | viafb_load_reg_num = | |
1300 | fifo_high_threshold_select_reg. | |
1301 | iga1_fifo_high_threshold_select_reg.reg_num; | |
1302 | reg = | |
1303 | fifo_high_threshold_select_reg. | |
1304 | iga1_fifo_high_threshold_select_reg.reg; | |
1305 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1306 | ||
1307 | /* Set Display Queue Expire Num */ | |
1308 | reg_value = | |
1309 | IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA | |
1310 | (iga1_display_queue_expire_num); | |
1311 | viafb_load_reg_num = | |
1312 | display_queue_expire_num_reg. | |
1313 | iga1_display_queue_expire_num_reg.reg_num; | |
1314 | reg = | |
1315 | display_queue_expire_num_reg. | |
1316 | iga1_display_queue_expire_num_reg.reg; | |
1317 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1318 | ||
1319 | } else { | |
1320 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { | |
1321 | iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH; | |
1322 | iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD; | |
1323 | iga2_fifo_high_threshold = | |
1324 | K800_IGA2_FIFO_HIGH_THRESHOLD; | |
1325 | ||
1326 | /* If resolution > 1280x1024, expire length = 64, | |
1327 | else expire length = 128 */ | |
1328 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1329 | iga2_display_queue_expire_num = 16; | |
1330 | else | |
1331 | iga2_display_queue_expire_num = | |
1332 | K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1333 | } | |
1334 | ||
1335 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { | |
1336 | iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH; | |
1337 | iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD; | |
1338 | iga2_fifo_high_threshold = | |
1339 | P880_IGA2_FIFO_HIGH_THRESHOLD; | |
1340 | ||
1341 | /* If resolution > 1280x1024, expire length = 64, | |
1342 | else expire length = 128 */ | |
1343 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1344 | iga2_display_queue_expire_num = 16; | |
1345 | else | |
1346 | iga2_display_queue_expire_num = | |
1347 | P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1348 | } | |
1349 | ||
1350 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { | |
1351 | iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH; | |
1352 | iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD; | |
1353 | iga2_fifo_high_threshold = | |
1354 | CN700_IGA2_FIFO_HIGH_THRESHOLD; | |
1355 | ||
1356 | /* If resolution > 1280x1024, expire length = 64, | |
1357 | else expire length = 128 */ | |
1358 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1359 | iga2_display_queue_expire_num = 16; | |
1360 | else | |
1361 | iga2_display_queue_expire_num = | |
1362 | CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1363 | } | |
1364 | ||
1365 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
1366 | iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH; | |
1367 | iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD; | |
1368 | iga2_fifo_high_threshold = | |
1369 | CX700_IGA2_FIFO_HIGH_THRESHOLD; | |
1370 | iga2_display_queue_expire_num = | |
1371 | CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1372 | } | |
1373 | ||
1374 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { | |
1375 | iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH; | |
1376 | iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD; | |
1377 | iga2_fifo_high_threshold = | |
1378 | K8M890_IGA2_FIFO_HIGH_THRESHOLD; | |
1379 | iga2_display_queue_expire_num = | |
1380 | K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1381 | } | |
1382 | ||
1383 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { | |
1384 | iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH; | |
1385 | iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD; | |
1386 | iga2_fifo_high_threshold = | |
1387 | P4M890_IGA2_FIFO_HIGH_THRESHOLD; | |
1388 | iga2_display_queue_expire_num = | |
1389 | P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1390 | } | |
1391 | ||
1392 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { | |
1393 | iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH; | |
1394 | iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD; | |
1395 | iga2_fifo_high_threshold = | |
1396 | P4M900_IGA2_FIFO_HIGH_THRESHOLD; | |
1397 | iga2_display_queue_expire_num = | |
1398 | P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1399 | } | |
1400 | ||
1401 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { | |
1402 | iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH; | |
1403 | iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD; | |
1404 | iga2_fifo_high_threshold = | |
1405 | VX800_IGA2_FIFO_HIGH_THRESHOLD; | |
1406 | iga2_display_queue_expire_num = | |
1407 | VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1408 | } | |
1409 | ||
0306ab11 HW |
1410 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
1411 | iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH; | |
1412 | iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD; | |
1413 | iga2_fifo_high_threshold = | |
1414 | VX855_IGA2_FIFO_HIGH_THRESHOLD; | |
1415 | iga2_display_queue_expire_num = | |
1416 | VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1417 | } | |
1418 | ||
d61e0bf3 JC |
1419 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
1420 | /* Set Display FIFO Depath Select */ | |
1421 | reg_value = | |
1422 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth) | |
1423 | - 1; | |
1424 | /* Patch LCD in IGA2 case */ | |
1425 | viafb_load_reg_num = | |
1426 | display_fifo_depth_reg. | |
1427 | iga2_fifo_depth_select_reg.reg_num; | |
1428 | reg = | |
1429 | display_fifo_depth_reg. | |
1430 | iga2_fifo_depth_select_reg.reg; | |
1431 | viafb_load_reg(reg_value, | |
1432 | viafb_load_reg_num, reg, VIACR); | |
1433 | } else { | |
1434 | ||
1435 | /* Set Display FIFO Depath Select */ | |
1436 | reg_value = | |
1437 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth); | |
1438 | viafb_load_reg_num = | |
1439 | display_fifo_depth_reg. | |
1440 | iga2_fifo_depth_select_reg.reg_num; | |
1441 | reg = | |
1442 | display_fifo_depth_reg. | |
1443 | iga2_fifo_depth_select_reg.reg; | |
1444 | viafb_load_reg(reg_value, | |
1445 | viafb_load_reg_num, reg, VIACR); | |
1446 | } | |
1447 | ||
1448 | /* Set Display FIFO Threshold Select */ | |
1449 | reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold); | |
1450 | viafb_load_reg_num = | |
1451 | fifo_threshold_select_reg. | |
1452 | iga2_fifo_threshold_select_reg.reg_num; | |
1453 | reg = | |
1454 | fifo_threshold_select_reg. | |
1455 | iga2_fifo_threshold_select_reg.reg; | |
1456 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1457 | ||
1458 | /* Set FIFO High Threshold Select */ | |
1459 | reg_value = | |
1460 | IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold); | |
1461 | viafb_load_reg_num = | |
1462 | fifo_high_threshold_select_reg. | |
1463 | iga2_fifo_high_threshold_select_reg.reg_num; | |
1464 | reg = | |
1465 | fifo_high_threshold_select_reg. | |
1466 | iga2_fifo_high_threshold_select_reg.reg; | |
1467 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1468 | ||
1469 | /* Set Display Queue Expire Num */ | |
1470 | reg_value = | |
1471 | IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA | |
1472 | (iga2_display_queue_expire_num); | |
1473 | viafb_load_reg_num = | |
1474 | display_queue_expire_num_reg. | |
1475 | iga2_display_queue_expire_num_reg.reg_num; | |
1476 | reg = | |
1477 | display_queue_expire_num_reg. | |
1478 | iga2_display_queue_expire_num_reg.reg; | |
1479 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1480 | ||
1481 | } | |
1482 | ||
1483 | } | |
1484 | ||
1485 | u32 viafb_get_clk_value(int clk) | |
1486 | { | |
1487 | int i; | |
1488 | ||
1489 | for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) { | |
1490 | if (clk == pll_value[i].clk) { | |
1491 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1492 | case UNICHROME_CLE266: | |
1493 | case UNICHROME_K400: | |
1494 | return pll_value[i].cle266_pll; | |
1495 | ||
1496 | case UNICHROME_K800: | |
1497 | case UNICHROME_PM800: | |
1498 | case UNICHROME_CN700: | |
1499 | return pll_value[i].k800_pll; | |
1500 | ||
1501 | case UNICHROME_CX700: | |
1502 | case UNICHROME_K8M890: | |
1503 | case UNICHROME_P4M890: | |
1504 | case UNICHROME_P4M900: | |
1505 | case UNICHROME_VX800: | |
1506 | return pll_value[i].cx700_pll; | |
0306ab11 HW |
1507 | case UNICHROME_VX855: |
1508 | return pll_value[i].vx855_pll; | |
d61e0bf3 JC |
1509 | } |
1510 | } | |
1511 | } | |
1512 | ||
1513 | DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n"); | |
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | /* Set VCLK*/ | |
1518 | void viafb_set_vclock(u32 CLK, int set_iga) | |
1519 | { | |
1520 | unsigned char RegTemp; | |
1521 | ||
1522 | /* H.W. Reset : ON */ | |
1523 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | |
1524 | ||
4bbac05f | 1525 | if (set_iga == IGA1) { |
d61e0bf3 JC |
1526 | /* Change D,N FOR VCLK */ |
1527 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1528 | case UNICHROME_CLE266: | |
1529 | case UNICHROME_K400: | |
1530 | viafb_write_reg(SR46, VIASR, CLK / 0x100); | |
1531 | viafb_write_reg(SR47, VIASR, CLK % 0x100); | |
1532 | break; | |
1533 | ||
1534 | case UNICHROME_K800: | |
1535 | case UNICHROME_PM800: | |
1536 | case UNICHROME_CN700: | |
1537 | case UNICHROME_CX700: | |
1538 | case UNICHROME_K8M890: | |
1539 | case UNICHROME_P4M890: | |
1540 | case UNICHROME_P4M900: | |
1541 | case UNICHROME_VX800: | |
0306ab11 | 1542 | case UNICHROME_VX855: |
d61e0bf3 JC |
1543 | viafb_write_reg(SR44, VIASR, CLK / 0x10000); |
1544 | DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000); | |
1545 | viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100); | |
1546 | DEBUG_MSG(KERN_INFO "\nSR45=%x", | |
1547 | (CLK & 0xFFFF) / 0x100); | |
1548 | viafb_write_reg(SR46, VIASR, CLK % 0x100); | |
1549 | DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100); | |
1550 | break; | |
1551 | } | |
1552 | } | |
1553 | ||
4bbac05f | 1554 | if (set_iga == IGA2) { |
d61e0bf3 JC |
1555 | /* Change D,N FOR LCK */ |
1556 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1557 | case UNICHROME_CLE266: | |
1558 | case UNICHROME_K400: | |
1559 | viafb_write_reg(SR44, VIASR, CLK / 0x100); | |
1560 | viafb_write_reg(SR45, VIASR, CLK % 0x100); | |
1561 | break; | |
1562 | ||
1563 | case UNICHROME_K800: | |
1564 | case UNICHROME_PM800: | |
1565 | case UNICHROME_CN700: | |
1566 | case UNICHROME_CX700: | |
1567 | case UNICHROME_K8M890: | |
1568 | case UNICHROME_P4M890: | |
1569 | case UNICHROME_P4M900: | |
1570 | case UNICHROME_VX800: | |
0306ab11 | 1571 | case UNICHROME_VX855: |
d61e0bf3 JC |
1572 | viafb_write_reg(SR4A, VIASR, CLK / 0x10000); |
1573 | viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100); | |
1574 | viafb_write_reg(SR4C, VIASR, CLK % 0x100); | |
1575 | break; | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | /* H.W. Reset : OFF */ | |
1580 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | |
1581 | ||
1582 | /* Reset PLL */ | |
4bbac05f | 1583 | if (set_iga == IGA1) { |
d61e0bf3 JC |
1584 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); |
1585 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); | |
1586 | } | |
1587 | ||
4bbac05f | 1588 | if (set_iga == IGA2) { |
d61e0bf3 JC |
1589 | viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); |
1590 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); | |
1591 | } | |
1592 | ||
1593 | /* Fire! */ | |
1594 | RegTemp = inb(VIARMisc); | |
1595 | outb(RegTemp | (BIT2 + BIT3), VIAWMisc); | |
1596 | } | |
1597 | ||
1598 | void viafb_load_crtc_timing(struct display_timing device_timing, | |
1599 | int set_iga) | |
1600 | { | |
1601 | int i; | |
1602 | int viafb_load_reg_num = 0; | |
1603 | int reg_value = 0; | |
1604 | struct io_register *reg = NULL; | |
1605 | ||
1606 | viafb_unlock_crt(); | |
1607 | ||
1608 | for (i = 0; i < 12; i++) { | |
1609 | if (set_iga == IGA1) { | |
1610 | switch (i) { | |
1611 | case H_TOTAL_INDEX: | |
1612 | reg_value = | |
1613 | IGA1_HOR_TOTAL_FORMULA(device_timing. | |
1614 | hor_total); | |
1615 | viafb_load_reg_num = | |
1616 | iga1_crtc_reg.hor_total.reg_num; | |
1617 | reg = iga1_crtc_reg.hor_total.reg; | |
1618 | break; | |
1619 | case H_ADDR_INDEX: | |
1620 | reg_value = | |
1621 | IGA1_HOR_ADDR_FORMULA(device_timing. | |
1622 | hor_addr); | |
1623 | viafb_load_reg_num = | |
1624 | iga1_crtc_reg.hor_addr.reg_num; | |
1625 | reg = iga1_crtc_reg.hor_addr.reg; | |
1626 | break; | |
1627 | case H_BLANK_START_INDEX: | |
1628 | reg_value = | |
1629 | IGA1_HOR_BLANK_START_FORMULA | |
1630 | (device_timing.hor_blank_start); | |
1631 | viafb_load_reg_num = | |
1632 | iga1_crtc_reg.hor_blank_start.reg_num; | |
1633 | reg = iga1_crtc_reg.hor_blank_start.reg; | |
1634 | break; | |
1635 | case H_BLANK_END_INDEX: | |
1636 | reg_value = | |
1637 | IGA1_HOR_BLANK_END_FORMULA | |
1638 | (device_timing.hor_blank_start, | |
1639 | device_timing.hor_blank_end); | |
1640 | viafb_load_reg_num = | |
1641 | iga1_crtc_reg.hor_blank_end.reg_num; | |
1642 | reg = iga1_crtc_reg.hor_blank_end.reg; | |
1643 | break; | |
1644 | case H_SYNC_START_INDEX: | |
1645 | reg_value = | |
1646 | IGA1_HOR_SYNC_START_FORMULA | |
1647 | (device_timing.hor_sync_start); | |
1648 | viafb_load_reg_num = | |
1649 | iga1_crtc_reg.hor_sync_start.reg_num; | |
1650 | reg = iga1_crtc_reg.hor_sync_start.reg; | |
1651 | break; | |
1652 | case H_SYNC_END_INDEX: | |
1653 | reg_value = | |
1654 | IGA1_HOR_SYNC_END_FORMULA | |
1655 | (device_timing.hor_sync_start, | |
1656 | device_timing.hor_sync_end); | |
1657 | viafb_load_reg_num = | |
1658 | iga1_crtc_reg.hor_sync_end.reg_num; | |
1659 | reg = iga1_crtc_reg.hor_sync_end.reg; | |
1660 | break; | |
1661 | case V_TOTAL_INDEX: | |
1662 | reg_value = | |
1663 | IGA1_VER_TOTAL_FORMULA(device_timing. | |
1664 | ver_total); | |
1665 | viafb_load_reg_num = | |
1666 | iga1_crtc_reg.ver_total.reg_num; | |
1667 | reg = iga1_crtc_reg.ver_total.reg; | |
1668 | break; | |
1669 | case V_ADDR_INDEX: | |
1670 | reg_value = | |
1671 | IGA1_VER_ADDR_FORMULA(device_timing. | |
1672 | ver_addr); | |
1673 | viafb_load_reg_num = | |
1674 | iga1_crtc_reg.ver_addr.reg_num; | |
1675 | reg = iga1_crtc_reg.ver_addr.reg; | |
1676 | break; | |
1677 | case V_BLANK_START_INDEX: | |
1678 | reg_value = | |
1679 | IGA1_VER_BLANK_START_FORMULA | |
1680 | (device_timing.ver_blank_start); | |
1681 | viafb_load_reg_num = | |
1682 | iga1_crtc_reg.ver_blank_start.reg_num; | |
1683 | reg = iga1_crtc_reg.ver_blank_start.reg; | |
1684 | break; | |
1685 | case V_BLANK_END_INDEX: | |
1686 | reg_value = | |
1687 | IGA1_VER_BLANK_END_FORMULA | |
1688 | (device_timing.ver_blank_start, | |
1689 | device_timing.ver_blank_end); | |
1690 | viafb_load_reg_num = | |
1691 | iga1_crtc_reg.ver_blank_end.reg_num; | |
1692 | reg = iga1_crtc_reg.ver_blank_end.reg; | |
1693 | break; | |
1694 | case V_SYNC_START_INDEX: | |
1695 | reg_value = | |
1696 | IGA1_VER_SYNC_START_FORMULA | |
1697 | (device_timing.ver_sync_start); | |
1698 | viafb_load_reg_num = | |
1699 | iga1_crtc_reg.ver_sync_start.reg_num; | |
1700 | reg = iga1_crtc_reg.ver_sync_start.reg; | |
1701 | break; | |
1702 | case V_SYNC_END_INDEX: | |
1703 | reg_value = | |
1704 | IGA1_VER_SYNC_END_FORMULA | |
1705 | (device_timing.ver_sync_start, | |
1706 | device_timing.ver_sync_end); | |
1707 | viafb_load_reg_num = | |
1708 | iga1_crtc_reg.ver_sync_end.reg_num; | |
1709 | reg = iga1_crtc_reg.ver_sync_end.reg; | |
1710 | break; | |
1711 | ||
1712 | } | |
1713 | } | |
1714 | ||
1715 | if (set_iga == IGA2) { | |
1716 | switch (i) { | |
1717 | case H_TOTAL_INDEX: | |
1718 | reg_value = | |
1719 | IGA2_HOR_TOTAL_FORMULA(device_timing. | |
1720 | hor_total); | |
1721 | viafb_load_reg_num = | |
1722 | iga2_crtc_reg.hor_total.reg_num; | |
1723 | reg = iga2_crtc_reg.hor_total.reg; | |
1724 | break; | |
1725 | case H_ADDR_INDEX: | |
1726 | reg_value = | |
1727 | IGA2_HOR_ADDR_FORMULA(device_timing. | |
1728 | hor_addr); | |
1729 | viafb_load_reg_num = | |
1730 | iga2_crtc_reg.hor_addr.reg_num; | |
1731 | reg = iga2_crtc_reg.hor_addr.reg; | |
1732 | break; | |
1733 | case H_BLANK_START_INDEX: | |
1734 | reg_value = | |
1735 | IGA2_HOR_BLANK_START_FORMULA | |
1736 | (device_timing.hor_blank_start); | |
1737 | viafb_load_reg_num = | |
1738 | iga2_crtc_reg.hor_blank_start.reg_num; | |
1739 | reg = iga2_crtc_reg.hor_blank_start.reg; | |
1740 | break; | |
1741 | case H_BLANK_END_INDEX: | |
1742 | reg_value = | |
1743 | IGA2_HOR_BLANK_END_FORMULA | |
1744 | (device_timing.hor_blank_start, | |
1745 | device_timing.hor_blank_end); | |
1746 | viafb_load_reg_num = | |
1747 | iga2_crtc_reg.hor_blank_end.reg_num; | |
1748 | reg = iga2_crtc_reg.hor_blank_end.reg; | |
1749 | break; | |
1750 | case H_SYNC_START_INDEX: | |
1751 | reg_value = | |
1752 | IGA2_HOR_SYNC_START_FORMULA | |
1753 | (device_timing.hor_sync_start); | |
1754 | if (UNICHROME_CN700 <= | |
1755 | viaparinfo->chip_info->gfx_chip_name) | |
1756 | viafb_load_reg_num = | |
1757 | iga2_crtc_reg.hor_sync_start. | |
1758 | reg_num; | |
1759 | else | |
1760 | viafb_load_reg_num = 3; | |
1761 | reg = iga2_crtc_reg.hor_sync_start.reg; | |
1762 | break; | |
1763 | case H_SYNC_END_INDEX: | |
1764 | reg_value = | |
1765 | IGA2_HOR_SYNC_END_FORMULA | |
1766 | (device_timing.hor_sync_start, | |
1767 | device_timing.hor_sync_end); | |
1768 | viafb_load_reg_num = | |
1769 | iga2_crtc_reg.hor_sync_end.reg_num; | |
1770 | reg = iga2_crtc_reg.hor_sync_end.reg; | |
1771 | break; | |
1772 | case V_TOTAL_INDEX: | |
1773 | reg_value = | |
1774 | IGA2_VER_TOTAL_FORMULA(device_timing. | |
1775 | ver_total); | |
1776 | viafb_load_reg_num = | |
1777 | iga2_crtc_reg.ver_total.reg_num; | |
1778 | reg = iga2_crtc_reg.ver_total.reg; | |
1779 | break; | |
1780 | case V_ADDR_INDEX: | |
1781 | reg_value = | |
1782 | IGA2_VER_ADDR_FORMULA(device_timing. | |
1783 | ver_addr); | |
1784 | viafb_load_reg_num = | |
1785 | iga2_crtc_reg.ver_addr.reg_num; | |
1786 | reg = iga2_crtc_reg.ver_addr.reg; | |
1787 | break; | |
1788 | case V_BLANK_START_INDEX: | |
1789 | reg_value = | |
1790 | IGA2_VER_BLANK_START_FORMULA | |
1791 | (device_timing.ver_blank_start); | |
1792 | viafb_load_reg_num = | |
1793 | iga2_crtc_reg.ver_blank_start.reg_num; | |
1794 | reg = iga2_crtc_reg.ver_blank_start.reg; | |
1795 | break; | |
1796 | case V_BLANK_END_INDEX: | |
1797 | reg_value = | |
1798 | IGA2_VER_BLANK_END_FORMULA | |
1799 | (device_timing.ver_blank_start, | |
1800 | device_timing.ver_blank_end); | |
1801 | viafb_load_reg_num = | |
1802 | iga2_crtc_reg.ver_blank_end.reg_num; | |
1803 | reg = iga2_crtc_reg.ver_blank_end.reg; | |
1804 | break; | |
1805 | case V_SYNC_START_INDEX: | |
1806 | reg_value = | |
1807 | IGA2_VER_SYNC_START_FORMULA | |
1808 | (device_timing.ver_sync_start); | |
1809 | viafb_load_reg_num = | |
1810 | iga2_crtc_reg.ver_sync_start.reg_num; | |
1811 | reg = iga2_crtc_reg.ver_sync_start.reg; | |
1812 | break; | |
1813 | case V_SYNC_END_INDEX: | |
1814 | reg_value = | |
1815 | IGA2_VER_SYNC_END_FORMULA | |
1816 | (device_timing.ver_sync_start, | |
1817 | device_timing.ver_sync_end); | |
1818 | viafb_load_reg_num = | |
1819 | iga2_crtc_reg.ver_sync_end.reg_num; | |
1820 | reg = iga2_crtc_reg.ver_sync_end.reg; | |
1821 | break; | |
1822 | ||
1823 | } | |
1824 | } | |
1825 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1826 | } | |
1827 | ||
1828 | viafb_lock_crt(); | |
1829 | } | |
1830 | ||
d61e0bf3 | 1831 | void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, |
dd73d686 | 1832 | struct VideoModeTable *video_mode, int bpp_byte, int set_iga) |
d61e0bf3 | 1833 | { |
d61e0bf3 JC |
1834 | struct display_timing crt_reg; |
1835 | int i; | |
1836 | int index = 0; | |
1837 | int h_addr, v_addr; | |
1838 | u32 pll_D_N; | |
1839 | ||
d61e0bf3 JC |
1840 | for (i = 0; i < video_mode->mode_array; i++) { |
1841 | index = i; | |
1842 | ||
1843 | if (crt_table[i].refresh_rate == viaparinfo-> | |
1844 | crt_setting_info->refresh_rate) | |
1845 | break; | |
1846 | } | |
1847 | ||
1848 | crt_reg = crt_table[index].crtc; | |
1849 | ||
1850 | /* Mode 640x480 has border, but LCD/DFP didn't have border. */ | |
1851 | /* So we would delete border. */ | |
dd73d686 FTS |
1852 | if ((viafb_LCD_ON | viafb_DVI_ON) |
1853 | && video_mode->crtc[0].crtc.hor_addr == 640 | |
1854 | && video_mode->crtc[0].crtc.ver_addr == 480 | |
1855 | && viaparinfo->crt_setting_info->refresh_rate == 60) { | |
d61e0bf3 JC |
1856 | /* The border is 8 pixels. */ |
1857 | crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; | |
1858 | ||
1859 | /* Blanking time should add left and right borders. */ | |
1860 | crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16; | |
1861 | } | |
1862 | ||
1863 | h_addr = crt_reg.hor_addr; | |
1864 | v_addr = crt_reg.ver_addr; | |
1865 | ||
1866 | /* update polarity for CRT timing */ | |
1867 | if (crt_table[index].h_sync_polarity == NEGATIVE) { | |
1868 | if (crt_table[index].v_sync_polarity == NEGATIVE) | |
1869 | outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | | |
1870 | (BIT6 + BIT7), VIAWMisc); | |
1871 | else | |
1872 | outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6), | |
1873 | VIAWMisc); | |
1874 | } else { | |
1875 | if (crt_table[index].v_sync_polarity == NEGATIVE) | |
1876 | outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7), | |
1877 | VIAWMisc); | |
1878 | else | |
1879 | outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc); | |
1880 | } | |
1881 | ||
1882 | if (set_iga == IGA1) { | |
1883 | viafb_unlock_crt(); | |
1884 | viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */ | |
1885 | viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6); | |
1886 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | |
1887 | } | |
1888 | ||
1889 | switch (set_iga) { | |
1890 | case IGA1: | |
1891 | viafb_load_crtc_timing(crt_reg, IGA1); | |
1892 | break; | |
1893 | case IGA2: | |
1894 | viafb_load_crtc_timing(crt_reg, IGA2); | |
1895 | break; | |
1896 | } | |
1897 | ||
1898 | load_fix_bit_crtc_reg(); | |
1899 | viafb_lock_crt(); | |
1900 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | |
d61e0bf3 JC |
1901 | viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga); |
1902 | ||
1903 | /* load FIFO */ | |
1904 | if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) | |
1905 | && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) | |
1906 | viafb_load_FIFO_reg(set_iga, h_addr, v_addr); | |
1907 | ||
d61e0bf3 JC |
1908 | pll_D_N = viafb_get_clk_value(crt_table[index].clk); |
1909 | DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); | |
1910 | viafb_set_vclock(pll_D_N, set_iga); | |
1911 | ||
1912 | } | |
1913 | ||
2d280f75 HW |
1914 | void viafb_init_chip_info(struct pci_dev *pdev, |
1915 | const struct pci_device_id *pdi) | |
d61e0bf3 | 1916 | { |
2d280f75 | 1917 | init_gfx_chip_info(pdev, pdi); |
d61e0bf3 JC |
1918 | init_tmds_chip_info(); |
1919 | init_lvds_chip_info(); | |
1920 | ||
1921 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
1922 | viaparinfo->crt_setting_info->refresh_rate = viafb_refresh; | |
1923 | ||
1924 | /*Set IGA path for each device */ | |
1925 | viafb_set_iga_path(); | |
1926 | ||
1927 | viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method; | |
1928 | viaparinfo->lvds_setting_info->get_lcd_size_method = | |
1929 | GET_LCD_SIZE_BY_USER_SETTING; | |
1930 | viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode; | |
1931 | viaparinfo->lvds_setting_info2->display_method = | |
1932 | viaparinfo->lvds_setting_info->display_method; | |
1933 | viaparinfo->lvds_setting_info2->lcd_mode = | |
1934 | viaparinfo->lvds_setting_info->lcd_mode; | |
1935 | } | |
1936 | ||
1937 | void viafb_update_device_setting(int hres, int vres, | |
1938 | int bpp, int vmode_refresh, int flag) | |
1939 | { | |
1940 | if (flag == 0) { | |
1941 | viaparinfo->crt_setting_info->h_active = hres; | |
1942 | viaparinfo->crt_setting_info->v_active = vres; | |
1943 | viaparinfo->crt_setting_info->bpp = bpp; | |
1944 | viaparinfo->crt_setting_info->refresh_rate = | |
1945 | vmode_refresh; | |
1946 | ||
1947 | viaparinfo->tmds_setting_info->h_active = hres; | |
1948 | viaparinfo->tmds_setting_info->v_active = vres; | |
d61e0bf3 JC |
1949 | |
1950 | viaparinfo->lvds_setting_info->h_active = hres; | |
1951 | viaparinfo->lvds_setting_info->v_active = vres; | |
1952 | viaparinfo->lvds_setting_info->bpp = bpp; | |
1953 | viaparinfo->lvds_setting_info->refresh_rate = | |
1954 | vmode_refresh; | |
1955 | viaparinfo->lvds_setting_info2->h_active = hres; | |
1956 | viaparinfo->lvds_setting_info2->v_active = vres; | |
1957 | viaparinfo->lvds_setting_info2->bpp = bpp; | |
1958 | viaparinfo->lvds_setting_info2->refresh_rate = | |
1959 | vmode_refresh; | |
1960 | } else { | |
1961 | ||
1962 | if (viaparinfo->tmds_setting_info->iga_path == IGA2) { | |
1963 | viaparinfo->tmds_setting_info->h_active = hres; | |
1964 | viaparinfo->tmds_setting_info->v_active = vres; | |
d61e0bf3 JC |
1965 | } |
1966 | ||
1967 | if (viaparinfo->lvds_setting_info->iga_path == IGA2) { | |
1968 | viaparinfo->lvds_setting_info->h_active = hres; | |
1969 | viaparinfo->lvds_setting_info->v_active = vres; | |
1970 | viaparinfo->lvds_setting_info->bpp = bpp; | |
1971 | viaparinfo->lvds_setting_info->refresh_rate = | |
1972 | vmode_refresh; | |
1973 | } | |
1974 | if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) { | |
1975 | viaparinfo->lvds_setting_info2->h_active = hres; | |
1976 | viaparinfo->lvds_setting_info2->v_active = vres; | |
1977 | viaparinfo->lvds_setting_info2->bpp = bpp; | |
1978 | viaparinfo->lvds_setting_info2->refresh_rate = | |
1979 | vmode_refresh; | |
1980 | } | |
1981 | } | |
1982 | } | |
1983 | ||
2d280f75 HW |
1984 | static void init_gfx_chip_info(struct pci_dev *pdev, |
1985 | const struct pci_device_id *pdi) | |
d61e0bf3 | 1986 | { |
d61e0bf3 JC |
1987 | u8 tmp; |
1988 | ||
2d280f75 | 1989 | viaparinfo->chip_info->gfx_chip_name = pdi->driver_data; |
d61e0bf3 JC |
1990 | |
1991 | /* Check revision of CLE266 Chip */ | |
1992 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { | |
1993 | /* CR4F only define in CLE266.CX chip */ | |
1994 | tmp = viafb_read_reg(VIACR, CR4F); | |
1995 | viafb_write_reg(CR4F, VIACR, 0x55); | |
1996 | if (viafb_read_reg(VIACR, CR4F) != 0x55) | |
1997 | viaparinfo->chip_info->gfx_chip_revision = | |
1998 | CLE266_REVISION_AX; | |
1999 | else | |
2000 | viaparinfo->chip_info->gfx_chip_revision = | |
2001 | CLE266_REVISION_CX; | |
2002 | /* restore orignal CR4F value */ | |
2003 | viafb_write_reg(CR4F, VIACR, tmp); | |
2004 | } | |
2005 | ||
2006 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
2007 | tmp = viafb_read_reg(VIASR, SR43); | |
2008 | DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp); | |
2009 | if (tmp & 0x02) { | |
2010 | viaparinfo->chip_info->gfx_chip_revision = | |
2011 | CX700_REVISION_700M2; | |
2012 | } else if (tmp & 0x40) { | |
2013 | viaparinfo->chip_info->gfx_chip_revision = | |
2014 | CX700_REVISION_700M; | |
2015 | } else { | |
2016 | viaparinfo->chip_info->gfx_chip_revision = | |
2017 | CX700_REVISION_700; | |
2018 | } | |
2019 | } | |
107ea34d HW |
2020 | |
2021 | /* Determine which 2D engine we have */ | |
2022 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2023 | case UNICHROME_VX800: | |
2024 | case UNICHROME_VX855: | |
2025 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; | |
2026 | break; | |
2027 | case UNICHROME_K8M890: | |
2028 | case UNICHROME_P4M900: | |
2029 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5; | |
2030 | break; | |
2031 | default: | |
2032 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2; | |
2033 | break; | |
2034 | } | |
d61e0bf3 JC |
2035 | } |
2036 | ||
2037 | static void init_tmds_chip_info(void) | |
2038 | { | |
2039 | viafb_tmds_trasmitter_identify(); | |
2040 | ||
2041 | if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info. | |
2042 | output_interface) { | |
2043 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2044 | case UNICHROME_CX700: | |
2045 | { | |
2046 | /* we should check support by hardware layout.*/ | |
2047 | if ((viafb_display_hardware_layout == | |
2048 | HW_LAYOUT_DVI_ONLY) | |
2049 | || (viafb_display_hardware_layout == | |
2050 | HW_LAYOUT_LCD_DVI)) { | |
2051 | viaparinfo->chip_info->tmds_chip_info. | |
2052 | output_interface = INTERFACE_TMDS; | |
2053 | } else { | |
2054 | viaparinfo->chip_info->tmds_chip_info. | |
2055 | output_interface = | |
2056 | INTERFACE_NONE; | |
2057 | } | |
2058 | break; | |
2059 | } | |
2060 | case UNICHROME_K8M890: | |
2061 | case UNICHROME_P4M900: | |
2062 | case UNICHROME_P4M890: | |
2063 | /* TMDS on PCIE, we set DFPLOW as default. */ | |
2064 | viaparinfo->chip_info->tmds_chip_info.output_interface = | |
2065 | INTERFACE_DFP_LOW; | |
2066 | break; | |
2067 | default: | |
2068 | { | |
2069 | /* set DVP1 default for DVI */ | |
2070 | viaparinfo->chip_info->tmds_chip_info | |
2071 | .output_interface = INTERFACE_DVP1; | |
2072 | } | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", | |
2077 | viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); | |
c5f06f5c FTS |
2078 | viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info, |
2079 | &viaparinfo->shared->tmds_setting_info); | |
d61e0bf3 JC |
2080 | } |
2081 | ||
2082 | static void init_lvds_chip_info(void) | |
2083 | { | |
2084 | if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM) | |
2085 | viaparinfo->lvds_setting_info->get_lcd_size_method = | |
2086 | GET_LCD_SIZE_BY_VGA_BIOS; | |
2087 | else | |
2088 | viaparinfo->lvds_setting_info->get_lcd_size_method = | |
2089 | GET_LCD_SIZE_BY_USER_SETTING; | |
2090 | ||
2091 | viafb_lvds_trasmitter_identify(); | |
2092 | viafb_init_lcd_size(); | |
2093 | viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info, | |
2094 | viaparinfo->lvds_setting_info); | |
2095 | if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { | |
2096 | viafb_init_lvds_output_interface(&viaparinfo->chip_info-> | |
2097 | lvds_chip_info2, viaparinfo->lvds_setting_info2); | |
2098 | } | |
2099 | /*If CX700,two singel LCD, we need to reassign | |
2100 | LCD interface to different LVDS port */ | |
2101 | if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name) | |
2102 | && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) { | |
2103 | if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info. | |
2104 | lvds_chip_name) && (INTEGRATED_LVDS == | |
2105 | viaparinfo->chip_info-> | |
2106 | lvds_chip_info2.lvds_chip_name)) { | |
2107 | viaparinfo->chip_info->lvds_chip_info.output_interface = | |
2108 | INTERFACE_LVDS0; | |
2109 | viaparinfo->chip_info->lvds_chip_info2. | |
2110 | output_interface = | |
2111 | INTERFACE_LVDS1; | |
2112 | } | |
2113 | } | |
2114 | ||
2115 | DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n", | |
2116 | viaparinfo->chip_info->lvds_chip_info.lvds_chip_name); | |
2117 | DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n", | |
2118 | viaparinfo->chip_info->lvds_chip_info.output_interface); | |
2119 | DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n", | |
2120 | viaparinfo->chip_info->lvds_chip_info.output_interface); | |
2121 | } | |
2122 | ||
2123 | void viafb_init_dac(int set_iga) | |
2124 | { | |
2125 | int i; | |
2126 | u8 tmp; | |
2127 | ||
2128 | if (set_iga == IGA1) { | |
2129 | /* access Primary Display's LUT */ | |
2130 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); | |
2131 | /* turn off LCK */ | |
2132 | viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); | |
2133 | for (i = 0; i < 256; i++) { | |
2134 | write_dac_reg(i, palLUT_table[i].red, | |
2135 | palLUT_table[i].green, | |
2136 | palLUT_table[i].blue); | |
2137 | } | |
2138 | /* turn on LCK */ | |
2139 | viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); | |
2140 | } else { | |
2141 | tmp = viafb_read_reg(VIACR, CR6A); | |
2142 | /* access Secondary Display's LUT */ | |
2143 | viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); | |
2144 | viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); | |
2145 | for (i = 0; i < 256; i++) { | |
2146 | write_dac_reg(i, palLUT_table[i].red, | |
2147 | palLUT_table[i].green, | |
2148 | palLUT_table[i].blue); | |
2149 | } | |
2150 | /* set IGA1 DAC for default */ | |
2151 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); | |
2152 | viafb_write_reg(CR6A, VIACR, tmp); | |
2153 | } | |
2154 | } | |
2155 | ||
2156 | static void device_screen_off(void) | |
2157 | { | |
2158 | /* turn off CRT screen (IGA1) */ | |
2159 | viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); | |
2160 | } | |
2161 | ||
2162 | static void device_screen_on(void) | |
2163 | { | |
2164 | /* turn on CRT screen (IGA1) */ | |
2165 | viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); | |
2166 | } | |
2167 | ||
2168 | static void set_display_channel(void) | |
2169 | { | |
2170 | /*If viafb_LCD2_ON, on cx700, internal lvds's information | |
2171 | is keeped on lvds_setting_info2 */ | |
2172 | if (viafb_LCD2_ON && | |
2173 | viaparinfo->lvds_setting_info2->device_lcd_dualedge) { | |
2174 | /* For dual channel LCD: */ | |
2175 | /* Set to Dual LVDS channel. */ | |
2176 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); | |
2177 | } else if (viafb_LCD_ON && viafb_DVI_ON) { | |
2178 | /* For LCD+DFP: */ | |
2179 | /* Set to LVDS1 + TMDS channel. */ | |
2180 | viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); | |
2181 | } else if (viafb_DVI_ON) { | |
2182 | /* Set to single TMDS channel. */ | |
2183 | viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); | |
2184 | } else if (viafb_LCD_ON) { | |
2185 | if (viaparinfo->lvds_setting_info->device_lcd_dualedge) { | |
2186 | /* For dual channel LCD: */ | |
2187 | /* Set to Dual LVDS channel. */ | |
2188 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); | |
2189 | } else { | |
2190 | /* Set to LVDS0 + LVDS1 channel. */ | |
2191 | viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); | |
2192 | } | |
2193 | } | |
2194 | } | |
2195 | ||
dd73d686 FTS |
2196 | int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, |
2197 | struct VideoModeTable *vmode_tbl1, int video_bpp1) | |
d61e0bf3 JC |
2198 | { |
2199 | int i, j; | |
2200 | int port; | |
2201 | u8 value, index, mask; | |
d61e0bf3 | 2202 | struct crt_mode_table *crt_timing; |
d61e0bf3 JC |
2203 | struct crt_mode_table *crt_timing1 = NULL; |
2204 | ||
d61e0bf3 | 2205 | device_screen_off(); |
d61e0bf3 JC |
2206 | crt_timing = vmode_tbl->crtc; |
2207 | ||
2208 | if (viafb_SAMM_ON == 1) { | |
d61e0bf3 JC |
2209 | crt_timing1 = vmode_tbl1->crtc; |
2210 | } | |
2211 | ||
2212 | inb(VIAStatus); | |
2213 | outb(0x00, VIAAR); | |
2214 | ||
2215 | /* Write Common Setting for Video Mode */ | |
2216 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2217 | case UNICHROME_CLE266: | |
2218 | viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs); | |
2219 | break; | |
2220 | ||
2221 | case UNICHROME_K400: | |
2222 | viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs); | |
2223 | break; | |
2224 | ||
2225 | case UNICHROME_K800: | |
2226 | case UNICHROME_PM800: | |
2227 | viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs); | |
2228 | break; | |
2229 | ||
2230 | case UNICHROME_CN700: | |
2231 | case UNICHROME_K8M890: | |
2232 | case UNICHROME_P4M890: | |
2233 | case UNICHROME_P4M900: | |
2234 | viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs); | |
2235 | break; | |
2236 | ||
2237 | case UNICHROME_CX700: | |
d61e0bf3 | 2238 | case UNICHROME_VX800: |
0e3ca33a | 2239 | viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs); |
d61e0bf3 | 2240 | break; |
0306ab11 HW |
2241 | |
2242 | case UNICHROME_VX855: | |
2243 | viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); | |
2244 | break; | |
d61e0bf3 JC |
2245 | } |
2246 | ||
2247 | device_off(); | |
2248 | ||
2249 | /* Fill VPIT Parameters */ | |
2250 | /* Write Misc Register */ | |
2251 | outb(VPIT.Misc, VIAWMisc); | |
2252 | ||
2253 | /* Write Sequencer */ | |
2254 | for (i = 1; i <= StdSR; i++) { | |
2255 | outb(i, VIASR); | |
2256 | outb(VPIT.SR[i - 1], VIASR + 1); | |
2257 | } | |
2258 | ||
415559fb | 2259 | viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); |
d61e0bf3 JC |
2260 | viafb_set_iga_path(); |
2261 | ||
2262 | /* Write CRTC */ | |
dd73d686 | 2263 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1); |
d61e0bf3 JC |
2264 | |
2265 | /* Write Graphic Controller */ | |
2266 | for (i = 0; i < StdGR; i++) { | |
2267 | outb(i, VIAGR); | |
2268 | outb(VPIT.GR[i], VIAGR + 1); | |
2269 | } | |
2270 | ||
2271 | /* Write Attribute Controller */ | |
2272 | for (i = 0; i < StdAR; i++) { | |
2273 | inb(VIAStatus); | |
2274 | outb(i, VIAAR); | |
2275 | outb(VPIT.AR[i], VIAAR); | |
2276 | } | |
2277 | ||
2278 | inb(VIAStatus); | |
2279 | outb(0x20, VIAAR); | |
2280 | ||
2281 | /* Update Patch Register */ | |
2282 | ||
dd73d686 FTS |
2283 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266 |
2284 | || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400) | |
2285 | && vmode_tbl->crtc[0].crtc.hor_addr == 1024 | |
2286 | && vmode_tbl->crtc[0].crtc.ver_addr == 768) { | |
2287 | for (j = 0; j < res_patch_table[0].table_length; j++) { | |
2288 | index = res_patch_table[0].io_reg_table[j].index; | |
2289 | port = res_patch_table[0].io_reg_table[j].port; | |
2290 | value = res_patch_table[0].io_reg_table[j].value; | |
2291 | mask = res_patch_table[0].io_reg_table[j].mask; | |
2292 | viafb_write_reg_mask(index, port, value, mask); | |
d61e0bf3 JC |
2293 | } |
2294 | } | |
2295 | ||
2d6e8851 FTS |
2296 | viafb_set_primary_pitch(viafbinfo->fix.line_length); |
2297 | viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length | |
2298 | : viafbinfo->fix.line_length); | |
daacccd1 FTS |
2299 | viafb_set_primary_color_depth(viaparinfo->depth); |
2300 | viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth | |
2301 | : viaparinfo->depth); | |
d61e0bf3 JC |
2302 | /* Update Refresh Rate Setting */ |
2303 | ||
2304 | /* Clear On Screen */ | |
2305 | ||
2306 | /* CRT set mode */ | |
2307 | if (viafb_CRT_ON) { | |
2308 | if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path == | |
2309 | IGA2)) { | |
dd73d686 | 2310 | viafb_fill_crtc_timing(crt_timing1, vmode_tbl1, |
d61e0bf3 JC |
2311 | video_bpp1 / 8, |
2312 | viaparinfo->crt_setting_info->iga_path); | |
2313 | } else { | |
dd73d686 | 2314 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, |
d61e0bf3 JC |
2315 | video_bpp / 8, |
2316 | viaparinfo->crt_setting_info->iga_path); | |
2317 | } | |
2318 | ||
2319 | set_crt_output_path(viaparinfo->crt_setting_info->iga_path); | |
2320 | ||
2321 | /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode | |
2322 | to 8 alignment (1368),there is several pixels (2 pixels) | |
2323 | on right side of screen. */ | |
dd73d686 | 2324 | if (vmode_tbl->crtc[0].crtc.hor_addr % 8) { |
d61e0bf3 JC |
2325 | viafb_unlock_crt(); |
2326 | viafb_write_reg(CR02, VIACR, | |
2327 | viafb_read_reg(VIACR, CR02) - 1); | |
2328 | viafb_lock_crt(); | |
2329 | } | |
2330 | } | |
2331 | ||
2332 | if (viafb_DVI_ON) { | |
2333 | if (viafb_SAMM_ON && | |
2334 | (viaparinfo->tmds_setting_info->iga_path == IGA2)) { | |
dd73d686 | 2335 | viafb_dvi_set_mode(viafb_get_mode |
d61e0bf3 JC |
2336 | (viaparinfo->tmds_setting_info->h_active, |
2337 | viaparinfo->tmds_setting_info-> | |
52159444 | 2338 | v_active), |
d61e0bf3 JC |
2339 | video_bpp1, viaparinfo-> |
2340 | tmds_setting_info->iga_path); | |
2341 | } else { | |
dd73d686 | 2342 | viafb_dvi_set_mode(viafb_get_mode |
d61e0bf3 JC |
2343 | (viaparinfo->tmds_setting_info->h_active, |
2344 | viaparinfo-> | |
52159444 | 2345 | tmds_setting_info->v_active), |
d61e0bf3 JC |
2346 | video_bpp, viaparinfo-> |
2347 | tmds_setting_info->iga_path); | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | if (viafb_LCD_ON) { | |
2352 | if (viafb_SAMM_ON && | |
2353 | (viaparinfo->lvds_setting_info->iga_path == IGA2)) { | |
2354 | viaparinfo->lvds_setting_info->bpp = video_bpp1; | |
2355 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> | |
2356 | lvds_setting_info, | |
2357 | &viaparinfo->chip_info->lvds_chip_info); | |
2358 | } else { | |
2359 | /* IGA1 doesn't have LCD scaling, so set it center. */ | |
2360 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) { | |
2361 | viaparinfo->lvds_setting_info->display_method = | |
2362 | LCD_CENTERING; | |
2363 | } | |
2364 | viaparinfo->lvds_setting_info->bpp = video_bpp; | |
2365 | viafb_lcd_set_mode(crt_timing, viaparinfo-> | |
2366 | lvds_setting_info, | |
2367 | &viaparinfo->chip_info->lvds_chip_info); | |
2368 | } | |
2369 | } | |
2370 | if (viafb_LCD2_ON) { | |
2371 | if (viafb_SAMM_ON && | |
2372 | (viaparinfo->lvds_setting_info2->iga_path == IGA2)) { | |
2373 | viaparinfo->lvds_setting_info2->bpp = video_bpp1; | |
2374 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> | |
2375 | lvds_setting_info2, | |
2376 | &viaparinfo->chip_info->lvds_chip_info2); | |
2377 | } else { | |
2378 | /* IGA1 doesn't have LCD scaling, so set it center. */ | |
2379 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) { | |
2380 | viaparinfo->lvds_setting_info2->display_method = | |
2381 | LCD_CENTERING; | |
2382 | } | |
2383 | viaparinfo->lvds_setting_info2->bpp = video_bpp; | |
2384 | viafb_lcd_set_mode(crt_timing, viaparinfo-> | |
2385 | lvds_setting_info2, | |
2386 | &viaparinfo->chip_info->lvds_chip_info2); | |
2387 | } | |
2388 | } | |
2389 | ||
2390 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) | |
2391 | && (viafb_LCD_ON || viafb_DVI_ON)) | |
2392 | set_display_channel(); | |
2393 | ||
2394 | /* If set mode normally, save resolution information for hot-plug . */ | |
2395 | if (!viafb_hotplug) { | |
dd73d686 FTS |
2396 | viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr; |
2397 | viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr; | |
d61e0bf3 JC |
2398 | viafb_hotplug_bpp = video_bpp; |
2399 | viafb_hotplug_refresh = viafb_refresh; | |
2400 | ||
2401 | if (viafb_DVI_ON) | |
2402 | viafb_DeviceStatus = DVI_Device; | |
2403 | else | |
2404 | viafb_DeviceStatus = CRT_Device; | |
2405 | } | |
2406 | device_on(); | |
2407 | ||
2408 | if (viafb_SAMM_ON == 1) | |
2409 | viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); | |
2410 | ||
2411 | device_screen_on(); | |
2412 | return 1; | |
2413 | } | |
2414 | ||
2415 | int viafb_get_pixclock(int hres, int vres, int vmode_refresh) | |
2416 | { | |
2417 | int i; | |
2418 | ||
2419 | for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { | |
2420 | if ((hres == res_map_refresh_tbl[i].hres) | |
2421 | && (vres == res_map_refresh_tbl[i].vres) | |
2422 | && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh)) | |
2423 | return res_map_refresh_tbl[i].pixclock; | |
2424 | } | |
2425 | return RES_640X480_60HZ_PIXCLOCK; | |
2426 | ||
2427 | } | |
2428 | ||
2429 | int viafb_get_refresh(int hres, int vres, u32 long_refresh) | |
2430 | { | |
2431 | #define REFRESH_TOLERANCE 3 | |
2432 | int i, nearest = -1, diff = REFRESH_TOLERANCE; | |
2433 | for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { | |
2434 | if ((hres == res_map_refresh_tbl[i].hres) | |
2435 | && (vres == res_map_refresh_tbl[i].vres) | |
2436 | && (diff > (abs(long_refresh - | |
2437 | res_map_refresh_tbl[i].vmode_refresh)))) { | |
2438 | diff = abs(long_refresh - res_map_refresh_tbl[i]. | |
2439 | vmode_refresh); | |
2440 | nearest = i; | |
2441 | } | |
2442 | } | |
2443 | #undef REFRESH_TOLERANCE | |
2444 | if (nearest > 0) | |
2445 | return res_map_refresh_tbl[nearest].vmode_refresh; | |
2446 | return 60; | |
2447 | } | |
2448 | ||
2449 | static void device_off(void) | |
2450 | { | |
2451 | viafb_crt_disable(); | |
2452 | viafb_dvi_disable(); | |
2453 | viafb_lcd_disable(); | |
2454 | } | |
2455 | ||
2456 | static void device_on(void) | |
2457 | { | |
2458 | if (viafb_CRT_ON == 1) | |
2459 | viafb_crt_enable(); | |
2460 | if (viafb_DVI_ON == 1) | |
2461 | viafb_dvi_enable(); | |
2462 | if (viafb_LCD_ON == 1) | |
2463 | viafb_lcd_enable(); | |
2464 | } | |
2465 | ||
2466 | void viafb_crt_disable(void) | |
2467 | { | |
2468 | viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4); | |
2469 | } | |
2470 | ||
2471 | void viafb_crt_enable(void) | |
2472 | { | |
2473 | viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4); | |
2474 | } | |
2475 | ||
d61e0bf3 JC |
2476 | static void enable_second_display_channel(void) |
2477 | { | |
2478 | /* to enable second display channel. */ | |
2479 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); | |
2480 | viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); | |
2481 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | |
2482 | } | |
2483 | ||
2484 | static void disable_second_display_channel(void) | |
2485 | { | |
2486 | /* to disable second display channel. */ | |
2487 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); | |
2488 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); | |
2489 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | |
2490 | } | |
2491 | ||
b72a5070 HW |
2492 | static u_int16_t via_function3[] = { |
2493 | CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3, | |
2494 | CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3, | |
2495 | P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, | |
2496 | }; | |
2497 | ||
2498 | /* Get the BIOS-configured framebuffer size from PCI configuration space | |
2499 | * of function 3 in the respective chipset */ | |
2d280f75 | 2500 | int viafb_get_fb_size_from_pci(void) |
d61e0bf3 | 2501 | { |
b72a5070 HW |
2502 | int i; |
2503 | u_int8_t offset = 0; | |
2504 | u_int32_t FBSize; | |
2505 | u_int32_t VideoMemSize; | |
2506 | ||
2507 | /* search for the "FUNCTION3" device in this chipset */ | |
2508 | for (i = 0; i < ARRAY_SIZE(via_function3); i++) { | |
2509 | struct pci_dev *pdev; | |
2510 | ||
2511 | pdev = pci_get_device(PCI_VENDOR_ID_VIA, via_function3[i], | |
2512 | NULL); | |
2513 | if (!pdev) | |
2514 | continue; | |
2515 | ||
2516 | DEBUG_MSG(KERN_INFO "Device ID = %x\n", pdev->device); | |
d61e0bf3 | 2517 | |
b72a5070 HW |
2518 | switch (pdev->device) { |
2519 | case CLE266_FUNCTION3: | |
2520 | case KM400_FUNCTION3: | |
2521 | offset = 0xE0; | |
2522 | break; | |
d61e0bf3 JC |
2523 | case CN400_FUNCTION3: |
2524 | case CN700_FUNCTION3: | |
2525 | case CX700_FUNCTION3: | |
2526 | case KM800_FUNCTION3: | |
2527 | case KM890_FUNCTION3: | |
2528 | case P4M890_FUNCTION3: | |
2529 | case P4M900_FUNCTION3: | |
2530 | case VX800_FUNCTION3: | |
0306ab11 | 2531 | case VX855_FUNCTION3: |
b72a5070 HW |
2532 | /*case CN750_FUNCTION3: */ |
2533 | offset = 0xA0; | |
d61e0bf3 JC |
2534 | break; |
2535 | } | |
2536 | ||
b72a5070 | 2537 | if (!offset) |
d61e0bf3 | 2538 | break; |
b72a5070 HW |
2539 | |
2540 | pci_read_config_dword(pdev, offset, &FBSize); | |
2541 | pci_dev_put(pdev); | |
d61e0bf3 JC |
2542 | } |
2543 | ||
b72a5070 HW |
2544 | if (!offset) { |
2545 | printk(KERN_ERR "cannot determine framebuffer size\n"); | |
2546 | return -EIO; | |
2547 | } | |
d61e0bf3 JC |
2548 | |
2549 | FBSize = FBSize & 0x00007000; | |
2550 | DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize); | |
2551 | ||
2552 | if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) { | |
2553 | switch (FBSize) { | |
2554 | case 0x00004000: | |
2555 | VideoMemSize = (16 << 20); /*16M */ | |
2556 | break; | |
2557 | ||
2558 | case 0x00005000: | |
2559 | VideoMemSize = (32 << 20); /*32M */ | |
2560 | break; | |
2561 | ||
2562 | case 0x00006000: | |
2563 | VideoMemSize = (64 << 20); /*64M */ | |
2564 | break; | |
2565 | ||
2566 | default: | |
2567 | VideoMemSize = (32 << 20); /*32M */ | |
2568 | break; | |
2569 | } | |
2570 | } else { | |
2571 | switch (FBSize) { | |
2572 | case 0x00001000: | |
2573 | VideoMemSize = (8 << 20); /*8M */ | |
2574 | break; | |
2575 | ||
2576 | case 0x00002000: | |
2577 | VideoMemSize = (16 << 20); /*16M */ | |
2578 | break; | |
2579 | ||
2580 | case 0x00003000: | |
2581 | VideoMemSize = (32 << 20); /*32M */ | |
2582 | break; | |
2583 | ||
2584 | case 0x00004000: | |
2585 | VideoMemSize = (64 << 20); /*64M */ | |
2586 | break; | |
2587 | ||
2588 | case 0x00005000: | |
2589 | VideoMemSize = (128 << 20); /*128M */ | |
2590 | break; | |
2591 | ||
2592 | case 0x00006000: | |
2593 | VideoMemSize = (256 << 20); /*256M */ | |
2594 | break; | |
2595 | ||
0306ab11 HW |
2596 | case 0x00007000: /* Only on VX855/875 */ |
2597 | VideoMemSize = (512 << 20); /*512M */ | |
2598 | break; | |
2599 | ||
d61e0bf3 JC |
2600 | default: |
2601 | VideoMemSize = (32 << 20); /*32M */ | |
2602 | break; | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | return VideoMemSize; | |
2607 | } | |
2608 | ||
2609 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ | |
2610 | *p_gfx_dpa_setting) | |
2611 | { | |
2612 | switch (output_interface) { | |
2613 | case INTERFACE_DVP0: | |
2614 | { | |
2615 | /* DVP0 Clock Polarity and Adjust: */ | |
2616 | viafb_write_reg_mask(CR96, VIACR, | |
2617 | p_gfx_dpa_setting->DVP0, 0x0F); | |
2618 | ||
2619 | /* DVP0 Clock and Data Pads Driving: */ | |
2620 | viafb_write_reg_mask(SR1E, VIASR, | |
2621 | p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); | |
2622 | viafb_write_reg_mask(SR2A, VIASR, | |
2623 | p_gfx_dpa_setting->DVP0ClockDri_S1, | |
2624 | BIT4); | |
2625 | viafb_write_reg_mask(SR1B, VIASR, | |
2626 | p_gfx_dpa_setting->DVP0DataDri_S, BIT1); | |
2627 | viafb_write_reg_mask(SR2A, VIASR, | |
2628 | p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); | |
2629 | break; | |
2630 | } | |
2631 | ||
2632 | case INTERFACE_DVP1: | |
2633 | { | |
2634 | /* DVP1 Clock Polarity and Adjust: */ | |
2635 | viafb_write_reg_mask(CR9B, VIACR, | |
2636 | p_gfx_dpa_setting->DVP1, 0x0F); | |
2637 | ||
2638 | /* DVP1 Clock and Data Pads Driving: */ | |
2639 | viafb_write_reg_mask(SR65, VIASR, | |
2640 | p_gfx_dpa_setting->DVP1Driving, 0x0F); | |
2641 | break; | |
2642 | } | |
2643 | ||
2644 | case INTERFACE_DFP_HIGH: | |
2645 | { | |
2646 | viafb_write_reg_mask(CR97, VIACR, | |
2647 | p_gfx_dpa_setting->DFPHigh, 0x0F); | |
2648 | break; | |
2649 | } | |
2650 | ||
2651 | case INTERFACE_DFP_LOW: | |
2652 | { | |
2653 | viafb_write_reg_mask(CR99, VIACR, | |
2654 | p_gfx_dpa_setting->DFPLow, 0x0F); | |
2655 | break; | |
2656 | } | |
2657 | ||
2658 | case INTERFACE_DFP: | |
2659 | { | |
2660 | viafb_write_reg_mask(CR97, VIACR, | |
2661 | p_gfx_dpa_setting->DFPHigh, 0x0F); | |
2662 | viafb_write_reg_mask(CR99, VIACR, | |
2663 | p_gfx_dpa_setting->DFPLow, 0x0F); | |
2664 | break; | |
2665 | } | |
2666 | } | |
2667 | } | |
2668 | ||
d61e0bf3 JC |
2669 | /*According var's xres, yres fill var's other timing information*/ |
2670 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, | |
dd73d686 | 2671 | struct VideoModeTable *vmode_tbl) |
d61e0bf3 | 2672 | { |
d61e0bf3 JC |
2673 | struct crt_mode_table *crt_timing = NULL; |
2674 | struct display_timing crt_reg; | |
2675 | int i = 0, index = 0; | |
d61e0bf3 JC |
2676 | crt_timing = vmode_tbl->crtc; |
2677 | for (i = 0; i < vmode_tbl->mode_array; i++) { | |
2678 | index = i; | |
2679 | if (crt_timing[i].refresh_rate == refresh) | |
2680 | break; | |
2681 | } | |
2682 | ||
2683 | crt_reg = crt_timing[index].crtc; | |
d61e0bf3 JC |
2684 | var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh); |
2685 | var->left_margin = | |
2686 | crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); | |
2687 | var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; | |
2688 | var->hsync_len = crt_reg.hor_sync_end; | |
2689 | var->upper_margin = | |
2690 | crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); | |
2691 | var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; | |
2692 | var->vsync_len = crt_reg.ver_sync_end; | |
2693 | } |