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viafb: some small cleanup for global variables
[mirror_ubuntu-zesty-kernel.git] / drivers / video / via / lcd.c
CommitLineData
ac6c97e2
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
ec66841e
JC		 21#include <linux/via-core.h>
22#include <linux/via_i2c.h>
ac6c97e2 23#include "global.h"
ac6c97e2 24
dd73d686
FTS		 25#define viafb_compact_res(x, y) (((x)<<16)|(y))
26
91336712
FTS		 27/* CLE266 Software Power Sequence */
28/* {Mask}, {Data}, {Delay} */
23e5abd5
SH		 29static const int PowerSequenceOn[3][3] = {
30 {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
31};
32static const int PowerSequenceOff[3][3] = {
33 {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
34};
91336712 35
ac6c97e2
JC		 36static struct _lcd_scaling_factor lcd_scaling_factor = {
37 /* LCD Horizontal Scaling Factor Register */
38 {LCD_HOR_SCALING_FACTOR_REG_NUM,
39 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
40 /* LCD Vertical Scaling Factor Register */
41 {LCD_VER_SCALING_FACTOR_REG_NUM,
42 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
43};
44static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
45 /* LCD Horizontal Scaling Factor Register */
46 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
47 /* LCD Vertical Scaling Factor Register */
48 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
49};
50
51static int check_lvds_chip(int device_id_subaddr, int device_id);
52static bool lvds_identify_integratedlvds(void);
f4ab2f7a 53static void __devinit fp_id_to_vindex(int panel_id);
ac6c97e2
JC		 54static int lvds_register_read(int index);
55static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
56 int panel_vres);
ac6c97e2
JC		 57static void via_pitch_alignment_patch_lcd(
58 struct lvds_setting_information *plvds_setting_info,
59 struct lvds_chip_information
60 *plvds_chip_info);
61static void lcd_patch_skew_dvp0(struct lvds_setting_information
62 *plvds_setting_info,
63 struct lvds_chip_information *plvds_chip_info);
64static void lcd_patch_skew_dvp1(struct lvds_setting_information
65 *plvds_setting_info,
66 struct lvds_chip_information *plvds_chip_info);
67static void lcd_patch_skew(struct lvds_setting_information
68 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
69
70static void integrated_lvds_disable(struct lvds_setting_information
71 *plvds_setting_info,
72 struct lvds_chip_information *plvds_chip_info);
73static void integrated_lvds_enable(struct lvds_setting_information
74 *plvds_setting_info,
75 struct lvds_chip_information *plvds_chip_info);
76static void lcd_powersequence_off(void);
77static void lcd_powersequence_on(void);
78static void fill_lcd_format(void);
79static void check_diport_of_integrated_lvds(
80 struct lvds_chip_information *plvds_chip_info,
81 struct lvds_setting_information
82 *plvds_setting_info);
83static struct display_timing lcd_centering_timging(struct display_timing
84 mode_crt_reg,
85 struct display_timing panel_crt_reg);
ac6c97e2
JC		 86
87static int check_lvds_chip(int device_id_subaddr, int device_id)
88{
89 if (lvds_register_read(device_id_subaddr) == device_id)
90 return OK;
91 else
92 return FAIL;
93}
94
f4ab2f7a 95void __devinit viafb_init_lcd_size(void)
ac6c97e2
JC		 96{
97 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
ac6c97e2 98
cc3fd679 99 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 100 viaparinfo->lvds_setting_info2->lcd_panel_hres =
101 viaparinfo->lvds_setting_info->lcd_panel_hres;
102 viaparinfo->lvds_setting_info2->lcd_panel_vres =
103 viaparinfo->lvds_setting_info->lcd_panel_vres;
104 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
105 viaparinfo->lvds_setting_info->device_lcd_dualedge;
106 viaparinfo->lvds_setting_info2->LCDDithering =
107 viaparinfo->lvds_setting_info->LCDDithering;
108}
109
110static bool lvds_identify_integratedlvds(void)
111{
112 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
113 /* Two dual channel LCD (Internal LVDS + External LVDS): */
114 /* If we have an external LVDS, such as VT1636, we should
115 have its chip ID already. */
116 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
117 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
118 INTEGRATED_LVDS;
2c0e0c88
JP		 119 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
120 "(Internal LVDS + External LVDS)\n");
ac6c97e2
JC		 121 } else {
122 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
123 INTEGRATED_LVDS;
2c0e0c88
JP		 124 DEBUG_MSG(KERN_INFO "Not found external LVDS, "
125 "so can't support two dual channel LVDS!\n");
ac6c97e2
JC		 126 }
127 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
128 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
129 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
130 INTEGRATED_LVDS;
131 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
132 INTEGRATED_LVDS;
2c0e0c88
JP		 133 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
134 "(Internal LVDS + Internal LVDS)\n");
ac6c97e2
JC		 135 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
136 /* If we have found external LVDS, just use it,
137 otherwise, we will use internal LVDS as default. */
138 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
139 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
140 INTEGRATED_LVDS;
141 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
142 }
143 } else {
144 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
145 NON_LVDS_TRANSMITTER;
146 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
147 return false;
148 }
149
150 return true;
151}
152
f4ab2f7a 153int __devinit viafb_lvds_trasmitter_identify(void)
ac6c97e2 154{
f045f77b
JC		 155 if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
156 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
ac6c97e2 157 DEBUG_MSG(KERN_INFO
277d32a3 158 "Found VIA VT1636 LVDS on port i2c 0x31\n");
ac6c97e2 159 } else {
f045f77b 160 if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
ac6c97e2 161 viaparinfo->chip_info->lvds_chip_info.i2c_port =
f045f77b 162 VIA_PORT_2C;
ac6c97e2 163 DEBUG_MSG(KERN_INFO
277d32a3 164 "Found VIA VT1636 LVDS on port gpio 0x2c\n");
ac6c97e2
JC		 165 }
166 }
167
168 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
169 lvds_identify_integratedlvds();
170
171 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
172 return true;
173 /* Check for VT1631: */
174 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
175 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
176 VT1631_LVDS_I2C_ADDR;
177
178 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
179 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
180 DEBUG_MSG(KERN_INFO "\n %2d",
181 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
182 DEBUG_MSG(KERN_INFO "\n %2d",
183 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
184 return OK;
185 }
186
187 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
188 NON_LVDS_TRANSMITTER;
189 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
190 VT1631_LVDS_I2C_ADDR;
191 return FAIL;
192}
193
f4ab2f7a 194static void __devinit fp_id_to_vindex(int panel_id)
ac6c97e2
JC		 195{
196 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
197
198 if (panel_id > LCD_PANEL_ID_MAXIMUM)
199 viafb_lcd_panel_id = panel_id =
200 viafb_read_reg(VIACR, CR3F) & 0x0F;
201
202 switch (panel_id) {
203 case 0x0:
204 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
205 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
ac6c97e2
JC		 206 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
207 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 208 break;
209 case 0x1:
210 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
211 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
ac6c97e2
JC		 212 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
213 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 214 break;
215 case 0x2:
216 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
217 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 218 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
219 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 220 break;
221 case 0x3:
222 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
223 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 224 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
225 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 226 break;
227 case 0x4:
228 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
229 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
ac6c97e2
JC		 230 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
231 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 232 break;
233 case 0x5:
234 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
235 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
ac6c97e2
JC		 236 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
237 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 238 break;
239 case 0x6:
240 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
241 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
ac6c97e2
JC		 242 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
243 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 244 break;
245 case 0x8:
246 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
247 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
ac6c97e2
JC		 248 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
249 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 250 break;
251 case 0x9:
252 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
253 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 254 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
255 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 256 break;
257 case 0xA:
258 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
259 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 260 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
261 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 262 break;
263 case 0xB:
264 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
265 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 266 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
267 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 268 break;
269 case 0xC:
270 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
271 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 272 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
273 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 274 break;
275 case 0xD:
276 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
277 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
ac6c97e2
JC		 278 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
279 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 280 break;
281 case 0xE:
282 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
283 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
ac6c97e2
JC		 284 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
285 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 286 break;
287 case 0xF:
288 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
289 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
ac6c97e2
JC		 290 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
291 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 292 break;
293 case 0x10:
294 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
295 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 296 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
297 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 298 break;
299 case 0x11:
300 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
301 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
ac6c97e2
JC		 302 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
303 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 304 break;
305 case 0x12:
306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
307 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 308 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
309 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 310 break;
311 case 0x13:
312 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
313 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
ac6c97e2
JC		 314 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
315 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 316 break;
317 case 0x14:
318 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
319 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 320 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
321 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 322 break;
323 case 0x15:
324 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
325 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
ac6c97e2
JC		 326 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
327 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 328 break;
329 case 0x16:
330 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
331 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
ac6c97e2
JC		 332 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
333 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2 334 break;
c205d932
CB		 335 case 0x17:
336 /* OLPC XO-1.5 panel */
337 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
338 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
c205d932
CB		 339 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
340 viaparinfo->lvds_setting_info->LCDDithering = 0;
341 break;
ac6c97e2
JC		 342 default:
343 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
344 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
ac6c97e2
JC		 345 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
346 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 347 }
348}
349
350static int lvds_register_read(int index)
351{
352 u8 data;
353
f045f77b 354 viafb_i2c_readbyte(VIA_PORT_2C,
277d32a3 355 (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
ac6c97e2
JC		 356 (u8) index, &data);
357 return data;
358}
359
360static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
361 int panel_vres)
362{
363 int reg_value = 0;
364 int viafb_load_reg_num;
365 struct io_register *reg = NULL;
366
367 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
368
369 /* LCD Scaling Enable */
370 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
ac6c97e2
JC		 371
372 /* Check if expansion for horizontal */
119b953a 373 if (set_hres < panel_hres) {
ac6c97e2
JC		 374 /* Load Horizontal Scaling Factor */
375 switch (viaparinfo->chip_info->gfx_chip_name) {
376 case UNICHROME_CLE266:
377 case UNICHROME_K400:
378 reg_value =
379 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
380 viafb_load_reg_num =
381 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
382 reg_num;
383 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
384 viafb_load_reg(reg_value,
385 viafb_load_reg_num, reg, VIACR);
386 break;
387 case UNICHROME_K800:
388 case UNICHROME_PM800:
389 case UNICHROME_CN700:
390 case UNICHROME_CX700:
391 case UNICHROME_K8M890:
392 case UNICHROME_P4M890:
4a73d70e 393 case UNICHROME_P4M900:
f1ad752a
FTS		 394 case UNICHROME_CN750:
395 case UNICHROME_VX800:
396 case UNICHROME_VX855:
51f4332b 397 case UNICHROME_VX900:
ac6c97e2
JC		 398 reg_value =
399 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
400 /* Horizontal scaling enabled */
401 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
402 viafb_load_reg_num =
403 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
404 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
405 viafb_load_reg(reg_value,
406 viafb_load_reg_num, reg, VIACR);
407 break;
408 }
409
410 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
411 } else {
412 /* Horizontal scaling disabled */
413 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
414 }
415
416 /* Check if expansion for vertical */
119b953a 417 if (set_vres < panel_vres) {
ac6c97e2
JC		 418 /* Load Vertical Scaling Factor */
419 switch (viaparinfo->chip_info->gfx_chip_name) {
420 case UNICHROME_CLE266:
421 case UNICHROME_K400:
422 reg_value =
423 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
424 viafb_load_reg_num =
425 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
426 reg_num;
427 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
428 viafb_load_reg(reg_value,
429 viafb_load_reg_num, reg, VIACR);
430 break;
431 case UNICHROME_K800:
432 case UNICHROME_PM800:
433 case UNICHROME_CN700:
434 case UNICHROME_CX700:
435 case UNICHROME_K8M890:
436 case UNICHROME_P4M890:
4a73d70e 437 case UNICHROME_P4M900:
f1ad752a
FTS		 438 case UNICHROME_CN750:
439 case UNICHROME_VX800:
440 case UNICHROME_VX855:
51f4332b 441 case UNICHROME_VX900:
ac6c97e2
JC		 442 reg_value =
443 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
444 /* Vertical scaling enabled */
445 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
446 viafb_load_reg_num =
447 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
448 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
449 viafb_load_reg(reg_value,
450 viafb_load_reg_num, reg, VIACR);
451 break;
452 }
453
454 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
455 } else {
456 /* Vertical scaling disabled */
457 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
458 }
459}
460
ac6c97e2
JC		 461static void via_pitch_alignment_patch_lcd(
462 struct lvds_setting_information *plvds_setting_info,
463 struct lvds_chip_information
464 *plvds_chip_info)
465{
466 unsigned char cr13, cr35, cr65, cr66, cr67;
467 unsigned long dwScreenPitch = 0;
468 unsigned long dwPitch;
469
470 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
471 if (dwPitch & 0x1F) {
472 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
473 if (plvds_setting_info->iga_path == IGA2) {
474 if (plvds_setting_info->bpp > 8) {
475 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
476 viafb_write_reg(CR66, VIACR, cr66);
477 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
478 cr67 |=
479 (unsigned
480 char)((dwScreenPitch & 0x300) >> 8);
481 viafb_write_reg(CR67, VIACR, cr67);
482 }
483
484 /* Fetch Count */
485 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
486 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
487 viafb_write_reg(CR67, VIACR, cr67);
488 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
489 cr65 += 2;
490 viafb_write_reg(CR65, VIACR, cr65);
491 } else {
492 if (plvds_setting_info->bpp > 8) {
493 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
494 viafb_write_reg(CR13, VIACR, cr13);
495 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
496 cr35 |=
497 (unsigned
498 char)((dwScreenPitch & 0x700) >> 3);
499 viafb_write_reg(CR35, VIACR, cr35);
500 }
501 }
502 }
503}
504static void lcd_patch_skew_dvp0(struct lvds_setting_information
505 *plvds_setting_info,
506 struct lvds_chip_information *plvds_chip_info)
507{
508 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
509 switch (viaparinfo->chip_info->gfx_chip_name) {
510 case UNICHROME_P4M900:
511 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
512 plvds_chip_info);
513 break;
514 case UNICHROME_P4M890:
515 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
516 plvds_chip_info);
517 break;
518 }
519 }
520}
521static void lcd_patch_skew_dvp1(struct lvds_setting_information
522 *plvds_setting_info,
523 struct lvds_chip_information *plvds_chip_info)
524{
525 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
526 switch (viaparinfo->chip_info->gfx_chip_name) {
527 case UNICHROME_CX700:
528 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
529 plvds_chip_info);
530 break;
531 }
532 }
533}
534static void lcd_patch_skew(struct lvds_setting_information
535 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
536{
537 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
538 switch (plvds_chip_info->output_interface) {
539 case INTERFACE_DVP0:
540 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
541 break;
542 case INTERFACE_DVP1:
543 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
544 break;
545 case INTERFACE_DFP_LOW:
546 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
547 viafb_write_reg_mask(CR99, VIACR, 0x08,
548 BIT0 + BIT1 + BIT2 + BIT3);
549 }
550 break;
551 }
552}
553
554/* LCD Set Mode */
555void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
556 struct lvds_setting_information *plvds_setting_info,
557 struct lvds_chip_information *plvds_chip_info)
558{
ac6c97e2
JC		 559 int set_iga = plvds_setting_info->iga_path;
560 int mode_bpp = plvds_setting_info->bpp;
dd73d686
FTS		 561 int set_hres = plvds_setting_info->h_active;
562 int set_vres = plvds_setting_info->v_active;
563 int panel_hres = plvds_setting_info->lcd_panel_hres;
564 int panel_vres = plvds_setting_info->lcd_panel_vres;
fd3cc698 565 u32 pll_D_N, clock;
ac6c97e2
JC		 566 struct display_timing mode_crt_reg, panel_crt_reg;
567 struct crt_mode_table *panel_crt_table = NULL;
dd73d686
FTS		 568 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
569 panel_vres);
ac6c97e2
JC		 570
571 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
572 /* Get mode table */
573 mode_crt_reg = mode_crt_table->crtc;
574 /* Get panel table Pointer */
ac6c97e2
JC		 575 panel_crt_table = vmode_tbl->crtc;
576 panel_crt_reg = panel_crt_table->crtc;
577 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
ac6c97e2
JC		 578 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
579 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
fd3cc698
FTS		 580 clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
581 * panel_crt_table->refresh_rate;
582 plvds_setting_info->vclk = clock;
ac6c97e2
JC		 583 if (set_iga == IGA1) {
584 /* IGA1 doesn't have LCD scaling, so set it as centering. */
585 viafb_load_crtc_timing(lcd_centering_timging
586 (mode_crt_reg, panel_crt_reg), IGA1);
587 } else {
588 /* Expansion */
119b953a
FTS		 589 if (plvds_setting_info->display_method == LCD_EXPANDSION
590 && (set_hres < panel_hres || set_vres < panel_vres)) {
ac6c97e2
JC		 591 /* expansion timing IGA2 loaded panel set timing*/
592 viafb_load_crtc_timing(panel_crt_reg, IGA2);
593 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
594 load_lcd_scaling(set_hres, set_vres, panel_hres,
595 panel_vres);
596 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
597 } else { /* Centering */
598 /* centering timing IGA2 always loaded panel
599 and mode releative timing */
600 viafb_load_crtc_timing(lcd_centering_timging
601 (mode_crt_reg, panel_crt_reg), IGA2);
602 viafb_write_reg_mask(CR79, VIACR, 0x00,
603 BIT0 + BIT1 + BIT2);
604 /* LCD scaling disabled */
605 }
606 }
607
4bbac05f
FTS		 608 /* Fetch count for IGA2 only */
609 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
ac6c97e2 610
4bbac05f
FTS		 611 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
612 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
613 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
ac6c97e2
JC		 614
615 fill_lcd_format();
616
fd3cc698 617 pll_D_N = viafb_get_clk_value(clock);
ac6c97e2
JC		 618 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
619 viafb_set_vclock(pll_D_N, set_iga);
ac6c97e2
JC		 620 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
621
622 /* If K8M800, enable LCD Prefetch Mode. */
623 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
624 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
625 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
626
ac6c97e2
JC		 627 /* Patch for non 32bit alignment mode */
628 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
629}
630
631static void integrated_lvds_disable(struct lvds_setting_information
632 *plvds_setting_info,
633 struct lvds_chip_information *plvds_chip_info)
634{
635 bool turn_off_first_powersequence = false;
636 bool turn_off_second_powersequence = false;
637 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
638 turn_off_first_powersequence = true;
639 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
640 turn_off_first_powersequence = true;
641 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
642 turn_off_second_powersequence = true;
643 if (turn_off_second_powersequence) {
644 /* Use second power sequence control: */
645
646 /* Turn off power sequence. */
647 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
648
649 /* Turn off back light. */
650 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
651 }
652 if (turn_off_first_powersequence) {
653 /* Use first power sequence control: */
654
655 /* Turn off power sequence. */
656 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
657
658 /* Turn off back light. */
659 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
660 }
661
ac6c97e2
JC		 662 /* Power off LVDS channel. */
663 switch (plvds_chip_info->output_interface) {
664 case INTERFACE_LVDS0:
665 {
666 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
667 break;
668 }
669
670 case INTERFACE_LVDS1:
671 {
672 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
673 break;
674 }
675
676 case INTERFACE_LVDS0LVDS1:
677 {
678 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
679 break;
680 }
681 }
682}
683
684static void integrated_lvds_enable(struct lvds_setting_information
685 *plvds_setting_info,
686 struct lvds_chip_information *plvds_chip_info)
687{
ac6c97e2
JC		 688 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
689 plvds_chip_info->output_interface);
690 if (plvds_setting_info->lcd_mode == LCD_SPWG)
691 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
e6bf0d2c 692 else
ac6c97e2 693 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
ac6c97e2 694
e6bf0d2c
HW		 695 switch (plvds_chip_info->output_interface) {
696 case INTERFACE_LVDS0LVDS1:
697 case INTERFACE_LVDS0:
ac6c97e2 698 /* Use first power sequence control: */
ac6c97e2
JC		 699 /* Use hardware control power sequence. */
700 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
ac6c97e2
JC		 701 /* Turn on back light. */
702 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
ac6c97e2
JC		 703 /* Turn on hardware power sequence. */
704 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
e6bf0d2c
HW		 705 break;
706 case INTERFACE_LVDS1:
707 /* Use second power sequence control: */
708 /* Use hardware control power sequence. */
709 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
710 /* Turn on back light. */
711 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
712 /* Turn on hardware power sequence. */
713 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
714 break;
ac6c97e2
JC		 715 }
716
ac6c97e2
JC		 717 /* Power on LVDS channel. */
718 switch (plvds_chip_info->output_interface) {
719 case INTERFACE_LVDS0:
720 {
721 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
722 break;
723 }
724
725 case INTERFACE_LVDS1:
726 {
727 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
728 break;
729 }
730
731 case INTERFACE_LVDS0LVDS1:
732 {
733 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
734 break;
735 }
736 }
737}
738
739void viafb_lcd_disable(void)
740{
741
742 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
743 lcd_powersequence_off();
744 /* DI1 pad off */
745 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
746 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
747 if (viafb_LCD2_ON
748 && (INTEGRATED_LVDS ==
749 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
750 integrated_lvds_disable(viaparinfo->lvds_setting_info,
751 &viaparinfo->chip_info->lvds_chip_info2);
752 if (INTEGRATED_LVDS ==
753 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
754 integrated_lvds_disable(viaparinfo->lvds_setting_info,
755 &viaparinfo->chip_info->lvds_chip_info);
756 if (VT1636_LVDS == viaparinfo->chip_info->
757 lvds_chip_info.lvds_chip_name)
758 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
759 &viaparinfo->chip_info->lvds_chip_info);
760 } else if (VT1636_LVDS ==
761 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
762 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
763 &viaparinfo->chip_info->lvds_chip_info);
764 } else {
ac6c97e2
JC		 765 /* Backlight off */
766 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
767 /* 24 bit DI data paht off */
768 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
ac6c97e2
JC		 769 }
770
771 /* Disable expansion bit */
772 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
ac6c97e2
JC		 773 /* Simultaneout disabled */
774 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
ac6c97e2
JC		 775}
776
cd7e9103
FTS		 777static void set_lcd_output_path(int set_iga, int output_interface)
778{
779 switch (output_interface) {
780 case INTERFACE_DFP:
781 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
782 || (UNICHROME_P4M890 ==
783 viaparinfo->chip_info->gfx_chip_name))
784 viafb_write_reg_mask(CR97, VIACR, 0x84,
785 BIT7 + BIT2 + BIT1 + BIT0);
786 case INTERFACE_DVP0:
787 case INTERFACE_DVP1:
788 case INTERFACE_DFP_HIGH:
789 case INTERFACE_DFP_LOW:
790 if (set_iga == IGA2)
791 viafb_write_reg(CR91, VIACR, 0x00);
792 break;
793 }
794}
795
ac6c97e2
JC		 796void viafb_lcd_enable(void)
797{
cd7e9103
FTS		 798 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
799 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
800 set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
801 viaparinfo->chip_info->lvds_chip_info.output_interface);
802 if (viafb_LCD2_ON)
803 set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
804 viaparinfo->chip_info->
805 lvds_chip_info2.output_interface);
806
ac6c97e2
JC		 807 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
808 /* DI1 pad on */
809 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
810 lcd_powersequence_on();
811 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
812 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
813 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
814 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
815 &viaparinfo->chip_info->lvds_chip_info2);
816 if (INTEGRATED_LVDS ==
817 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
818 integrated_lvds_enable(viaparinfo->lvds_setting_info,
819 &viaparinfo->chip_info->lvds_chip_info);
820 if (VT1636_LVDS == viaparinfo->chip_info->
821 lvds_chip_info.lvds_chip_name)
822 viafb_enable_lvds_vt1636(viaparinfo->
823 lvds_setting_info, &viaparinfo->chip_info->
824 lvds_chip_info);
825 } else if (VT1636_LVDS ==
826 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
827 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
828 &viaparinfo->chip_info->lvds_chip_info);
829 } else {
ac6c97e2
JC		 830 /* Backlight on */
831 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
832 /* 24 bit DI data paht on */
833 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
ac6c97e2
JC		 834 /* LCD enabled */
835 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
836 }
ac6c97e2
JC		 837}
838
839static void lcd_powersequence_off(void)
840{
841 int i, mask, data;
842
843 /* Software control power sequence */
844 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
845
846 for (i = 0; i < 3; i++) {
847 mask = PowerSequenceOff[0][i];
848 data = PowerSequenceOff[1][i] & mask;
849 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
850 udelay(PowerSequenceOff[2][i]);
851 }
852
853 /* Disable LCD */
854 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
855}
856
857static void lcd_powersequence_on(void)
858{
859 int i, mask, data;
860
861 /* Software control power sequence */
862 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
863
864 /* Enable LCD */
865 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
866
867 for (i = 0; i < 3; i++) {
868 mask = PowerSequenceOn[0][i];
869 data = PowerSequenceOn[1][i] & mask;
870 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
871 udelay(PowerSequenceOn[2][i]);
872 }
873
874 udelay(1);
875}
876
877static void fill_lcd_format(void)
878{
879 u8 bdithering = 0, bdual = 0;
880
881 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
882 bdual = BIT4;
883 if (viaparinfo->lvds_setting_info->LCDDithering)
884 bdithering = BIT0;
885 /* Dual & Dithering */
886 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
887}
888
889static void check_diport_of_integrated_lvds(
890 struct lvds_chip_information *plvds_chip_info,
891 struct lvds_setting_information
892 *plvds_setting_info)
893{
894 /* Determine LCD DI Port by hardware layout. */
895 switch (viafb_display_hardware_layout) {
896 case HW_LAYOUT_LCD_ONLY:
897 {
898 if (plvds_setting_info->device_lcd_dualedge) {
899 plvds_chip_info->output_interface =
900 INTERFACE_LVDS0LVDS1;
901 } else {
902 plvds_chip_info->output_interface =
903 INTERFACE_LVDS0;
904 }
905
906 break;
907 }
908
909 case HW_LAYOUT_DVI_ONLY:
910 {
911 plvds_chip_info->output_interface = INTERFACE_NONE;
912 break;
913 }
914
915 case HW_LAYOUT_LCD1_LCD2:
916 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
917 {
918 plvds_chip_info->output_interface =
919 INTERFACE_LVDS0LVDS1;
920 break;
921 }
922
923 case HW_LAYOUT_LCD_DVI:
924 {
925 plvds_chip_info->output_interface = INTERFACE_LVDS1;
926 break;
927 }
928
929 default:
930 {
931 plvds_chip_info->output_interface = INTERFACE_LVDS1;
932 break;
933 }
934 }
935
936 DEBUG_MSG(KERN_INFO
937 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
938 viafb_display_hardware_layout,
939 plvds_chip_info->output_interface);
940}
941
f4ab2f7a 942void __devinit viafb_init_lvds_output_interface(struct lvds_chip_information
ac6c97e2
JC		 943 *plvds_chip_info,
944 struct lvds_setting_information
945 *plvds_setting_info)
946{
947 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
948 /*Do nothing, lcd port is specified by module parameter */
949 return;
950 }
951
952 switch (plvds_chip_info->lvds_chip_name) {
953
954 case VT1636_LVDS:
955 switch (viaparinfo->chip_info->gfx_chip_name) {
956 case UNICHROME_CX700:
957 plvds_chip_info->output_interface = INTERFACE_DVP1;
958 break;
959 case UNICHROME_CN700:
960 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
961 break;
962 default:
963 plvds_chip_info->output_interface = INTERFACE_DVP0;
964 break;
965 }
966 break;
967
968 case INTEGRATED_LVDS:
969 check_diport_of_integrated_lvds(plvds_chip_info,
970 plvds_setting_info);
971 break;
972
973 default:
974 switch (viaparinfo->chip_info->gfx_chip_name) {
975 case UNICHROME_K8M890:
976 case UNICHROME_P4M900:
977 case UNICHROME_P4M890:
978 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
979 break;
980 default:
981 plvds_chip_info->output_interface = INTERFACE_DFP;
982 break;
983 }
984 break;
985 }
986}
987
988static struct display_timing lcd_centering_timging(struct display_timing
989 mode_crt_reg,
990 struct display_timing panel_crt_reg)
991{
992 struct display_timing crt_reg;
993
994 crt_reg.hor_total = panel_crt_reg.hor_total;
995 crt_reg.hor_addr = mode_crt_reg.hor_addr;
996 crt_reg.hor_blank_start =
997 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
998 crt_reg.hor_addr;
999 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1000 crt_reg.hor_sync_start =
1001 (panel_crt_reg.hor_sync_start -
1002 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1003 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1004
1005 crt_reg.ver_total = panel_crt_reg.ver_total;
1006 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1007 crt_reg.ver_blank_start =
1008 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1009 crt_reg.ver_addr;
1010 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1011 crt_reg.ver_sync_start =
1012 (panel_crt_reg.ver_sync_start -
1013 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1014 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1015
1016 return crt_reg;
1017}
1018
ac6c97e2
JC		 1019bool viafb_lcd_get_mobile_state(bool *mobile)
1020{
b65d6040 1021 unsigned char __iomem *romptr, *tableptr, *biosptr;
ac6c97e2 1022 u8 core_base;
ac6c97e2 1023 /* Rom address */
b65d6040
SH		 1024 const u32 romaddr = 0x000C0000;
1025 u16 start_pattern;
ac6c97e2
JC		 1026
1027 biosptr = ioremap(romaddr, 0x10000);
b65d6040 1028 start_pattern = readw(biosptr);
ac6c97e2 1029
ac6c97e2
JC		 1030 /* Compare pattern */
1031 if (start_pattern == 0xAA55) {
1032 /* Get the start of Table */
1033 /* 0x1B means BIOS offset position */
1034 romptr = biosptr + 0x1B;
b65d6040 1035 tableptr = biosptr + readw(romptr);
ac6c97e2
JC		 1036
1037 /* Get the start of biosver structure */
1038 /* 18 means BIOS version position. */
1039 romptr = tableptr + 18;
b65d6040 1040 romptr = biosptr + readw(romptr);
ac6c97e2
JC		 1041
1042 /* The offset should be 44, but the
1043 actual image is less three char. */
1044 /* pRom += 44; */
1045 romptr += 41;
1046
b65d6040 1047 core_base = readb(romptr);
ac6c97e2
JC		 1048
1049 if (core_base & 0x8)
1050 *mobile = false;
1051 else
1052 *mobile = true;
1053 /* release memory */
1054 iounmap(biosptr);
1055
1056 return true;
1057 } else {
1058 iounmap(biosptr);
1059 return false;
1060 }
1061}
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