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viafb: Add 1200x900 DCON/LCD panel modes for OLPC XO-1.5
[mirror_ubuntu-artful-kernel.git] / drivers / video / via / lcd.c
CommitLineData
ac6c97e2
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23#include "lcdtbl.h"
24
dd73d686
FTS		 25#define viafb_compact_res(x, y) (((x)<<16)|(y))
26
ac6c97e2
JC		 27static struct _lcd_scaling_factor lcd_scaling_factor = {
28 /* LCD Horizontal Scaling Factor Register */
29 {LCD_HOR_SCALING_FACTOR_REG_NUM,
30 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
31 /* LCD Vertical Scaling Factor Register */
32 {LCD_VER_SCALING_FACTOR_REG_NUM,
33 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
34};
35static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
36 /* LCD Horizontal Scaling Factor Register */
37 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
38 /* LCD Vertical Scaling Factor Register */
39 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
40};
41
42static int check_lvds_chip(int device_id_subaddr, int device_id);
43static bool lvds_identify_integratedlvds(void);
9b24b00c 44static void fp_id_to_vindex(int panel_id);
ac6c97e2
JC		 45static int lvds_register_read(int index);
46static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
47 int panel_vres);
ac6c97e2
JC		 48static void via_pitch_alignment_patch_lcd(
49 struct lvds_setting_information *plvds_setting_info,
50 struct lvds_chip_information
51 *plvds_chip_info);
52static void lcd_patch_skew_dvp0(struct lvds_setting_information
53 *plvds_setting_info,
54 struct lvds_chip_information *plvds_chip_info);
55static void lcd_patch_skew_dvp1(struct lvds_setting_information
56 *plvds_setting_info,
57 struct lvds_chip_information *plvds_chip_info);
58static void lcd_patch_skew(struct lvds_setting_information
59 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
60
61static void integrated_lvds_disable(struct lvds_setting_information
62 *plvds_setting_info,
63 struct lvds_chip_information *plvds_chip_info);
64static void integrated_lvds_enable(struct lvds_setting_information
65 *plvds_setting_info,
66 struct lvds_chip_information *plvds_chip_info);
67static void lcd_powersequence_off(void);
68static void lcd_powersequence_on(void);
69static void fill_lcd_format(void);
70static void check_diport_of_integrated_lvds(
71 struct lvds_chip_information *plvds_chip_info,
72 struct lvds_setting_information
73 *plvds_setting_info);
74static struct display_timing lcd_centering_timging(struct display_timing
75 mode_crt_reg,
76 struct display_timing panel_crt_reg);
ac6c97e2
JC		 77static void viafb_load_scaling_factor_for_p4m900(int set_hres,
78 int set_vres, int panel_hres, int panel_vres);
79
80static int check_lvds_chip(int device_id_subaddr, int device_id)
81{
82 if (lvds_register_read(device_id_subaddr) == device_id)
83 return OK;
84 else
85 return FAIL;
86}
87
88void viafb_init_lcd_size(void)
89{
90 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
91 DEBUG_MSG(KERN_INFO
92 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
93 viaparinfo->lvds_setting_info->get_lcd_size_method);
94
95 switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
96 case GET_LCD_SIZE_BY_SYSTEM_BIOS:
97 break;
98 case GET_LCD_SZIE_BY_HW_STRAPPING:
99 break;
100 case GET_LCD_SIZE_BY_VGA_BIOS:
101 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
9b24b00c 102 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 103 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
104 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 105 break;
106 case GET_LCD_SIZE_BY_USER_SETTING:
107 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
9b24b00c 108 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 109 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
110 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 111 break;
112 default:
113 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
114 viaparinfo->lvds_setting_info->lcd_panel_id =
115 LCD_PANEL_ID1_800X600;
9b24b00c 116 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
ac6c97e2
JC		 117 }
118 viaparinfo->lvds_setting_info2->lcd_panel_id =
119 viaparinfo->lvds_setting_info->lcd_panel_id;
ac6c97e2
JC		 120 viaparinfo->lvds_setting_info2->lcd_panel_hres =
121 viaparinfo->lvds_setting_info->lcd_panel_hres;
122 viaparinfo->lvds_setting_info2->lcd_panel_vres =
123 viaparinfo->lvds_setting_info->lcd_panel_vres;
124 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
125 viaparinfo->lvds_setting_info->device_lcd_dualedge;
126 viaparinfo->lvds_setting_info2->LCDDithering =
127 viaparinfo->lvds_setting_info->LCDDithering;
128}
129
130static bool lvds_identify_integratedlvds(void)
131{
132 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
133 /* Two dual channel LCD (Internal LVDS + External LVDS): */
134 /* If we have an external LVDS, such as VT1636, we should
135 have its chip ID already. */
136 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
137 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
138 INTEGRATED_LVDS;
2c0e0c88
JP		 139 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
140 "(Internal LVDS + External LVDS)\n");
ac6c97e2
JC		 141 } else {
142 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
143 INTEGRATED_LVDS;
2c0e0c88
JP		 144 DEBUG_MSG(KERN_INFO "Not found external LVDS, "
145 "so can't support two dual channel LVDS!\n");
ac6c97e2
JC		 146 }
147 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
148 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
149 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
150 INTEGRATED_LVDS;
151 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
152 INTEGRATED_LVDS;
2c0e0c88
JP		 153 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
154 "(Internal LVDS + Internal LVDS)\n");
ac6c97e2
JC		 155 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
156 /* If we have found external LVDS, just use it,
157 otherwise, we will use internal LVDS as default. */
158 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
159 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
160 INTEGRATED_LVDS;
161 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
162 }
163 } else {
164 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
165 NON_LVDS_TRANSMITTER;
166 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
167 return false;
168 }
169
170 return true;
171}
172
173int viafb_lvds_trasmitter_identify(void)
174{
c4df5489 175 viaparinfo->shared->i2c_stuff.i2c_port = I2CPORTINDEX;
ac6c97e2
JC		 176 if (viafb_lvds_identify_vt1636()) {
177 viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
178 DEBUG_MSG(KERN_INFO
179 "Found VIA VT1636 LVDS on port i2c 0x31 \n");
180 } else {
c4df5489 181 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
ac6c97e2
JC		 182 if (viafb_lvds_identify_vt1636()) {
183 viaparinfo->chip_info->lvds_chip_info.i2c_port =
184 GPIOPORTINDEX;
185 DEBUG_MSG(KERN_INFO
186 "Found VIA VT1636 LVDS on port gpio 0x2c \n");
187 }
188 }
189
190 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
191 lvds_identify_integratedlvds();
192
193 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
194 return true;
195 /* Check for VT1631: */
196 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
197 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
198 VT1631_LVDS_I2C_ADDR;
199
200 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
201 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
202 DEBUG_MSG(KERN_INFO "\n %2d",
203 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
204 DEBUG_MSG(KERN_INFO "\n %2d",
205 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
206 return OK;
207 }
208
209 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
210 NON_LVDS_TRANSMITTER;
211 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
212 VT1631_LVDS_I2C_ADDR;
213 return FAIL;
214}
215
9b24b00c 216static void fp_id_to_vindex(int panel_id)
ac6c97e2
JC		 217{
218 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
219
220 if (panel_id > LCD_PANEL_ID_MAXIMUM)
221 viafb_lcd_panel_id = panel_id =
222 viafb_read_reg(VIACR, CR3F) & 0x0F;
223
224 switch (panel_id) {
225 case 0x0:
226 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
227 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
228 viaparinfo->lvds_setting_info->lcd_panel_id =
229 LCD_PANEL_ID0_640X480;
230 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
231 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 232 break;
233 case 0x1:
234 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
235 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
236 viaparinfo->lvds_setting_info->lcd_panel_id =
237 LCD_PANEL_ID1_800X600;
238 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
239 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 240 break;
241 case 0x2:
242 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
243 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
244 viaparinfo->lvds_setting_info->lcd_panel_id =
245 LCD_PANEL_ID2_1024X768;
246 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
247 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 248 break;
249 case 0x3:
250 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
251 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
252 viaparinfo->lvds_setting_info->lcd_panel_id =
253 LCD_PANEL_ID3_1280X768;
254 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
255 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 256 break;
257 case 0x4:
258 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
259 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
260 viaparinfo->lvds_setting_info->lcd_panel_id =
261 LCD_PANEL_ID4_1280X1024;
262 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
263 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 264 break;
265 case 0x5:
266 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
267 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
268 viaparinfo->lvds_setting_info->lcd_panel_id =
269 LCD_PANEL_ID5_1400X1050;
270 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
271 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 272 break;
273 case 0x6:
274 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
275 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
276 viaparinfo->lvds_setting_info->lcd_panel_id =
277 LCD_PANEL_ID6_1600X1200;
278 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
279 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 280 break;
281 case 0x8:
282 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
283 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
284 viaparinfo->lvds_setting_info->lcd_panel_id =
285 LCD_PANEL_IDA_800X480;
286 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
287 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 288 break;
289 case 0x9:
290 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
291 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
292 viaparinfo->lvds_setting_info->lcd_panel_id =
293 LCD_PANEL_ID2_1024X768;
294 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
295 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 296 break;
297 case 0xA:
298 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
299 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
300 viaparinfo->lvds_setting_info->lcd_panel_id =
301 LCD_PANEL_ID2_1024X768;
302 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
303 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 304 break;
305 case 0xB:
306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
307 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
308 viaparinfo->lvds_setting_info->lcd_panel_id =
309 LCD_PANEL_ID2_1024X768;
310 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
311 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 312 break;
313 case 0xC:
314 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
315 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
316 viaparinfo->lvds_setting_info->lcd_panel_id =
317 LCD_PANEL_ID3_1280X768;
318 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
319 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 320 break;
321 case 0xD:
322 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
323 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
324 viaparinfo->lvds_setting_info->lcd_panel_id =
325 LCD_PANEL_ID4_1280X1024;
326 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
327 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 328 break;
329 case 0xE:
330 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
331 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
332 viaparinfo->lvds_setting_info->lcd_panel_id =
333 LCD_PANEL_ID5_1400X1050;
334 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
335 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 336 break;
337 case 0xF:
338 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
339 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
340 viaparinfo->lvds_setting_info->lcd_panel_id =
341 LCD_PANEL_ID6_1600X1200;
342 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
343 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 344 break;
345 case 0x10:
346 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
347 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
348 viaparinfo->lvds_setting_info->lcd_panel_id =
349 LCD_PANEL_ID7_1366X768;
350 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
351 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 352 break;
353 case 0x11:
354 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
355 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
356 viaparinfo->lvds_setting_info->lcd_panel_id =
357 LCD_PANEL_ID8_1024X600;
358 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
359 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 360 break;
361 case 0x12:
362 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
363 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
364 viaparinfo->lvds_setting_info->lcd_panel_id =
365 LCD_PANEL_ID3_1280X768;
366 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
367 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 368 break;
369 case 0x13:
370 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
371 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
372 viaparinfo->lvds_setting_info->lcd_panel_id =
373 LCD_PANEL_ID9_1280X800;
374 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
375 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 376 break;
377 case 0x14:
378 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
379 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
380 viaparinfo->lvds_setting_info->lcd_panel_id =
381 LCD_PANEL_IDB_1360X768;
382 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
383 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 384 break;
385 case 0x15:
386 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
387 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
388 viaparinfo->lvds_setting_info->lcd_panel_id =
389 LCD_PANEL_ID3_1280X768;
390 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
391 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 392 break;
393 case 0x16:
394 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
395 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
396 viaparinfo->lvds_setting_info->lcd_panel_id =
397 LCD_PANEL_IDC_480X640;
398 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
399 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2 400 break;
c205d932
CB		 401 case 0x17:
402 /* OLPC XO-1.5 panel */
403 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
404 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
405 viaparinfo->lvds_setting_info->lcd_panel_id =
406 LCD_PANEL_IDD_1200X900;
407 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
408 viaparinfo->lvds_setting_info->LCDDithering = 0;
409 break;
ac6c97e2
JC		 410 default:
411 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
412 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
413 viaparinfo->lvds_setting_info->lcd_panel_id =
414 LCD_PANEL_ID1_800X600;
415 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
416 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 417 }
418}
419
420static int lvds_register_read(int index)
421{
422 u8 data;
423
c4df5489 424 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
ac6c97e2
JC		 425 viafb_i2c_readbyte((u8) viaparinfo->chip_info->
426 lvds_chip_info.lvds_chip_slave_addr,
427 (u8) index, &data);
428 return data;
429}
430
431static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
432 int panel_vres)
433{
434 int reg_value = 0;
435 int viafb_load_reg_num;
436 struct io_register *reg = NULL;
437
438 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
439
440 /* LCD Scaling Enable */
441 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
442 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
443 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
444 panel_hres, panel_vres);
445 return;
446 }
447
448 /* Check if expansion for horizontal */
449 if (set_hres != panel_hres) {
450 /* Load Horizontal Scaling Factor */
451 switch (viaparinfo->chip_info->gfx_chip_name) {
452 case UNICHROME_CLE266:
453 case UNICHROME_K400:
454 reg_value =
455 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
456 viafb_load_reg_num =
457 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
458 reg_num;
459 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
460 viafb_load_reg(reg_value,
461 viafb_load_reg_num, reg, VIACR);
462 break;
463 case UNICHROME_K800:
464 case UNICHROME_PM800:
465 case UNICHROME_CN700:
466 case UNICHROME_CX700:
467 case UNICHROME_K8M890:
468 case UNICHROME_P4M890:
469 reg_value =
470 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
471 /* Horizontal scaling enabled */
472 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
473 viafb_load_reg_num =
474 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
475 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
476 viafb_load_reg(reg_value,
477 viafb_load_reg_num, reg, VIACR);
478 break;
479 }
480
481 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
482 } else {
483 /* Horizontal scaling disabled */
484 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
485 }
486
487 /* Check if expansion for vertical */
488 if (set_vres != panel_vres) {
489 /* Load Vertical Scaling Factor */
490 switch (viaparinfo->chip_info->gfx_chip_name) {
491 case UNICHROME_CLE266:
492 case UNICHROME_K400:
493 reg_value =
494 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
495 viafb_load_reg_num =
496 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
497 reg_num;
498 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
499 viafb_load_reg(reg_value,
500 viafb_load_reg_num, reg, VIACR);
501 break;
502 case UNICHROME_K800:
503 case UNICHROME_PM800:
504 case UNICHROME_CN700:
505 case UNICHROME_CX700:
506 case UNICHROME_K8M890:
507 case UNICHROME_P4M890:
508 reg_value =
509 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
510 /* Vertical scaling enabled */
511 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
512 viafb_load_reg_num =
513 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
514 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
515 viafb_load_reg(reg_value,
516 viafb_load_reg_num, reg, VIACR);
517 break;
518 }
519
520 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
521 } else {
522 /* Vertical scaling disabled */
523 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
524 }
525}
526
ac6c97e2
JC		 527static void via_pitch_alignment_patch_lcd(
528 struct lvds_setting_information *plvds_setting_info,
529 struct lvds_chip_information
530 *plvds_chip_info)
531{
532 unsigned char cr13, cr35, cr65, cr66, cr67;
533 unsigned long dwScreenPitch = 0;
534 unsigned long dwPitch;
535
536 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
537 if (dwPitch & 0x1F) {
538 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
539 if (plvds_setting_info->iga_path == IGA2) {
540 if (plvds_setting_info->bpp > 8) {
541 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
542 viafb_write_reg(CR66, VIACR, cr66);
543 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
544 cr67 |=
545 (unsigned
546 char)((dwScreenPitch & 0x300) >> 8);
547 viafb_write_reg(CR67, VIACR, cr67);
548 }
549
550 /* Fetch Count */
551 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
552 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
553 viafb_write_reg(CR67, VIACR, cr67);
554 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
555 cr65 += 2;
556 viafb_write_reg(CR65, VIACR, cr65);
557 } else {
558 if (plvds_setting_info->bpp > 8) {
559 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
560 viafb_write_reg(CR13, VIACR, cr13);
561 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
562 cr35 |=
563 (unsigned
564 char)((dwScreenPitch & 0x700) >> 3);
565 viafb_write_reg(CR35, VIACR, cr35);
566 }
567 }
568 }
569}
570static void lcd_patch_skew_dvp0(struct lvds_setting_information
571 *plvds_setting_info,
572 struct lvds_chip_information *plvds_chip_info)
573{
574 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
575 switch (viaparinfo->chip_info->gfx_chip_name) {
576 case UNICHROME_P4M900:
577 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
578 plvds_chip_info);
579 break;
580 case UNICHROME_P4M890:
581 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
582 plvds_chip_info);
583 break;
584 }
585 }
586}
587static void lcd_patch_skew_dvp1(struct lvds_setting_information
588 *plvds_setting_info,
589 struct lvds_chip_information *plvds_chip_info)
590{
591 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
592 switch (viaparinfo->chip_info->gfx_chip_name) {
593 case UNICHROME_CX700:
594 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
595 plvds_chip_info);
596 break;
597 }
598 }
599}
600static void lcd_patch_skew(struct lvds_setting_information
601 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
602{
603 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
604 switch (plvds_chip_info->output_interface) {
605 case INTERFACE_DVP0:
606 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
607 break;
608 case INTERFACE_DVP1:
609 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
610 break;
611 case INTERFACE_DFP_LOW:
612 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
613 viafb_write_reg_mask(CR99, VIACR, 0x08,
614 BIT0 + BIT1 + BIT2 + BIT3);
615 }
616 break;
617 }
618}
619
620/* LCD Set Mode */
621void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
622 struct lvds_setting_information *plvds_setting_info,
623 struct lvds_chip_information *plvds_chip_info)
624{
ac6c97e2
JC		 625 int set_iga = plvds_setting_info->iga_path;
626 int mode_bpp = plvds_setting_info->bpp;
dd73d686
FTS		 627 int set_hres = plvds_setting_info->h_active;
628 int set_vres = plvds_setting_info->v_active;
629 int panel_hres = plvds_setting_info->lcd_panel_hres;
630 int panel_vres = plvds_setting_info->lcd_panel_vres;
ac6c97e2 631 u32 pll_D_N;
ac6c97e2
JC		 632 struct display_timing mode_crt_reg, panel_crt_reg;
633 struct crt_mode_table *panel_crt_table = NULL;
dd73d686
FTS		 634 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
635 panel_vres);
ac6c97e2
JC		 636
637 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
638 /* Get mode table */
639 mode_crt_reg = mode_crt_table->crtc;
640 /* Get panel table Pointer */
ac6c97e2
JC		 641 panel_crt_table = vmode_tbl->crtc;
642 panel_crt_reg = panel_crt_table->crtc;
643 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
ac6c97e2
JC		 644 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
645 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
646 plvds_setting_info->vclk = panel_crt_table->clk;
647 if (set_iga == IGA1) {
648 /* IGA1 doesn't have LCD scaling, so set it as centering. */
649 viafb_load_crtc_timing(lcd_centering_timging
650 (mode_crt_reg, panel_crt_reg), IGA1);
651 } else {
652 /* Expansion */
653 if ((plvds_setting_info->display_method ==
654 LCD_EXPANDSION) & ((set_hres != panel_hres)
655 || (set_vres != panel_vres))) {
656 /* expansion timing IGA2 loaded panel set timing*/
657 viafb_load_crtc_timing(panel_crt_reg, IGA2);
658 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
659 load_lcd_scaling(set_hres, set_vres, panel_hres,
660 panel_vres);
661 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
662 } else { /* Centering */
663 /* centering timing IGA2 always loaded panel
664 and mode releative timing */
665 viafb_load_crtc_timing(lcd_centering_timging
666 (mode_crt_reg, panel_crt_reg), IGA2);
667 viafb_write_reg_mask(CR79, VIACR, 0x00,
668 BIT0 + BIT1 + BIT2);
669 /* LCD scaling disabled */
670 }
671 }
672
4bbac05f
FTS		 673 /* Fetch count for IGA2 only */
674 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
ac6c97e2 675
4bbac05f
FTS		 676 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
677 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
678 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
ac6c97e2
JC		 679
680 fill_lcd_format();
681
682 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
683 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
684 viafb_set_vclock(pll_D_N, set_iga);
685
686 viafb_set_output_path(DEVICE_LCD, set_iga,
687 plvds_chip_info->output_interface);
688 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
689
690 /* If K8M800, enable LCD Prefetch Mode. */
691 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
692 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
693 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
694
ac6c97e2
JC		 695 /* Patch for non 32bit alignment mode */
696 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
697}
698
699static void integrated_lvds_disable(struct lvds_setting_information
700 *plvds_setting_info,
701 struct lvds_chip_information *plvds_chip_info)
702{
703 bool turn_off_first_powersequence = false;
704 bool turn_off_second_powersequence = false;
705 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
706 turn_off_first_powersequence = true;
707 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
708 turn_off_first_powersequence = true;
709 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
710 turn_off_second_powersequence = true;
711 if (turn_off_second_powersequence) {
712 /* Use second power sequence control: */
713
714 /* Turn off power sequence. */
715 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
716
717 /* Turn off back light. */
718 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
719 }
720 if (turn_off_first_powersequence) {
721 /* Use first power sequence control: */
722
723 /* Turn off power sequence. */
724 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
725
726 /* Turn off back light. */
727 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
728 }
729
730 /* Turn DFP High/Low Pad off. */
731 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
732
733 /* Power off LVDS channel. */
734 switch (plvds_chip_info->output_interface) {
735 case INTERFACE_LVDS0:
736 {
737 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
738 break;
739 }
740
741 case INTERFACE_LVDS1:
742 {
743 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
744 break;
745 }
746
747 case INTERFACE_LVDS0LVDS1:
748 {
749 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
750 break;
751 }
752 }
753}
754
755static void integrated_lvds_enable(struct lvds_setting_information
756 *plvds_setting_info,
757 struct lvds_chip_information *plvds_chip_info)
758{
ac6c97e2
JC		 759 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
760 plvds_chip_info->output_interface);
761 if (plvds_setting_info->lcd_mode == LCD_SPWG)
762 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
e6bf0d2c 763 else
ac6c97e2 764 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
ac6c97e2 765
e6bf0d2c
HW		 766 switch (plvds_chip_info->output_interface) {
767 case INTERFACE_LVDS0LVDS1:
768 case INTERFACE_LVDS0:
ac6c97e2 769 /* Use first power sequence control: */
ac6c97e2
JC		 770 /* Use hardware control power sequence. */
771 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
ac6c97e2
JC		 772 /* Turn on back light. */
773 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
ac6c97e2
JC		 774 /* Turn on hardware power sequence. */
775 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
e6bf0d2c
HW		 776 break;
777 case INTERFACE_LVDS1:
778 /* Use second power sequence control: */
779 /* Use hardware control power sequence. */
780 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
781 /* Turn on back light. */
782 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
783 /* Turn on hardware power sequence. */
784 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
785 break;
ac6c97e2
JC		 786 }
787
788 /* Turn DFP High/Low pad on. */
789 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
790
791 /* Power on LVDS channel. */
792 switch (plvds_chip_info->output_interface) {
793 case INTERFACE_LVDS0:
794 {
795 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
796 break;
797 }
798
799 case INTERFACE_LVDS1:
800 {
801 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
802 break;
803 }
804
805 case INTERFACE_LVDS0LVDS1:
806 {
807 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
808 break;
809 }
810 }
811}
812
813void viafb_lcd_disable(void)
814{
815
816 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
817 lcd_powersequence_off();
818 /* DI1 pad off */
819 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
820 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
821 if (viafb_LCD2_ON
822 && (INTEGRATED_LVDS ==
823 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
824 integrated_lvds_disable(viaparinfo->lvds_setting_info,
825 &viaparinfo->chip_info->lvds_chip_info2);
826 if (INTEGRATED_LVDS ==
827 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
828 integrated_lvds_disable(viaparinfo->lvds_setting_info,
829 &viaparinfo->chip_info->lvds_chip_info);
830 if (VT1636_LVDS == viaparinfo->chip_info->
831 lvds_chip_info.lvds_chip_name)
832 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
833 &viaparinfo->chip_info->lvds_chip_info);
834 } else if (VT1636_LVDS ==
835 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
836 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
837 &viaparinfo->chip_info->lvds_chip_info);
838 } else {
839 /* DFP-HL pad off */
840 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
841 /* Backlight off */
842 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
843 /* 24 bit DI data paht off */
844 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
845 /* Simultaneout disabled */
846 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
847 }
848
849 /* Disable expansion bit */
850 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
851 /* CRT path set to IGA1 */
852 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
853 /* Simultaneout disabled */
854 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
855 /* IGA2 path disabled */
856 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
857
858}
859
860void viafb_lcd_enable(void)
861{
862 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
863 /* DI1 pad on */
864 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
865 lcd_powersequence_on();
866 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
867 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
868 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
869 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
870 &viaparinfo->chip_info->lvds_chip_info2);
871 if (INTEGRATED_LVDS ==
872 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
873 integrated_lvds_enable(viaparinfo->lvds_setting_info,
874 &viaparinfo->chip_info->lvds_chip_info);
875 if (VT1636_LVDS == viaparinfo->chip_info->
876 lvds_chip_info.lvds_chip_name)
877 viafb_enable_lvds_vt1636(viaparinfo->
878 lvds_setting_info, &viaparinfo->chip_info->
879 lvds_chip_info);
880 } else if (VT1636_LVDS ==
881 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
882 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
883 &viaparinfo->chip_info->lvds_chip_info);
884 } else {
885 /* DFP-HL pad on */
886 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
887 /* Backlight on */
888 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
889 /* 24 bit DI data paht on */
890 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
891
892 /* Set data source selection bit by iga path */
893 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
894 /* DFP-H set to IGA1 */
895 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
896 /* DFP-L set to IGA1 */
897 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
898 } else {
899 /* DFP-H set to IGA2 */
900 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
901 /* DFP-L set to IGA2 */
902 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
903 }
904 /* LCD enabled */
905 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
906 }
907
4bbac05f 908 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
ac6c97e2
JC		 909 /* CRT path set to IGA2 */
910 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
911 /* IGA2 path disabled */
912 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
913 /* IGA2 path enabled */
914 } else { /* IGA2 */
915 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
916 }
917
918}
919
920static void lcd_powersequence_off(void)
921{
922 int i, mask, data;
923
924 /* Software control power sequence */
925 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
926
927 for (i = 0; i < 3; i++) {
928 mask = PowerSequenceOff[0][i];
929 data = PowerSequenceOff[1][i] & mask;
930 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
931 udelay(PowerSequenceOff[2][i]);
932 }
933
934 /* Disable LCD */
935 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
936}
937
938static void lcd_powersequence_on(void)
939{
940 int i, mask, data;
941
942 /* Software control power sequence */
943 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
944
945 /* Enable LCD */
946 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
947
948 for (i = 0; i < 3; i++) {
949 mask = PowerSequenceOn[0][i];
950 data = PowerSequenceOn[1][i] & mask;
951 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
952 udelay(PowerSequenceOn[2][i]);
953 }
954
955 udelay(1);
956}
957
958static void fill_lcd_format(void)
959{
960 u8 bdithering = 0, bdual = 0;
961
962 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
963 bdual = BIT4;
964 if (viaparinfo->lvds_setting_info->LCDDithering)
965 bdithering = BIT0;
966 /* Dual & Dithering */
967 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
968}
969
970static void check_diport_of_integrated_lvds(
971 struct lvds_chip_information *plvds_chip_info,
972 struct lvds_setting_information
973 *plvds_setting_info)
974{
975 /* Determine LCD DI Port by hardware layout. */
976 switch (viafb_display_hardware_layout) {
977 case HW_LAYOUT_LCD_ONLY:
978 {
979 if (plvds_setting_info->device_lcd_dualedge) {
980 plvds_chip_info->output_interface =
981 INTERFACE_LVDS0LVDS1;
982 } else {
983 plvds_chip_info->output_interface =
984 INTERFACE_LVDS0;
985 }
986
987 break;
988 }
989
990 case HW_LAYOUT_DVI_ONLY:
991 {
992 plvds_chip_info->output_interface = INTERFACE_NONE;
993 break;
994 }
995
996 case HW_LAYOUT_LCD1_LCD2:
997 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
998 {
999 plvds_chip_info->output_interface =
1000 INTERFACE_LVDS0LVDS1;
1001 break;
1002 }
1003
1004 case HW_LAYOUT_LCD_DVI:
1005 {
1006 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1007 break;
1008 }
1009
1010 default:
1011 {
1012 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1013 break;
1014 }
1015 }
1016
1017 DEBUG_MSG(KERN_INFO
1018 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1019 viafb_display_hardware_layout,
1020 plvds_chip_info->output_interface);
1021}
1022
1023void viafb_init_lvds_output_interface(struct lvds_chip_information
1024 *plvds_chip_info,
1025 struct lvds_setting_information
1026 *plvds_setting_info)
1027{
1028 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1029 /*Do nothing, lcd port is specified by module parameter */
1030 return;
1031 }
1032
1033 switch (plvds_chip_info->lvds_chip_name) {
1034
1035 case VT1636_LVDS:
1036 switch (viaparinfo->chip_info->gfx_chip_name) {
1037 case UNICHROME_CX700:
1038 plvds_chip_info->output_interface = INTERFACE_DVP1;
1039 break;
1040 case UNICHROME_CN700:
1041 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1042 break;
1043 default:
1044 plvds_chip_info->output_interface = INTERFACE_DVP0;
1045 break;
1046 }
1047 break;
1048
1049 case INTEGRATED_LVDS:
1050 check_diport_of_integrated_lvds(plvds_chip_info,
1051 plvds_setting_info);
1052 break;
1053
1054 default:
1055 switch (viaparinfo->chip_info->gfx_chip_name) {
1056 case UNICHROME_K8M890:
1057 case UNICHROME_P4M900:
1058 case UNICHROME_P4M890:
1059 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1060 break;
1061 default:
1062 plvds_chip_info->output_interface = INTERFACE_DFP;
1063 break;
1064 }
1065 break;
1066 }
1067}
1068
1069static struct display_timing lcd_centering_timging(struct display_timing
1070 mode_crt_reg,
1071 struct display_timing panel_crt_reg)
1072{
1073 struct display_timing crt_reg;
1074
1075 crt_reg.hor_total = panel_crt_reg.hor_total;
1076 crt_reg.hor_addr = mode_crt_reg.hor_addr;
1077 crt_reg.hor_blank_start =
1078 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1079 crt_reg.hor_addr;
1080 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1081 crt_reg.hor_sync_start =
1082 (panel_crt_reg.hor_sync_start -
1083 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1084 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1085
1086 crt_reg.ver_total = panel_crt_reg.ver_total;
1087 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1088 crt_reg.ver_blank_start =
1089 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1090 crt_reg.ver_addr;
1091 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1092 crt_reg.ver_sync_start =
1093 (panel_crt_reg.ver_sync_start -
1094 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1095 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1096
1097 return crt_reg;
1098}
1099
ac6c97e2
JC		 1100bool viafb_lcd_get_mobile_state(bool *mobile)
1101{
1102 unsigned char *romptr, *tableptr;
1103 u8 core_base;
1104 unsigned char *biosptr;
1105 /* Rom address */
1106 u32 romaddr = 0x000C0000;
1107 u16 start_pattern = 0;
1108
1109 biosptr = ioremap(romaddr, 0x10000);
1110
1111 memcpy(&start_pattern, biosptr, 2);
1112 /* Compare pattern */
1113 if (start_pattern == 0xAA55) {
1114 /* Get the start of Table */
1115 /* 0x1B means BIOS offset position */
1116 romptr = biosptr + 0x1B;
1117 tableptr = biosptr + *((u16 *) romptr);
1118
1119 /* Get the start of biosver structure */
1120 /* 18 means BIOS version position. */
1121 romptr = tableptr + 18;
1122 romptr = biosptr + *((u16 *) romptr);
1123
1124 /* The offset should be 44, but the
1125 actual image is less three char. */
1126 /* pRom += 44; */
1127 romptr += 41;
1128
1129 core_base = *romptr++;
1130
1131 if (core_base & 0x8)
1132 *mobile = false;
1133 else
1134 *mobile = true;
1135 /* release memory */
1136 iounmap(biosptr);
1137
1138 return true;
1139 } else {
1140 iounmap(biosptr);
1141 return false;
1142 }
1143}
1144
1145static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1146 int set_vres, int panel_hres, int panel_vres)
1147{
1148 int h_scaling_factor;
1149 int v_scaling_factor;
1150 u8 cra2 = 0;
1151 u8 cr77 = 0;
1152 u8 cr78 = 0;
1153 u8 cr79 = 0;
1154 u8 cr9f = 0;
1155 /* Check if expansion for horizontal */
1156 if (set_hres < panel_hres) {
1157 /* Load Horizontal Scaling Factor */
1158
1159 /* For VIA_K8M800 or later chipsets. */
1160 h_scaling_factor =
1161 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1162 /* HSCaleFactor[1:0] at CR9F[1:0] */
1163 cr9f = h_scaling_factor & 0x0003;
1164 /* HSCaleFactor[9:2] at CR77[7:0] */
1165 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1166 /* HSCaleFactor[11:10] at CR79[5:4] */
1167 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1168 cr79 <<= 4;
1169
1170 /* Horizontal scaling enabled */
1171 cra2 = 0xC0;
1172
1173 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1174 h_scaling_factor);
1175 } else {
1176 /* Horizontal scaling disabled */
1177 cra2 = 0x00;
1178 }
1179
1180 /* Check if expansion for vertical */
1181 if (set_vres < panel_vres) {
1182 /* Load Vertical Scaling Factor */
1183
1184 /* For VIA_K8M800 or later chipsets. */
1185 v_scaling_factor =
1186 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1187
1188 /* Vertical scaling enabled */
1189 cra2 |= 0x08;
1190 /* VSCaleFactor[0] at CR79[3] */
1191 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1192 /* VSCaleFactor[8:1] at CR78[7:0] */
1193 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1194 /* VSCaleFactor[10:9] at CR79[7:6] */
1195 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1196
1197 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1198 v_scaling_factor);
1199 } else {
1200 /* Vertical scaling disabled */
1201 cra2 |= 0x00;
1202 }
1203
1204 viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1205 viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1206 viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1207 viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1208 viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1209}
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