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viafb: remove 640x480-60 CRT special case
[mirror_ubuntu-zesty-kernel.git] / drivers / video / via / viamode.c
CommitLineData
9f291634
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
ec66841e 22#include <linux/via-core.h>
9f291634 23#include "global.h"
9f291634
JC		 24
25struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
26{VIASR, SR15, 0x02, 0x02},
27{VIASR, SR16, 0xBF, 0x08},
28{VIASR, SR17, 0xFF, 0x1F},
29{VIASR, SR18, 0xFF, 0x4E},
30{VIASR, SR1A, 0xFB, 0x08},
31{VIASR, SR1E, 0x0F, 0x01},
32{VIASR, SR2A, 0xFF, 0x00},
9f291634
JC		 33{VIACR, CR32, 0xFF, 0x00},
34{VIACR, CR33, 0xFF, 0x00},
9f291634
JC		 35{VIACR, CR35, 0xFF, 0x00},
36{VIACR, CR36, 0x08, 0x00},
9f291634
JC		 37{VIACR, CR69, 0xFF, 0x00},
38{VIACR, CR6A, 0xFF, 0x40},
39{VIACR, CR6B, 0xFF, 0x00},
9f291634
JC		 40{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
41{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
42{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
43{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
44{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
45{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
46{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
47{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
48{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
49{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
50{VIACR, CR96, 0xFF, 0x00},
51{VIACR, CR97, 0xFF, 0x00},
52{VIACR, CR99, 0xFF, 0x00},
53{VIACR, CR9B, 0xFF, 0x00}
54};
55
56/* Video Mode Table for VT3314 chipset*/
57/* Common Setting for Video Mode */
58struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
59{VIASR, SR15, 0x02, 0x02},
60{VIASR, SR16, 0xBF, 0x08},
61{VIASR, SR17, 0xFF, 0x1F},
62{VIASR, SR18, 0xFF, 0x4E},
63{VIASR, SR1A, 0xFB, 0x82},
64{VIASR, SR1B, 0xFF, 0xF0},
65{VIASR, SR1F, 0xFF, 0x00},
66{VIASR, SR1E, 0xFF, 0x01},
67{VIASR, SR22, 0xFF, 0x1F},
68{VIASR, SR2A, 0x0F, 0x00},
69{VIASR, SR2E, 0xFF, 0xFF},
70{VIASR, SR3F, 0xFF, 0xFF},
71{VIASR, SR40, 0xF7, 0x00},
72{VIASR, CR30, 0xFF, 0x04},
73{VIACR, CR32, 0xFF, 0x00},
74{VIACR, CR33, 0x7F, 0x00},
9f291634
JC		 75{VIACR, CR35, 0xFF, 0x00},
76{VIACR, CR36, 0xFF, 0x31},
77{VIACR, CR41, 0xFF, 0x80},
78{VIACR, CR42, 0xFF, 0x00},
79{VIACR, CR55, 0x80, 0x00},
80{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
9f291634
JC		 81{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
82{VIACR, CR69, 0xFF, 0x00},
83{VIACR, CR6A, 0xFD, 0x40},
84{VIACR, CR6B, 0xFF, 0x00},
9f291634
JC		 85{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
86{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
87{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
88{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
9f291634
JC		 89{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
90{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
91{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
92{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
93{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
94{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
95{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
96{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
97{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
98{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
99{VIACR, CR96, 0xFF, 0x00},
100{VIACR, CR97, 0xFF, 0x00},
101{VIACR, CR99, 0xFF, 0x00},
102{VIACR, CR9B, 0xFF, 0x00},
103{VIACR, CR9D, 0xFF, 0x80},
104{VIACR, CR9E, 0xFF, 0x80}
105};
106
107struct io_reg KM400_ModeXregs[] = {
108 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
109 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
110 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
111 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
112 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
113 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
114 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
115 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
116 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
117 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
118 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
119 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
120 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
121 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
9f291634
JC		 122 {VIACR, CR33, 0xFF, 0x00},
123 {VIACR, CR55, 0x80, 0x00},
124 {VIACR, CR5D, 0x80, 0x00},
125 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
9f291634
JC		 126 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
127 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
9f291634
JC		 128 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
129 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
130 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
131 {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
132 {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
133 {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
134 {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
135 {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
136 {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
137 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
138 {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */
139 {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */
140 {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
141 {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/
142};
143
144/* For VT3324: Common Setting for Video Mode */
145struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
146{VIASR, SR15, 0x02, 0x02},
147{VIASR, SR16, 0xBF, 0x08},
148{VIASR, SR17, 0xFF, 0x1F},
149{VIASR, SR18, 0xFF, 0x4E},
150{VIASR, SR1A, 0xFB, 0x08},
9f291634
JC		 151{VIASR, SR1B, 0xFF, 0xF0},
152{VIASR, SR1E, 0xFF, 0x01},
153{VIASR, SR2A, 0xFF, 0x00},
4d9fd0b7 154{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
9f291634
JC		 155{VIACR, CR32, 0xFF, 0x00},
156{VIACR, CR33, 0xFF, 0x00},
9f291634
JC		 157{VIACR, CR35, 0xFF, 0x00},
158{VIACR, CR36, 0x08, 0x00},
159{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
9f291634
JC		 160{VIACR, CR69, 0xFF, 0x00},
161{VIACR, CR6A, 0xFF, 0x40},
162{VIACR, CR6B, 0xFF, 0x00},
9f291634
JC		 163{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
164{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
165{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
166{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
167{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
168{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
169{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
170{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
171{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
172{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
173{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
174{VIACR, CR96, 0xFF, 0x00},
175{VIACR, CR97, 0xFF, 0x00},
176{VIACR, CR99, 0xFF, 0x00},
8594ac33 177{VIACR, CR9B, 0xFF, 0x00}
9f291634
JC		 178};
179
0306ab11
HW		 180struct io_reg VX855_ModeXregs[] = {
181{VIASR, SR10, 0xFF, 0x01},
182{VIASR, SR15, 0x02, 0x02},
183{VIASR, SR16, 0xBF, 0x08},
184{VIASR, SR17, 0xFF, 0x1F},
185{VIASR, SR18, 0xFF, 0x4E},
186{VIASR, SR1A, 0xFB, 0x08},
187{VIASR, SR1B, 0xFF, 0xF0},
188{VIASR, SR1E, 0x07, 0x01},
189{VIASR, SR2A, 0xF0, 0x00},
190{VIASR, SR58, 0xFF, 0x00},
191{VIASR, SR59, 0xFF, 0x00},
4d9fd0b7 192{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
0306ab11
HW		 193{VIACR, CR32, 0xFF, 0x00},
194{VIACR, CR33, 0x7F, 0x00},
195{VIACR, CR35, 0xFF, 0x00},
196{VIACR, CR36, 0x08, 0x00},
197{VIACR, CR69, 0xFF, 0x00},
198{VIACR, CR6A, 0xFD, 0x60},
199{VIACR, CR6B, 0xFF, 0x00},
0306ab11
HW		 200{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
201{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
202{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
203{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
204{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
205{VIACR, CR96, 0xFF, 0x00},
206{VIACR, CR97, 0xFF, 0x00},
207{VIACR, CR99, 0xFF, 0x00},
208{VIACR, CR9B, 0xFF, 0x00},
209{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
210};
211
9f291634
JC		 212/* Video Mode Table */
213/* Common Setting for Video Mode */
214struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
215{VIASR, SR2A, 0x0F, 0x00},
216{VIASR, SR15, 0x02, 0x02},
217{VIASR, SR16, 0xBF, 0x08},
218{VIASR, SR17, 0xFF, 0x1F},
219{VIASR, SR18, 0xFF, 0x4E},
220{VIASR, SR1A, 0xFB, 0x08},
221
222{VIACR, CR32, 0xFF, 0x00},
9f291634
JC		 223{VIACR, CR35, 0xFF, 0x00},
224{VIACR, CR36, 0x08, 0x00},
225{VIACR, CR6A, 0xFF, 0x80},
226{VIACR, CR6A, 0xFF, 0xC0},
227
228{VIACR, CR55, 0x80, 0x00},
229{VIACR, CR5D, 0x80, 0x00},
230
231{VIAGR, GR20, 0xFF, 0x00},
232{VIAGR, GR21, 0xFF, 0x00},
233{VIAGR, GR22, 0xFF, 0x00},
9f291634
JC		 234
235};
236
237/* Mode:1024X768 */
238struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
239{VIASR, 0x18, 0xFF, 0x4C}
240};
241
242struct patch_table res_patch_table[] = {
dd73d686 243 {ARRAY_SIZE(PM1024x768), PM1024x768}
9f291634
JC		 244};
245
246/* struct VPITTable {
247 unsigned char Misc;
248 unsigned char SR[StdSR];
249 unsigned char CR[StdCR];
250 unsigned char GR[StdGR];
251 unsigned char AR[StdAR];
252 };*/
253
254struct VPITTable VPIT = {
255 /* Msic */
256 0xC7,
257 /* Sequencer */
258 {0x01, 0x0F, 0x00, 0x0E},
259 /* Graphic Controller */
260 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
261 /* Attribute Controller */
262 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
263 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
264 0x01, 0x00, 0x0F, 0x00}
265};
266
267/********************/
268/* Mode Table */
269/********************/
270
271/* 480x640 */
23e5abd5 272static struct crt_mode_table CRTM480x640[] = {
fd3cc698 273 /* r_rate, hsp, vsp */
9f291634 274 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 275 {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
9f291634
JC		 276 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
277};
278
279/* 640x480*/
23e5abd5 280static struct crt_mode_table CRTM640x480[] = {
fd3cc698 281 /*r_rate,hsp,vsp */
9f291634 282 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 283 {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
04922622 284 {800, 640, 640, 160, 656, 96, 525, 480, 480, 45, 490, 2} },
fd3cc698 285 {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
9f291634 286 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
fd3cc698 287 {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
9f291634 288 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
fd3cc698 289 {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
9f291634 290 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
fd3cc698
FTS		 291 {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
292 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
9f291634
JC		 293};
294
295/*720x480 (GTF)*/
23e5abd5 296static struct crt_mode_table CRTM720x480[] = {
fd3cc698 297 /*r_rate,hsp,vsp */
9f291634 298 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 299 {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
9f291634
JC		 300 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
301
302};
303
304/*720x576 (GTF)*/
23e5abd5 305static struct crt_mode_table CRTM720x576[] = {
fd3cc698 306 /*r_rate,hsp,vsp */
9f291634 307 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 308 {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
9f291634
JC		 309 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
310};
311
312/* 800x480 (CVT) */
23e5abd5 313static struct crt_mode_table CRTM800x480[] = {
fd3cc698 314 /* r_rate, hsp, vsp */
9f291634 315 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 316 {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
9f291634
JC		 317 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
318};
319
320/* 800x600*/
23e5abd5 321static struct crt_mode_table CRTM800x600[] = {
fd3cc698 322 /*r_rate,hsp,vsp */
9f291634 323 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 324 {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
9f291634 325 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
fd3cc698 326 {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
9f291634 327 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
fd3cc698 328 {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
9f291634 329 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
fd3cc698 330 {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
9f291634 331 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
fd3cc698
FTS		 332 {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
333 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
9f291634
JC		 334};
335
336/* 848x480 (CVT) */
23e5abd5 337static struct crt_mode_table CRTM848x480[] = {
fd3cc698 338 /* r_rate, hsp, vsp */
9f291634 339 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 340 {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
9f291634
JC		 341 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
342};
343
344/*856x480 (GTF) convert to 852x480*/
23e5abd5 345static struct crt_mode_table CRTM852x480[] = {
fd3cc698 346 /*r_rate,hsp,vsp */
9f291634 347 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 348 {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
9f291634
JC		 349 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
350};
351
352/*1024x512 (GTF)*/
23e5abd5 353static struct crt_mode_table CRTM1024x512[] = {
fd3cc698 354 /*r_rate,hsp,vsp */
9f291634 355 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 356 {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
9f291634
JC		 357 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
358
359};
360
361/* 1024x600*/
23e5abd5 362static struct crt_mode_table CRTM1024x600[] = {
fd3cc698 363 /*r_rate,hsp,vsp */
9f291634 364 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 365 {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
9f291634
JC		 366 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
367};
368
369/* 1024x768*/
23e5abd5 370static struct crt_mode_table CRTM1024x768[] = {
fd3cc698 371 /*r_rate,hsp,vsp */
9f291634 372 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 373 {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
9f291634 374 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
fd3cc698 375 {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
9f291634 376 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
fd3cc698 377 {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
9f291634 378 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
fd3cc698 379 {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
9f291634
JC		 380 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
381};
382
383/* 1152x864*/
23e5abd5 384static struct crt_mode_table CRTM1152x864[] = {
fd3cc698 385 /*r_rate,hsp,vsp */
9f291634 386 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 387 {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
9f291634
JC		 388 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
389
390};
391
392/* 1280x720 (HDMI 720P)*/
23e5abd5 393static struct crt_mode_table CRTM1280x720[] = {
fd3cc698 394 /*r_rate,hsp,vsp */
9f291634 395 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 396 {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
9f291634 397 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
fd3cc698 398 {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
9f291634
JC		 399 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
400};
401
402/*1280x768 (GTF)*/
23e5abd5 403static struct crt_mode_table CRTM1280x768[] = {
fd3cc698 404 /*r_rate,hsp,vsp */
9f291634 405 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 406 {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
9f291634 407 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
fd3cc698 408 {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
9f291634
JC		 409 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
410};
411
412/* 1280x800 (CVT) */
23e5abd5 413static struct crt_mode_table CRTM1280x800[] = {
fd3cc698 414 /* r_rate, hsp, vsp */
9f291634 415 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 416 {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
9f291634
JC		 417 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
418};
419
420/*1280x960*/
23e5abd5 421static struct crt_mode_table CRTM1280x960[] = {
fd3cc698 422 /*r_rate,hsp,vsp */
9f291634 423 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 424 {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
9f291634
JC		 425 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
426};
427
428/* 1280x1024*/
23e5abd5 429static struct crt_mode_table CRTM1280x1024[] = {
fd3cc698 430 /*r_rate,hsp,vsp */
9f291634 431 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 432 {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
9f291634
JC		 433 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
434 3} },
fd3cc698 435 {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
9f291634
JC		 436 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
437 3} },
fd3cc698 438 {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
9f291634
JC		 439 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
440};
441
442/* 1368x768 (GTF) */
23e5abd5 443static struct crt_mode_table CRTM1368x768[] = {
fd3cc698 444 /* r_rate, hsp, vsp */
9f291634 445 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 446 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
9f291634
JC		 447 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
448};
449
450/*1440x1050 (GTF)*/
23e5abd5 451static struct crt_mode_table CRTM1440x1050[] = {
fd3cc698 452 /*r_rate,hsp,vsp */
9f291634 453 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 454 {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
9f291634
JC		 455 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
456};
457
458/* 1600x1200*/
23e5abd5 459static struct crt_mode_table CRTM1600x1200[] = {
fd3cc698 460 /*r_rate,hsp,vsp */
9f291634 461 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 462 {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
9f291634
JC		 463 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
464 3} },
fd3cc698 465 {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
9f291634
JC		 466 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
467
468};
469
470/* 1680x1050 (CVT) */
23e5abd5 471static struct crt_mode_table CRTM1680x1050[] = {
fd3cc698 472 /* r_rate, hsp, vsp */
9f291634 473 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 474 {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
9f291634
JC		 475 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
476 6} },
fd3cc698 477 {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
9f291634
JC		 478 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
479};
480
481/* 1680x1050 (CVT Reduce Blanking) */
23e5abd5 482static struct crt_mode_table CRTM1680x1050_RB[] = {
fd3cc698 483 /* r_rate, hsp, vsp */
9f291634 484 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 485 {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
9f291634
JC		 486 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
487};
488
489/* 1920x1080 (CVT)*/
23e5abd5 490static struct crt_mode_table CRTM1920x1080[] = {
fd3cc698 491 /*r_rate,hsp,vsp */
9f291634 492 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 493 {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
9f291634
JC		 494 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
495};
496
497/* 1920x1080 (CVT with Reduce Blanking) */
23e5abd5 498static struct crt_mode_table CRTM1920x1080_RB[] = {
fd3cc698 499 /* r_rate, hsp, vsp */
9f291634 500 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 501 {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
9f291634
JC		 502 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
503};
504
505/* 1920x1440*/
23e5abd5 506static struct crt_mode_table CRTM1920x1440[] = {
fd3cc698 507 /*r_rate,hsp,vsp */
9f291634 508 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 509 {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
9f291634
JC		 510 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
511 3} },
fd3cc698 512 {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
9f291634
JC		 513 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
514};
515
516/* 1400x1050 (CVT) */
23e5abd5 517static struct crt_mode_table CRTM1400x1050[] = {
fd3cc698 518 /* r_rate, hsp, vsp */
9f291634 519 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 520 {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
9f291634
JC		 521 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
522 4} },
fd3cc698 523 {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
9f291634
JC		 524 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
525};
526
527/* 1400x1050 (CVT Reduce Blanking) */
23e5abd5 528static struct crt_mode_table CRTM1400x1050_RB[] = {
fd3cc698 529 /* r_rate, hsp, vsp */
9f291634 530 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 531 {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
9f291634
JC		 532 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
533};
534
535/* 960x600 (CVT) */
23e5abd5 536static struct crt_mode_table CRTM960x600[] = {
fd3cc698 537 /* r_rate, hsp, vsp */
9f291634 538 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 539 {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
9f291634
JC		 540 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
541};
542
543/* 1000x600 (GTF) */
23e5abd5 544static struct crt_mode_table CRTM1000x600[] = {
fd3cc698 545 /* r_rate, hsp, vsp */
9f291634 546 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 547 {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
9f291634
JC		 548 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
549};
550
551/* 1024x576 (GTF) */
23e5abd5 552static struct crt_mode_table CRTM1024x576[] = {
fd3cc698 553 /* r_rate, hsp, vsp */
9f291634 554 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 555 {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
9f291634
JC		 556 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
557};
558
559/* 1088x612 (CVT) */
23e5abd5 560static struct crt_mode_table CRTM1088x612[] = {
fd3cc698 561 /* r_rate, hsp, vsp */
9f291634 562 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 563 {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
9f291634
JC		 564 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
565};
566
567/* 1152x720 (CVT) */
23e5abd5 568static struct crt_mode_table CRTM1152x720[] = {
fd3cc698 569 /* r_rate, hsp, vsp */
9f291634 570 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 571 {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
9f291634
JC		 572 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
573};
574
575/* 1200x720 (GTF) */
23e5abd5 576static struct crt_mode_table CRTM1200x720[] = {
fd3cc698 577 /* r_rate, hsp, vsp */
9f291634 578 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 579 {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
9f291634
JC		 580 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
581};
582
c205d932 583/* 1200x900 (DCON) */
23e5abd5 584static struct crt_mode_table DCON1200x900[] = {
fd3cc698 585 /* r_rate, hsp, vsp */
c5a4e6d7 586 {REFRESH_49, M1200X900_R60_HSP, M1200X900_R60_VSP,
c205d932
CB		 587 /* The correct htotal is 1240, but this doesn't raster on VX855. */
588 /* Via suggested changing to a multiple of 16, hence 1264. */
589 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
590 {1264, 1200, 1200, 64, 1211, 32, 912, 900, 900, 12, 901, 10} }
591};
592
9f291634 593/* 1280x600 (GTF) */
23e5abd5 594static struct crt_mode_table CRTM1280x600[] = {
fd3cc698 595 /* r_rate, hsp, vsp */
9f291634 596 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 597 {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
9f291634
JC		 598 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
599};
600
601/* 1360x768 (CVT) */
23e5abd5 602static struct crt_mode_table CRTM1360x768[] = {
fd3cc698 603 /* r_rate, hsp, vsp */
9f291634 604 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 605 {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
9f291634
JC		 606 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
607};
608
609/* 1360x768 (CVT Reduce Blanking) */
23e5abd5 610static struct crt_mode_table CRTM1360x768_RB[] = {
fd3cc698 611 /* r_rate, hsp, vsp */
9f291634 612 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 613 {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
9f291634
JC		 614 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
615};
616
617/* 1366x768 (GTF) */
23e5abd5 618static struct crt_mode_table CRTM1366x768[] = {
fd3cc698 619 /* r_rate, hsp, vsp */
9f291634 620 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 621 {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
9f291634 622 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
fd3cc698 623 {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
9f291634
JC		 624 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
625};
626
627/* 1440x900 (CVT) */
23e5abd5 628static struct crt_mode_table CRTM1440x900[] = {
fd3cc698 629 /* r_rate, hsp, vsp */
9f291634 630 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 631 {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
9f291634 632 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
fd3cc698 633 {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
9f291634
JC		 634 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
635};
636
637/* 1440x900 (CVT Reduce Blanking) */
23e5abd5 638static struct crt_mode_table CRTM1440x900_RB[] = {
fd3cc698 639 /* r_rate, hsp, vsp */
9f291634 640 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 641 {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
9f291634
JC		 642 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
643};
644
645/* 1600x900 (CVT) */
23e5abd5 646static struct crt_mode_table CRTM1600x900[] = {
fd3cc698 647 /* r_rate, hsp, vsp */
9f291634 648 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 649 {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
9f291634
JC		 650 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
651};
652
653/* 1600x900 (CVT Reduce Blanking) */
23e5abd5 654static struct crt_mode_table CRTM1600x900_RB[] = {
fd3cc698 655 /* r_rate, hsp, vsp */
9f291634 656 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 657 {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
9f291634
JC		 658 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
659};
660
661/* 1600x1024 (GTF) */
23e5abd5 662static struct crt_mode_table CRTM1600x1024[] = {
fd3cc698 663 /* r_rate, hsp, vsp */
9f291634 664 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 665 {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
9f291634
JC		 666 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
667};
668
669/* 1792x1344 (DMT) */
23e5abd5 670static struct crt_mode_table CRTM1792x1344[] = {
fd3cc698 671 /* r_rate, hsp, vsp */
9f291634 672 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 673 {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
9f291634
JC		 674 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
675};
676
677/* 1856x1392 (DMT) */
23e5abd5 678static struct crt_mode_table CRTM1856x1392[] = {
fd3cc698 679 /* r_rate, hsp, vsp */
9f291634 680 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 681 {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
9f291634
JC		 682 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
683};
684
685/* 1920x1200 (CVT) */
23e5abd5 686static struct crt_mode_table CRTM1920x1200[] = {
fd3cc698 687 /* r_rate, hsp, vsp */
9f291634 688 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 689 {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
9f291634
JC		 690 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
691};
692
693/* 1920x1200 (CVT with Reduce Blanking) */
23e5abd5 694static struct crt_mode_table CRTM1920x1200_RB[] = {
fd3cc698 695 /* r_rate, hsp, vsp */
9f291634 696 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 697 {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
9f291634
JC		 698 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
699};
700
701/* 2048x1536 (CVT) */
23e5abd5 702static struct crt_mode_table CRTM2048x1536[] = {
fd3cc698 703 /* r_rate, hsp, vsp */
9f291634 704 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
fd3cc698 705 {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
9f291634
JC		 706 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
707};
708
23e5abd5 709static struct VideoModeTable viafb_modes[] = {
9f291634 710 /* Display : 480x640 (GTF) */
dd73d686 711 {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
9f291634
JC		 712
713 /* Display : 640x480 */
dd73d686 714 {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
9f291634
JC		 715
716 /* Display : 720x480 (GTF) */
dd73d686 717 {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
9f291634
JC		 718
719 /* Display : 720x576 (GTF) */
dd73d686 720 {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
9f291634
JC		 721
722 /* Display : 800x600 */
dd73d686 723 {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
9f291634
JC		 724
725 /* Display : 800x480 (CVT) */
dd73d686 726 {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
9f291634
JC		 727
728 /* Display : 848x480 (CVT) */
dd73d686 729 {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
9f291634
JC		 730
731 /* Display : 852x480 (GTF) */
dd73d686 732 {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
9f291634
JC		 733
734 /* Display : 1024x512 (GTF) */
dd73d686 735 {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
9f291634
JC		 736
737 /* Display : 1024x600 */
dd73d686 738 {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
9f291634
JC		 739
740 /* Display : 1024x768 */
dd73d686 741 {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
9f291634
JC		 742
743 /* Display : 1152x864 */
dd73d686 744 {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
9f291634
JC		 745
746 /* Display : 1280x768 (GTF) */
dd73d686 747 {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
9f291634
JC		 748
749 /* Display : 960x600 (CVT) */
dd73d686 750 {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
9f291634
JC		 751
752 /* Display : 1000x600 (GTF) */
dd73d686 753 {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
9f291634
JC		 754
755 /* Display : 1024x576 (GTF) */
dd73d686 756 {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
9f291634
JC		 757
758 /* Display : 1088x612 (GTF) */
dd73d686 759 {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
9f291634
JC		 760
761 /* Display : 1152x720 (CVT) */
dd73d686 762 {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
9f291634
JC		 763
764 /* Display : 1200x720 (GTF) */
dd73d686 765 {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
9f291634 766
c205d932
CB		 767 /* Display : 1200x900 (DCON) */
768 {DCON1200x900, ARRAY_SIZE(DCON1200x900)},
769
9f291634 770 /* Display : 1280x600 (GTF) */
dd73d686 771 {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
9f291634
JC		 772
773 /* Display : 1280x800 (CVT) */
dd73d686 774 {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
9f291634
JC		 775
776 /* Display : 1280x960 */
dd73d686 777 {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
9f291634
JC		 778
779 /* Display : 1280x1024 */
dd73d686 780 {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
9f291634
JC		 781
782 /* Display : 1360x768 (CVT) */
dd73d686 783 {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
9f291634
JC		 784
785 /* Display : 1366x768 */
dd73d686 786 {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
9f291634
JC		 787
788 /* Display : 1368x768 (GTF) */
dd73d686 789 {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
9f291634
JC		 790
791 /* Display : 1440x900 (CVT) */
dd73d686 792 {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
9f291634
JC		 793
794 /* Display : 1440x1050 (GTF) */
dd73d686 795 {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
9f291634
JC		 796
797 /* Display : 1600x900 (CVT) */
dd73d686 798 {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
9f291634
JC		 799
800 /* Display : 1600x1024 (GTF) */
dd73d686 801 {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
9f291634
JC		 802
803 /* Display : 1600x1200 */
dd73d686 804 {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
9f291634
JC		 805
806 /* Display : 1680x1050 (CVT) */
dd73d686 807 {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
9f291634
JC		 808
809 /* Display : 1792x1344 (DMT) */
dd73d686 810 {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
9f291634
JC		 811
812 /* Display : 1856x1392 (DMT) */
dd73d686 813 {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
9f291634
JC		 814
815 /* Display : 1920x1440 */
dd73d686 816 {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
9f291634
JC		 817
818 /* Display : 2048x1536 */
dd73d686 819 {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
9f291634
JC		 820
821 /* Display : 1280x720 */
dd73d686 822 {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
9f291634
JC		 823
824 /* Display : 1920x1080 (CVT) */
dd73d686 825 {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
9f291634
JC		 826
827 /* Display : 1920x1200 (CVT) */
dd73d686 828 {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
9f291634
JC		 829
830 /* Display : 1400x1050 (CVT) */
dd73d686 831 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
9f291634 832};
dd73d686 833
23e5abd5 834static struct VideoModeTable viafb_rb_modes[] = {
dd73d686
FTS		 835 /* Display : 1360x768 (CVT Reduce Blanking) */
836 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
837
838 /* Display : 1440x900 (CVT Reduce Blanking) */
839 {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
840
841 /* Display : 1400x1050 (CVT Reduce Blanking) */
842 {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
843
844 /* Display : 1600x900 (CVT Reduce Blanking) */
845 {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
846
847 /* Display : 1680x1050 (CVT Reduce Blanking) */
848 {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
849
850 /* Display : 1920x1080 (CVT Reduce Blanking) */
851 {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
852
853 /* Display : 1920x1200 (CVT Reduce Blanking) */
854 {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
855};
856
deb7aab6
FTS		 857int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
858int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
859int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
860int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
0306ab11 861int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
deb7aab6
FTS		 862int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
863int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
dd73d686
FTS		 864
865
866struct VideoModeTable *viafb_get_mode(int hres, int vres)
867{
868 u32 i;
869 for (i = 0; i < ARRAY_SIZE(viafb_modes); i++)
870 if (viafb_modes[i].mode_array &&
871 viafb_modes[i].crtc[0].crtc.hor_addr == hres &&
872 viafb_modes[i].crtc[0].crtc.ver_addr == vres)
873 return &viafb_modes[i];
874
875 return NULL;
876}
877
878struct VideoModeTable *viafb_get_rb_mode(int hres, int vres)
879{
880 u32 i;
881 for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++)
882 if (viafb_rb_modes[i].mode_array &&
883 viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres &&
884 viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres)
885 return &viafb_rb_modes[i];
886
887 return NULL;
888}
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