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9f291634 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #include "global.h" | |
23 | struct res_map_refresh res_map_refresh_tbl[] = { | |
24 | /*hres, vres, vclock, vmode_refresh*/ | |
25 | {480, 640, RES_480X640_60HZ_PIXCLOCK, 60}, | |
26 | {640, 480, RES_640X480_60HZ_PIXCLOCK, 60}, | |
27 | {640, 480, RES_640X480_75HZ_PIXCLOCK, 75}, | |
28 | {640, 480, RES_640X480_85HZ_PIXCLOCK, 85}, | |
29 | {640, 480, RES_640X480_100HZ_PIXCLOCK, 100}, | |
30 | {640, 480, RES_640X480_120HZ_PIXCLOCK, 120}, | |
31 | {720, 480, RES_720X480_60HZ_PIXCLOCK, 60}, | |
32 | {720, 576, RES_720X576_60HZ_PIXCLOCK, 60}, | |
33 | {800, 480, RES_800X480_60HZ_PIXCLOCK, 60}, | |
34 | {800, 600, RES_800X600_60HZ_PIXCLOCK, 60}, | |
35 | {800, 600, RES_800X600_75HZ_PIXCLOCK, 75}, | |
36 | {800, 600, RES_800X600_85HZ_PIXCLOCK, 85}, | |
37 | {800, 600, RES_800X600_100HZ_PIXCLOCK, 100}, | |
38 | {800, 600, RES_800X600_120HZ_PIXCLOCK, 120}, | |
39 | {848, 480, RES_848X480_60HZ_PIXCLOCK, 60}, | |
40 | {856, 480, RES_856X480_60HZ_PIXCLOCK, 60}, | |
41 | {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60}, | |
42 | {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60}, | |
43 | {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60}, | |
44 | {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75}, | |
45 | {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85}, | |
46 | {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100}, | |
47 | /* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/ | |
48 | {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75}, | |
49 | {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60}, | |
50 | {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60}, | |
51 | {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60}, | |
52 | {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60}, | |
53 | {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75}, | |
54 | {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85}, | |
55 | {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60}, | |
56 | {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60}, | |
57 | {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75}, | |
58 | {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60}, | |
59 | {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60}, | |
60 | {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60}, | |
61 | {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75}, | |
62 | {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60}, | |
63 | {960, 600, RES_960X600_60HZ_PIXCLOCK, 60}, | |
64 | {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60}, | |
65 | {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60}, | |
66 | {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60}, | |
67 | {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60}, | |
68 | {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60}, | |
c205d932 | 69 | {1200, 900, RES_1200X900_60HZ_PIXCLOCK, 60}, |
9f291634 JC |
70 | {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60}, |
71 | {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50}, | |
72 | {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50}, | |
73 | {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60}, | |
74 | {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50}, | |
75 | {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60}, | |
76 | {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60}, | |
77 | {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75}, | |
78 | {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60}, | |
79 | {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60}, | |
80 | {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60}, | |
81 | {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75}, | |
82 | {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60}, | |
83 | {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60}, | |
84 | {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60}, | |
85 | {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60}, | |
86 | {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75}, | |
87 | {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60} | |
88 | }; | |
89 | ||
90 | struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, | |
91 | {VIASR, SR15, 0x02, 0x02}, | |
92 | {VIASR, SR16, 0xBF, 0x08}, | |
93 | {VIASR, SR17, 0xFF, 0x1F}, | |
94 | {VIASR, SR18, 0xFF, 0x4E}, | |
95 | {VIASR, SR1A, 0xFB, 0x08}, | |
96 | {VIASR, SR1E, 0x0F, 0x01}, | |
97 | {VIASR, SR2A, 0xFF, 0x00}, | |
98 | {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ | |
99 | {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ | |
100 | {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ | |
101 | {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ | |
102 | {VIACR, CR32, 0xFF, 0x00}, | |
103 | {VIACR, CR33, 0xFF, 0x00}, | |
9f291634 JC |
104 | {VIACR, CR35, 0xFF, 0x00}, |
105 | {VIACR, CR36, 0x08, 0x00}, | |
9f291634 JC |
106 | {VIACR, CR69, 0xFF, 0x00}, |
107 | {VIACR, CR6A, 0xFF, 0x40}, | |
108 | {VIACR, CR6B, 0xFF, 0x00}, | |
109 | {VIACR, CR6C, 0xFF, 0x00}, | |
110 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ | |
111 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ | |
112 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ | |
113 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ | |
114 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ | |
115 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ | |
116 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ | |
117 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ | |
118 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ | |
119 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ | |
120 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ | |
121 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ | |
122 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ | |
123 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ | |
124 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ | |
125 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ | |
126 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ | |
127 | {VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */ | |
128 | {VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */ | |
129 | {VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */ | |
130 | {VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */ | |
131 | {VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */ | |
132 | {VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */ | |
133 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ | |
134 | {VIACR, CR96, 0xFF, 0x00}, | |
135 | {VIACR, CR97, 0xFF, 0x00}, | |
136 | {VIACR, CR99, 0xFF, 0x00}, | |
137 | {VIACR, CR9B, 0xFF, 0x00} | |
138 | }; | |
139 | ||
140 | /* Video Mode Table for VT3314 chipset*/ | |
141 | /* Common Setting for Video Mode */ | |
142 | struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, | |
143 | {VIASR, SR15, 0x02, 0x02}, | |
144 | {VIASR, SR16, 0xBF, 0x08}, | |
145 | {VIASR, SR17, 0xFF, 0x1F}, | |
146 | {VIASR, SR18, 0xFF, 0x4E}, | |
147 | {VIASR, SR1A, 0xFB, 0x82}, | |
148 | {VIASR, SR1B, 0xFF, 0xF0}, | |
149 | {VIASR, SR1F, 0xFF, 0x00}, | |
150 | {VIASR, SR1E, 0xFF, 0x01}, | |
151 | {VIASR, SR22, 0xFF, 0x1F}, | |
152 | {VIASR, SR2A, 0x0F, 0x00}, | |
153 | {VIASR, SR2E, 0xFF, 0xFF}, | |
154 | {VIASR, SR3F, 0xFF, 0xFF}, | |
155 | {VIASR, SR40, 0xF7, 0x00}, | |
156 | {VIASR, CR30, 0xFF, 0x04}, | |
157 | {VIACR, CR32, 0xFF, 0x00}, | |
158 | {VIACR, CR33, 0x7F, 0x00}, | |
9f291634 JC |
159 | {VIACR, CR35, 0xFF, 0x00}, |
160 | {VIACR, CR36, 0xFF, 0x31}, | |
161 | {VIACR, CR41, 0xFF, 0x80}, | |
162 | {VIACR, CR42, 0xFF, 0x00}, | |
163 | {VIACR, CR55, 0x80, 0x00}, | |
164 | {VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/ | |
9f291634 JC |
165 | {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ |
166 | {VIACR, CR69, 0xFF, 0x00}, | |
167 | {VIACR, CR6A, 0xFD, 0x40}, | |
168 | {VIACR, CR6B, 0xFF, 0x00}, | |
169 | {VIACR, CR6C, 0xFF, 0x00}, | |
170 | {VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */ | |
171 | {VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */ | |
172 | {VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */ | |
173 | {VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */ | |
174 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ | |
175 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ | |
176 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ | |
177 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ | |
178 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ | |
179 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ | |
180 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ | |
181 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ | |
182 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ | |
183 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ | |
184 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ | |
185 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ | |
186 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ | |
187 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ | |
188 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ | |
189 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ | |
190 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ | |
191 | {VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ | |
192 | {VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ | |
193 | {VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ | |
194 | {VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ | |
195 | {VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ | |
196 | {VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ | |
197 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ | |
198 | {VIACR, CR96, 0xFF, 0x00}, | |
199 | {VIACR, CR97, 0xFF, 0x00}, | |
200 | {VIACR, CR99, 0xFF, 0x00}, | |
201 | {VIACR, CR9B, 0xFF, 0x00}, | |
202 | {VIACR, CR9D, 0xFF, 0x80}, | |
203 | {VIACR, CR9E, 0xFF, 0x80} | |
204 | }; | |
205 | ||
206 | struct io_reg KM400_ModeXregs[] = { | |
207 | {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */ | |
208 | {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */ | |
209 | {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */ | |
210 | {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */ | |
211 | {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */ | |
212 | {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */ | |
213 | {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */ | |
214 | {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */ | |
215 | {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */ | |
216 | {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */ | |
217 | {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */ | |
218 | {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */ | |
219 | {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */ | |
220 | {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */ | |
221 | {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ | |
222 | {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ | |
223 | {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ | |
224 | {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ | |
225 | {VIACR, CR33, 0xFF, 0x00}, | |
226 | {VIACR, CR55, 0x80, 0x00}, | |
227 | {VIACR, CR5D, 0x80, 0x00}, | |
228 | {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */ | |
9f291634 JC |
229 | {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */ |
230 | {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */ | |
231 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ | |
232 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ | |
233 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ | |
234 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ | |
235 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ | |
236 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ | |
237 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ | |
238 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ | |
239 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ | |
240 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ | |
241 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ | |
242 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ | |
243 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ | |
244 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ | |
245 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ | |
246 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ | |
247 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ | |
248 | {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */ | |
249 | {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */ | |
250 | {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */ | |
251 | {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */ | |
252 | {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */ | |
253 | {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */ | |
254 | {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */ | |
255 | {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */ | |
256 | {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */ | |
257 | {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/ | |
258 | {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/ | |
259 | }; | |
260 | ||
261 | /* For VT3324: Common Setting for Video Mode */ | |
262 | struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01}, | |
263 | {VIASR, SR15, 0x02, 0x02}, | |
264 | {VIASR, SR16, 0xBF, 0x08}, | |
265 | {VIASR, SR17, 0xFF, 0x1F}, | |
266 | {VIASR, SR18, 0xFF, 0x4E}, | |
267 | {VIASR, SR1A, 0xFB, 0x08}, | |
9f291634 JC |
268 | {VIASR, SR1B, 0xFF, 0xF0}, |
269 | {VIASR, SR1E, 0xFF, 0x01}, | |
270 | {VIASR, SR2A, 0xFF, 0x00}, | |
271 | {VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ | |
272 | {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ | |
273 | {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ | |
274 | {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ | |
275 | {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ | |
276 | {VIACR, CR32, 0xFF, 0x00}, | |
277 | {VIACR, CR33, 0xFF, 0x00}, | |
9f291634 JC |
278 | {VIACR, CR35, 0xFF, 0x00}, |
279 | {VIACR, CR36, 0x08, 0x00}, | |
280 | {VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */ | |
9f291634 JC |
281 | {VIACR, CR69, 0xFF, 0x00}, |
282 | {VIACR, CR6A, 0xFF, 0x40}, | |
283 | {VIACR, CR6B, 0xFF, 0x00}, | |
284 | {VIACR, CR6C, 0xFF, 0x00}, | |
285 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ | |
286 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ | |
287 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ | |
288 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ | |
289 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ | |
290 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ | |
291 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ | |
292 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ | |
293 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ | |
294 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ | |
295 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ | |
296 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ | |
297 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ | |
298 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ | |
299 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ | |
300 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ | |
301 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ | |
302 | {VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ | |
303 | {VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */ | |
304 | {VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */ | |
305 | {VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */ | |
306 | {VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */ | |
307 | {VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */ | |
308 | {VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */ | |
309 | {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ | |
310 | {VIACR, CR96, 0xFF, 0x00}, | |
311 | {VIACR, CR97, 0xFF, 0x00}, | |
312 | {VIACR, CR99, 0xFF, 0x00}, | |
8594ac33 | 313 | {VIACR, CR9B, 0xFF, 0x00} |
9f291634 JC |
314 | }; |
315 | ||
0306ab11 HW |
316 | struct io_reg VX855_ModeXregs[] = { |
317 | {VIASR, SR10, 0xFF, 0x01}, | |
318 | {VIASR, SR15, 0x02, 0x02}, | |
319 | {VIASR, SR16, 0xBF, 0x08}, | |
320 | {VIASR, SR17, 0xFF, 0x1F}, | |
321 | {VIASR, SR18, 0xFF, 0x4E}, | |
322 | {VIASR, SR1A, 0xFB, 0x08}, | |
323 | {VIASR, SR1B, 0xFF, 0xF0}, | |
324 | {VIASR, SR1E, 0x07, 0x01}, | |
325 | {VIASR, SR2A, 0xF0, 0x00}, | |
326 | {VIASR, SR58, 0xFF, 0x00}, | |
327 | {VIASR, SR59, 0xFF, 0x00}, | |
328 | {VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */ | |
329 | {VIACR, CR09, 0xFF, 0x00}, /* Initial CR09=0*/ | |
330 | {VIACR, CR11, 0x8F, 0x00}, /* IGA1 initial Vertical end */ | |
331 | {VIACR, CR17, 0x7F, 0x00}, /* IGA1 CRT Mode control init */ | |
332 | {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */ | |
333 | {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */ | |
334 | {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */ | |
335 | {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */ | |
336 | {VIACR, CR32, 0xFF, 0x00}, | |
337 | {VIACR, CR33, 0x7F, 0x00}, | |
338 | {VIACR, CR35, 0xFF, 0x00}, | |
339 | {VIACR, CR36, 0x08, 0x00}, | |
340 | {VIACR, CR69, 0xFF, 0x00}, | |
341 | {VIACR, CR6A, 0xFD, 0x60}, | |
342 | {VIACR, CR6B, 0xFF, 0x00}, | |
343 | {VIACR, CR6C, 0xFF, 0x00}, | |
344 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ | |
345 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ | |
346 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ | |
347 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ | |
348 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ | |
349 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ | |
350 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ | |
351 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ | |
352 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ | |
353 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ | |
354 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ | |
355 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ | |
356 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ | |
357 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ | |
358 | {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */ | |
359 | {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */ | |
360 | {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */ | |
361 | {VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */ | |
362 | {VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */ | |
363 | {VIACR, CR96, 0xFF, 0x00}, | |
364 | {VIACR, CR97, 0xFF, 0x00}, | |
365 | {VIACR, CR99, 0xFF, 0x00}, | |
366 | {VIACR, CR9B, 0xFF, 0x00}, | |
367 | {VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */ | |
368 | }; | |
369 | ||
9f291634 JC |
370 | /* Video Mode Table */ |
371 | /* Common Setting for Video Mode */ | |
372 | struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00}, | |
373 | {VIASR, SR2A, 0x0F, 0x00}, | |
374 | {VIASR, SR15, 0x02, 0x02}, | |
375 | {VIASR, SR16, 0xBF, 0x08}, | |
376 | {VIASR, SR17, 0xFF, 0x1F}, | |
377 | {VIASR, SR18, 0xFF, 0x4E}, | |
378 | {VIASR, SR1A, 0xFB, 0x08}, | |
379 | ||
380 | {VIACR, CR32, 0xFF, 0x00}, | |
9f291634 JC |
381 | {VIACR, CR35, 0xFF, 0x00}, |
382 | {VIACR, CR36, 0x08, 0x00}, | |
383 | {VIACR, CR6A, 0xFF, 0x80}, | |
384 | {VIACR, CR6A, 0xFF, 0xC0}, | |
385 | ||
386 | {VIACR, CR55, 0x80, 0x00}, | |
387 | {VIACR, CR5D, 0x80, 0x00}, | |
388 | ||
389 | {VIAGR, GR20, 0xFF, 0x00}, | |
390 | {VIAGR, GR21, 0xFF, 0x00}, | |
391 | {VIAGR, GR22, 0xFF, 0x00}, | |
392 | /* LCD Parameters */ | |
393 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */ | |
394 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */ | |
395 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */ | |
396 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */ | |
397 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */ | |
398 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */ | |
399 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */ | |
400 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */ | |
401 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */ | |
402 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */ | |
403 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */ | |
404 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */ | |
405 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */ | |
406 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */ | |
407 | ||
408 | }; | |
409 | ||
410 | /* Mode:1024X768 */ | |
411 | struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C}, | |
412 | {VIASR, 0x18, 0xFF, 0x4C} | |
413 | }; | |
414 | ||
415 | struct patch_table res_patch_table[] = { | |
dd73d686 | 416 | {ARRAY_SIZE(PM1024x768), PM1024x768} |
9f291634 JC |
417 | }; |
418 | ||
419 | /* struct VPITTable { | |
420 | unsigned char Misc; | |
421 | unsigned char SR[StdSR]; | |
422 | unsigned char CR[StdCR]; | |
423 | unsigned char GR[StdGR]; | |
424 | unsigned char AR[StdAR]; | |
425 | };*/ | |
426 | ||
427 | struct VPITTable VPIT = { | |
428 | /* Msic */ | |
429 | 0xC7, | |
430 | /* Sequencer */ | |
431 | {0x01, 0x0F, 0x00, 0x0E}, | |
432 | /* Graphic Controller */ | |
433 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF}, | |
434 | /* Attribute Controller */ | |
435 | {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, | |
436 | 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, | |
437 | 0x01, 0x00, 0x0F, 0x00} | |
438 | }; | |
439 | ||
440 | /********************/ | |
441 | /* Mode Table */ | |
442 | /********************/ | |
443 | ||
444 | /* 480x640 */ | |
445 | struct crt_mode_table CRTM480x640[] = { | |
446 | /* r_rate, vclk, hsp, vsp */ | |
447 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
448 | {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP, | |
449 | {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/ | |
450 | }; | |
451 | ||
452 | /* 640x480*/ | |
453 | struct crt_mode_table CRTM640x480[] = { | |
454 | /*r_rate,vclk,hsp,vsp */ | |
455 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
456 | {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP, | |
457 | {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} }, | |
458 | {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP, | |
459 | {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} }, | |
460 | {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP, | |
461 | {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} }, | |
462 | {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP, | |
463 | {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/ | |
464 | {REFRESH_120, CLK_52_406M, M640X480_R120_HSP, | |
465 | M640X480_R120_VSP, | |
466 | {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, | |
467 | 3} } /*GTF*/ | |
468 | }; | |
469 | ||
470 | /*720x480 (GTF)*/ | |
471 | struct crt_mode_table CRTM720x480[] = { | |
472 | /*r_rate,vclk,hsp,vsp */ | |
473 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
474 | {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP, | |
475 | {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} } | |
476 | ||
477 | }; | |
478 | ||
479 | /*720x576 (GTF)*/ | |
480 | struct crt_mode_table CRTM720x576[] = { | |
481 | /*r_rate,vclk,hsp,vsp */ | |
482 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
483 | {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP, | |
484 | {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} } | |
485 | }; | |
486 | ||
487 | /* 800x480 (CVT) */ | |
488 | struct crt_mode_table CRTM800x480[] = { | |
489 | /* r_rate, vclk, hsp, vsp */ | |
490 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
491 | {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP, | |
492 | {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} } | |
493 | }; | |
494 | ||
495 | /* 800x600*/ | |
496 | struct crt_mode_table CRTM800x600[] = { | |
497 | /*r_rate,vclk,hsp,vsp */ | |
498 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
499 | {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP, | |
500 | {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} }, | |
501 | {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP, | |
502 | {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} }, | |
503 | {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP, | |
504 | {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} }, | |
505 | {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP, | |
506 | {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} }, | |
507 | {REFRESH_120, CLK_83_950M, M800X600_R120_HSP, | |
508 | M800X600_R120_VSP, | |
509 | {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, | |
510 | 3} } | |
511 | }; | |
512 | ||
513 | /* 848x480 (CVT) */ | |
514 | struct crt_mode_table CRTM848x480[] = { | |
515 | /* r_rate, vclk, hsp, vsp */ | |
516 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
517 | {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP, | |
518 | {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} } | |
519 | }; | |
520 | ||
521 | /*856x480 (GTF) convert to 852x480*/ | |
522 | struct crt_mode_table CRTM852x480[] = { | |
523 | /*r_rate,vclk,hsp,vsp */ | |
524 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
525 | {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP, | |
526 | {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} } | |
527 | }; | |
528 | ||
529 | /*1024x512 (GTF)*/ | |
530 | struct crt_mode_table CRTM1024x512[] = { | |
531 | /*r_rate,vclk,hsp,vsp */ | |
532 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
533 | {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP, | |
534 | {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} } | |
535 | ||
536 | }; | |
537 | ||
538 | /* 1024x600*/ | |
539 | struct crt_mode_table CRTM1024x600[] = { | |
540 | /*r_rate,vclk,hsp,vsp */ | |
541 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
542 | {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP, | |
543 | {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} }, | |
544 | }; | |
545 | ||
546 | /* 1024x768*/ | |
547 | struct crt_mode_table CRTM1024x768[] = { | |
548 | /*r_rate,vclk,hsp,vsp */ | |
549 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
550 | {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP, | |
551 | {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} }, | |
552 | {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP, | |
553 | {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} }, | |
554 | {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP, | |
555 | {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} }, | |
556 | {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP, | |
557 | {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} } | |
558 | }; | |
559 | ||
560 | /* 1152x864*/ | |
561 | struct crt_mode_table CRTM1152x864[] = { | |
562 | /*r_rate,vclk,hsp,vsp */ | |
563 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
564 | {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP, | |
565 | {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} } | |
566 | ||
567 | }; | |
568 | ||
569 | /* 1280x720 (HDMI 720P)*/ | |
570 | struct crt_mode_table CRTM1280x720[] = { | |
571 | /*r_rate,vclk,hsp,vsp */ | |
572 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
573 | {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP, | |
574 | {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} }, | |
575 | {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP, | |
576 | {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} } | |
577 | }; | |
578 | ||
579 | /*1280x768 (GTF)*/ | |
580 | struct crt_mode_table CRTM1280x768[] = { | |
581 | /*r_rate,vclk,hsp,vsp */ | |
582 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
583 | {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP, | |
584 | {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} }, | |
585 | {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP, | |
586 | {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} } | |
587 | }; | |
588 | ||
589 | /* 1280x800 (CVT) */ | |
590 | struct crt_mode_table CRTM1280x800[] = { | |
591 | /* r_rate, vclk, hsp, vsp */ | |
592 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
593 | {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP, | |
594 | {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} } | |
595 | }; | |
596 | ||
597 | /*1280x960*/ | |
598 | struct crt_mode_table CRTM1280x960[] = { | |
599 | /*r_rate,vclk,hsp,vsp */ | |
600 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
601 | {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP, | |
602 | {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} } | |
603 | }; | |
604 | ||
605 | /* 1280x1024*/ | |
606 | struct crt_mode_table CRTM1280x1024[] = { | |
607 | /*r_rate,vclk,,hsp,vsp */ | |
608 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
609 | {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP, | |
610 | {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025, | |
611 | 3} }, | |
612 | {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP, | |
613 | {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025, | |
614 | 3} }, | |
615 | {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP, | |
616 | {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} } | |
617 | }; | |
618 | ||
619 | /* 1368x768 (GTF) */ | |
620 | struct crt_mode_table CRTM1368x768[] = { | |
621 | /* r_rate, vclk, hsp, vsp */ | |
622 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
623 | {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, | |
624 | {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} } | |
625 | }; | |
626 | ||
627 | /*1440x1050 (GTF)*/ | |
628 | struct crt_mode_table CRTM1440x1050[] = { | |
629 | /*r_rate,vclk,hsp,vsp */ | |
630 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
631 | {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP, | |
632 | {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} } | |
633 | }; | |
634 | ||
635 | /* 1600x1200*/ | |
636 | struct crt_mode_table CRTM1600x1200[] = { | |
637 | /*r_rate,vclk,hsp,vsp */ | |
638 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
639 | {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP, | |
640 | {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, | |
641 | 3} }, | |
642 | {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP, | |
643 | {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} } | |
644 | ||
645 | }; | |
646 | ||
647 | /* 1680x1050 (CVT) */ | |
648 | struct crt_mode_table CRTM1680x1050[] = { | |
649 | /* r_rate, vclk, hsp, vsp */ | |
650 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
651 | {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP, | |
652 | {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053, | |
653 | 6} }, | |
654 | {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP, | |
655 | {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} } | |
656 | }; | |
657 | ||
658 | /* 1680x1050 (CVT Reduce Blanking) */ | |
659 | struct crt_mode_table CRTM1680x1050_RB[] = { | |
660 | /* r_rate, vclk, hsp, vsp */ | |
661 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
662 | {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP, | |
663 | M1680x1050_RB_R60_VSP, | |
664 | {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} } | |
665 | }; | |
666 | ||
667 | /* 1920x1080 (CVT)*/ | |
668 | struct crt_mode_table CRTM1920x1080[] = { | |
669 | /*r_rate,vclk,hsp,vsp */ | |
670 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
671 | {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP, | |
672 | {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} } | |
673 | }; | |
674 | ||
675 | /* 1920x1080 (CVT with Reduce Blanking) */ | |
676 | struct crt_mode_table CRTM1920x1080_RB[] = { | |
677 | /* r_rate, vclk, hsp, vsp */ | |
678 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
679 | {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP, | |
680 | M1920X1080_RB_R60_VSP, | |
681 | {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} } | |
682 | }; | |
683 | ||
684 | /* 1920x1440*/ | |
685 | struct crt_mode_table CRTM1920x1440[] = { | |
686 | /*r_rate,vclk,hsp,vsp */ | |
687 | /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
688 | {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP, | |
689 | {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441, | |
690 | 3} }, | |
691 | {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP, | |
692 | {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} } | |
693 | }; | |
694 | ||
695 | /* 1400x1050 (CVT) */ | |
696 | struct crt_mode_table CRTM1400x1050[] = { | |
697 | /* r_rate, vclk, hsp, vsp */ | |
698 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
699 | {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP, | |
700 | {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053, | |
701 | 4} }, | |
702 | {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP, | |
703 | {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} } | |
704 | }; | |
705 | ||
706 | /* 1400x1050 (CVT Reduce Blanking) */ | |
707 | struct crt_mode_table CRTM1400x1050_RB[] = { | |
708 | /* r_rate, vclk, hsp, vsp */ | |
709 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
710 | {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP, | |
711 | M1400X1050_RB_R60_VSP, | |
712 | {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} } | |
713 | }; | |
714 | ||
715 | /* 960x600 (CVT) */ | |
716 | struct crt_mode_table CRTM960x600[] = { | |
717 | /* r_rate, vclk, hsp, vsp */ | |
718 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
719 | {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP, | |
720 | {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} } | |
721 | }; | |
722 | ||
723 | /* 1000x600 (GTF) */ | |
724 | struct crt_mode_table CRTM1000x600[] = { | |
725 | /* r_rate, vclk, hsp, vsp */ | |
726 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
727 | {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP, | |
728 | {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} } | |
729 | }; | |
730 | ||
731 | /* 1024x576 (GTF) */ | |
732 | struct crt_mode_table CRTM1024x576[] = { | |
733 | /* r_rate, vclk, hsp, vsp */ | |
734 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
735 | {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP, | |
736 | {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} } | |
737 | }; | |
738 | ||
739 | /* 1088x612 (CVT) */ | |
740 | struct crt_mode_table CRTM1088x612[] = { | |
741 | /* r_rate, vclk, hsp, vsp */ | |
742 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
743 | {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP, | |
744 | {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} } | |
745 | }; | |
746 | ||
747 | /* 1152x720 (CVT) */ | |
748 | struct crt_mode_table CRTM1152x720[] = { | |
749 | /* r_rate, vclk, hsp, vsp */ | |
750 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
751 | {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP, | |
752 | {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} } | |
753 | }; | |
754 | ||
755 | /* 1200x720 (GTF) */ | |
756 | struct crt_mode_table CRTM1200x720[] = { | |
757 | /* r_rate, vclk, hsp, vsp */ | |
758 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
759 | {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP, | |
760 | {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} } | |
761 | }; | |
762 | ||
c205d932 CB |
763 | /* 1200x900 (DCON) */ |
764 | struct crt_mode_table DCON1200x900[] = { | |
765 | /* r_rate, vclk, hsp, vsp */ | |
766 | {REFRESH_60, CLK_57_275M, M1200X900_R60_HSP, M1200X900_R60_VSP, | |
767 | /* The correct htotal is 1240, but this doesn't raster on VX855. */ | |
768 | /* Via suggested changing to a multiple of 16, hence 1264. */ | |
769 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
770 | {1264, 1200, 1200, 64, 1211, 32, 912, 900, 900, 12, 901, 10} } | |
771 | }; | |
772 | ||
9f291634 JC |
773 | /* 1280x600 (GTF) */ |
774 | struct crt_mode_table CRTM1280x600[] = { | |
775 | /* r_rate, vclk, hsp, vsp */ | |
776 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
777 | {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP, | |
778 | {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} } | |
779 | }; | |
780 | ||
781 | /* 1360x768 (CVT) */ | |
782 | struct crt_mode_table CRTM1360x768[] = { | |
783 | /* r_rate, vclk, hsp, vsp */ | |
784 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
785 | {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP, | |
786 | {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} } | |
787 | }; | |
788 | ||
789 | /* 1360x768 (CVT Reduce Blanking) */ | |
790 | struct crt_mode_table CRTM1360x768_RB[] = { | |
791 | /* r_rate, vclk, hsp, vsp */ | |
792 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
793 | {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP, | |
794 | M1360X768_RB_R60_VSP, | |
795 | {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} } | |
796 | }; | |
797 | ||
798 | /* 1366x768 (GTF) */ | |
799 | struct crt_mode_table CRTM1366x768[] = { | |
800 | /* r_rate, vclk, hsp, vsp */ | |
801 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
802 | {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP, | |
803 | {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }, | |
804 | {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP, | |
805 | {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} } | |
806 | }; | |
807 | ||
808 | /* 1440x900 (CVT) */ | |
809 | struct crt_mode_table CRTM1440x900[] = { | |
810 | /* r_rate, vclk, hsp, vsp */ | |
811 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
812 | {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP, | |
813 | {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} }, | |
814 | {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP, | |
815 | {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} } | |
816 | }; | |
817 | ||
818 | /* 1440x900 (CVT Reduce Blanking) */ | |
819 | struct crt_mode_table CRTM1440x900_RB[] = { | |
820 | /* r_rate, vclk, hsp, vsp */ | |
821 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
822 | {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP, | |
823 | M1440X900_RB_R60_VSP, | |
824 | {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} } | |
825 | }; | |
826 | ||
827 | /* 1600x900 (CVT) */ | |
828 | struct crt_mode_table CRTM1600x900[] = { | |
829 | /* r_rate, vclk, hsp, vsp */ | |
830 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
831 | {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP, | |
832 | {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} } | |
833 | }; | |
834 | ||
835 | /* 1600x900 (CVT Reduce Blanking) */ | |
836 | struct crt_mode_table CRTM1600x900_RB[] = { | |
837 | /* r_rate, vclk, hsp, vsp */ | |
838 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
839 | {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP, | |
840 | M1600X900_RB_R60_VSP, | |
841 | {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} } | |
842 | }; | |
843 | ||
844 | /* 1600x1024 (GTF) */ | |
845 | struct crt_mode_table CRTM1600x1024[] = { | |
846 | /* r_rate, vclk, hsp, vsp */ | |
847 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
848 | {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP, | |
849 | {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} } | |
850 | }; | |
851 | ||
852 | /* 1792x1344 (DMT) */ | |
853 | struct crt_mode_table CRTM1792x1344[] = { | |
854 | /* r_rate, vclk, hsp, vsp */ | |
855 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
856 | {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP, | |
857 | {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} } | |
858 | }; | |
859 | ||
860 | /* 1856x1392 (DMT) */ | |
861 | struct crt_mode_table CRTM1856x1392[] = { | |
862 | /* r_rate, vclk, hsp, vsp */ | |
863 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
864 | {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP, | |
865 | {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} } | |
866 | }; | |
867 | ||
868 | /* 1920x1200 (CVT) */ | |
869 | struct crt_mode_table CRTM1920x1200[] = { | |
870 | /* r_rate, vclk, hsp, vsp */ | |
871 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
872 | {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP, | |
873 | {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} } | |
874 | }; | |
875 | ||
876 | /* 1920x1200 (CVT with Reduce Blanking) */ | |
877 | struct crt_mode_table CRTM1920x1200_RB[] = { | |
878 | /* r_rate, vclk, hsp, vsp */ | |
879 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
880 | {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP, | |
881 | M1920X1200_RB_R60_VSP, | |
882 | {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} } | |
883 | }; | |
884 | ||
885 | /* 2048x1536 (CVT) */ | |
886 | struct crt_mode_table CRTM2048x1536[] = { | |
887 | /* r_rate, vclk, hsp, vsp */ | |
888 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
889 | {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP, | |
890 | {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} } | |
891 | }; | |
892 | ||
dd73d686 | 893 | struct VideoModeTable viafb_modes[] = { |
9f291634 | 894 | /* Display : 480x640 (GTF) */ |
dd73d686 | 895 | {CRTM480x640, ARRAY_SIZE(CRTM480x640)}, |
9f291634 JC |
896 | |
897 | /* Display : 640x480 */ | |
dd73d686 | 898 | {CRTM640x480, ARRAY_SIZE(CRTM640x480)}, |
9f291634 JC |
899 | |
900 | /* Display : 720x480 (GTF) */ | |
dd73d686 | 901 | {CRTM720x480, ARRAY_SIZE(CRTM720x480)}, |
9f291634 JC |
902 | |
903 | /* Display : 720x576 (GTF) */ | |
dd73d686 | 904 | {CRTM720x576, ARRAY_SIZE(CRTM720x576)}, |
9f291634 JC |
905 | |
906 | /* Display : 800x600 */ | |
dd73d686 | 907 | {CRTM800x600, ARRAY_SIZE(CRTM800x600)}, |
9f291634 JC |
908 | |
909 | /* Display : 800x480 (CVT) */ | |
dd73d686 | 910 | {CRTM800x480, ARRAY_SIZE(CRTM800x480)}, |
9f291634 JC |
911 | |
912 | /* Display : 848x480 (CVT) */ | |
dd73d686 | 913 | {CRTM848x480, ARRAY_SIZE(CRTM848x480)}, |
9f291634 JC |
914 | |
915 | /* Display : 852x480 (GTF) */ | |
dd73d686 | 916 | {CRTM852x480, ARRAY_SIZE(CRTM852x480)}, |
9f291634 JC |
917 | |
918 | /* Display : 1024x512 (GTF) */ | |
dd73d686 | 919 | {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)}, |
9f291634 JC |
920 | |
921 | /* Display : 1024x600 */ | |
dd73d686 | 922 | {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)}, |
9f291634 JC |
923 | |
924 | /* Display : 1024x768 */ | |
dd73d686 | 925 | {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)}, |
9f291634 JC |
926 | |
927 | /* Display : 1152x864 */ | |
dd73d686 | 928 | {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)}, |
9f291634 JC |
929 | |
930 | /* Display : 1280x768 (GTF) */ | |
dd73d686 | 931 | {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)}, |
9f291634 JC |
932 | |
933 | /* Display : 960x600 (CVT) */ | |
dd73d686 | 934 | {CRTM960x600, ARRAY_SIZE(CRTM960x600)}, |
9f291634 JC |
935 | |
936 | /* Display : 1000x600 (GTF) */ | |
dd73d686 | 937 | {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)}, |
9f291634 JC |
938 | |
939 | /* Display : 1024x576 (GTF) */ | |
dd73d686 | 940 | {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, |
9f291634 JC |
941 | |
942 | /* Display : 1088x612 (GTF) */ | |
dd73d686 | 943 | {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)}, |
9f291634 JC |
944 | |
945 | /* Display : 1152x720 (CVT) */ | |
dd73d686 | 946 | {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)}, |
9f291634 JC |
947 | |
948 | /* Display : 1200x720 (GTF) */ | |
dd73d686 | 949 | {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)}, |
9f291634 | 950 | |
c205d932 CB |
951 | /* Display : 1200x900 (DCON) */ |
952 | {DCON1200x900, ARRAY_SIZE(DCON1200x900)}, | |
953 | ||
9f291634 | 954 | /* Display : 1280x600 (GTF) */ |
dd73d686 | 955 | {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)}, |
9f291634 JC |
956 | |
957 | /* Display : 1280x800 (CVT) */ | |
dd73d686 | 958 | {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, |
9f291634 JC |
959 | |
960 | /* Display : 1280x960 */ | |
dd73d686 | 961 | {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)}, |
9f291634 JC |
962 | |
963 | /* Display : 1280x1024 */ | |
dd73d686 | 964 | {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)}, |
9f291634 JC |
965 | |
966 | /* Display : 1360x768 (CVT) */ | |
dd73d686 | 967 | {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)}, |
9f291634 JC |
968 | |
969 | /* Display : 1366x768 */ | |
dd73d686 | 970 | {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)}, |
9f291634 JC |
971 | |
972 | /* Display : 1368x768 (GTF) */ | |
dd73d686 | 973 | {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)}, |
9f291634 JC |
974 | |
975 | /* Display : 1440x900 (CVT) */ | |
dd73d686 | 976 | {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)}, |
9f291634 JC |
977 | |
978 | /* Display : 1440x1050 (GTF) */ | |
dd73d686 | 979 | {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)}, |
9f291634 JC |
980 | |
981 | /* Display : 1600x900 (CVT) */ | |
dd73d686 | 982 | {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)}, |
9f291634 JC |
983 | |
984 | /* Display : 1600x1024 (GTF) */ | |
dd73d686 | 985 | {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)}, |
9f291634 JC |
986 | |
987 | /* Display : 1600x1200 */ | |
dd73d686 | 988 | {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)}, |
9f291634 JC |
989 | |
990 | /* Display : 1680x1050 (CVT) */ | |
dd73d686 | 991 | {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)}, |
9f291634 JC |
992 | |
993 | /* Display : 1792x1344 (DMT) */ | |
dd73d686 | 994 | {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)}, |
9f291634 JC |
995 | |
996 | /* Display : 1856x1392 (DMT) */ | |
dd73d686 | 997 | {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)}, |
9f291634 JC |
998 | |
999 | /* Display : 1920x1440 */ | |
dd73d686 | 1000 | {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)}, |
9f291634 JC |
1001 | |
1002 | /* Display : 2048x1536 */ | |
dd73d686 | 1003 | {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)}, |
9f291634 JC |
1004 | |
1005 | /* Display : 1280x720 */ | |
dd73d686 | 1006 | {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)}, |
9f291634 JC |
1007 | |
1008 | /* Display : 1920x1080 (CVT) */ | |
dd73d686 | 1009 | {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)}, |
9f291634 JC |
1010 | |
1011 | /* Display : 1920x1200 (CVT) */ | |
dd73d686 | 1012 | {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)}, |
9f291634 JC |
1013 | |
1014 | /* Display : 1400x1050 (CVT) */ | |
dd73d686 | 1015 | {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)} |
9f291634 | 1016 | }; |
dd73d686 FTS |
1017 | |
1018 | struct VideoModeTable viafb_rb_modes[] = { | |
1019 | /* Display : 1360x768 (CVT Reduce Blanking) */ | |
1020 | {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)}, | |
1021 | ||
1022 | /* Display : 1440x900 (CVT Reduce Blanking) */ | |
1023 | {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)}, | |
1024 | ||
1025 | /* Display : 1400x1050 (CVT Reduce Blanking) */ | |
1026 | {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)}, | |
1027 | ||
1028 | /* Display : 1600x900 (CVT Reduce Blanking) */ | |
1029 | {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)}, | |
1030 | ||
1031 | /* Display : 1680x1050 (CVT Reduce Blanking) */ | |
1032 | {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)}, | |
1033 | ||
1034 | /* Display : 1920x1080 (CVT Reduce Blanking) */ | |
1035 | {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)}, | |
1036 | ||
1037 | /* Display : 1920x1200 (CVT Reduce Blanking) */ | |
1038 | {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)} | |
1039 | }; | |
1040 | ||
9f291634 JC |
1041 | struct crt_mode_table CEAM1280x720[] = { |
1042 | {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP, | |
1043 | M1280X720_CEA_R60_VSP, | |
1044 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
1045 | {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} } | |
1046 | }; | |
1047 | struct crt_mode_table CEAM1920x1080[] = { | |
1048 | {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP, | |
1049 | M1920X1080_CEA_R60_VSP, | |
1050 | /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */ | |
1051 | {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} } | |
1052 | }; | |
1053 | struct VideoModeTable CEA_HDMI_Modes[] = { | |
1054 | /* Display : 1280x720 */ | |
dd73d686 FTS |
1055 | {CEAM1280x720, ARRAY_SIZE(CEAM1280x720)}, |
1056 | {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)} | |
9f291634 | 1057 | }; |
deb7aab6 FTS |
1058 | |
1059 | int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl); | |
1060 | int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes); | |
1061 | int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs); | |
1062 | int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs); | |
1063 | int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs); | |
1064 | int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs); | |
0306ab11 | 1065 | int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs); |
deb7aab6 FTS |
1066 | int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs); |
1067 | int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); | |
dd73d686 FTS |
1068 | |
1069 | ||
1070 | struct VideoModeTable *viafb_get_mode(int hres, int vres) | |
1071 | { | |
1072 | u32 i; | |
1073 | for (i = 0; i < ARRAY_SIZE(viafb_modes); i++) | |
1074 | if (viafb_modes[i].mode_array && | |
1075 | viafb_modes[i].crtc[0].crtc.hor_addr == hres && | |
1076 | viafb_modes[i].crtc[0].crtc.ver_addr == vres) | |
1077 | return &viafb_modes[i]; | |
1078 | ||
1079 | return NULL; | |
1080 | } | |
1081 | ||
1082 | struct VideoModeTable *viafb_get_rb_mode(int hres, int vres) | |
1083 | { | |
1084 | u32 i; | |
1085 | for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++) | |
1086 | if (viafb_rb_modes[i].mode_array && | |
1087 | viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres && | |
1088 | viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres) | |
1089 | return &viafb_rb_modes[i]; | |
1090 | ||
1091 | return NULL; | |
1092 | } |