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vme: tsi148: Improve 17 size determinations
[mirror_ubuntu-bionic-kernel.git] / drivers / vme / bridges / vme_tsi148.c
CommitLineData
d22b8ed9
MW		 1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
66bd8db5
MW		 4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
d22b8ed9
MW		 6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
d22b8ed9
MW		 16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
5a0e3ad6 28#include <linux/slab.h>
7946328f
MW		 29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
ac1a4f2c 32#include <linux/byteorder/generic.h>
db3b9e99 33#include <linux/vme.h>
d22b8ed9 34
d22b8ed9
MW		 35#include "../vme_bridge.h"
36#include "vme_tsi148.h"
37
d22b8ed9
MW		 38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39static void tsi148_remove(struct pci_dev *);
d22b8ed9
MW		 40
41
29848ac9 42/* Module parameter */
90ab5ee9 43static bool err_chk;
638f199d 44static int geoid;
d22b8ed9 45
584721ca 46static const char driver_name[] = "vme_tsi148";
d22b8ed9 47
c3a09c18 48static const struct pci_device_id tsi148_ids[] = {
d22b8ed9
MW		 49 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
50 { },
51};
52
553ebb8e
AIB		 53MODULE_DEVICE_TABLE(pci, tsi148_ids);
54
d22b8ed9
MW		 55static struct pci_driver tsi148_driver = {
56 .name = driver_name,
57 .id_table = tsi148_ids,
58 .probe = tsi148_probe,
59 .remove = tsi148_remove,
60};
61
62static void reg_join(unsigned int high, unsigned int low,
63 unsigned long long *variable)
64{
65 *variable = (unsigned long long)high << 32;
66 *variable |= (unsigned long long)low;
67}
68
69static void reg_split(unsigned long long variable, unsigned int *high,
70 unsigned int *low)
71{
72 *low = (unsigned int)variable & 0xFFFFFFFF;
73 *high = (unsigned int)(variable >> 32);
74}
75
76/*
77 * Wakes up DMA queue.
78 */
29848ac9
MW		 79static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
80 int channel_mask)
d22b8ed9
MW		 81{
82 u32 serviced = 0;
83
84 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
886953e9 85 wake_up(&bridge->dma_queue[0]);
d22b8ed9
MW		 86 serviced |= TSI148_LCSR_INTC_DMA0C;
87 }
88 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
886953e9 89 wake_up(&bridge->dma_queue[1]);
d22b8ed9
MW		 90 serviced |= TSI148_LCSR_INTC_DMA1C;
91 }
92
93 return serviced;
94}
95
96/*
97 * Wake up location monitor queue
98 */
29848ac9 99static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
d22b8ed9
MW		 100{
101 int i;
102 u32 serviced = 0;
103
104 for (i = 0; i < 4; i++) {
7946328f 105 if (stat & TSI148_LCSR_INTS_LMS[i]) {
d22b8ed9 106 /* We only enable interrupts if the callback is set */
fa54b326 107 bridge->lm_callback[i](bridge->lm_data[i]);
d22b8ed9
MW		 108 serviced |= TSI148_LCSR_INTC_LMC[i];
109 }
110 }
111
112 return serviced;
113}
114
115/*
116 * Wake up mail box queue.
117 *
118 * XXX This functionality is not exposed up though API.
119 */
48d9356e 120static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
d22b8ed9
MW		 121{
122 int i;
123 u32 val;
124 u32 serviced = 0;
48d9356e
MW		 125 struct tsi148_driver *bridge;
126
127 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 128
129 for (i = 0; i < 4; i++) {
7946328f 130 if (stat & TSI148_LCSR_INTS_MBS[i]) {
29848ac9 131 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
48d9356e
MW		 132 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
133 ": 0x%x\n", i, val);
d22b8ed9
MW		 134 serviced |= TSI148_LCSR_INTC_MBC[i];
135 }
136 }
137
138 return serviced;
139}
140
141/*
142 * Display error & status message when PERR (PCI) exception interrupt occurs.
143 */
48d9356e 144static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9 145{
48d9356e
MW		 146 struct tsi148_driver *bridge;
147
148 bridge = tsi148_bridge->driver_priv;
149
150 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
151 "attributes: %08x\n",
29848ac9
MW		 152 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
153 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
48d9356e
MW		 154 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
155
156 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
157 "completion reg: %08x\n",
29848ac9 158 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
48d9356e 159 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
d22b8ed9 160
29848ac9 161 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
d22b8ed9
MW		 162
163 return TSI148_LCSR_INTC_PERRC;
164}
165
166/*
167 * Save address and status when VME error interrupt occurs.
168 */
29848ac9 169static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 170{
171 unsigned int error_addr_high, error_addr_low;
172 unsigned long long error_addr;
173 u32 error_attrib;
472f16f3 174 int error_am;
29848ac9
MW		 175 struct tsi148_driver *bridge;
176
177 bridge = tsi148_bridge->driver_priv;
d22b8ed9 178
29848ac9
MW		 179 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
180 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
181 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
472f16f3 182 error_am = (error_attrib & TSI148_LCSR_VEAT_AM_M) >> 8;
d22b8ed9
MW		 183
184 reg_join(error_addr_high, error_addr_low, &error_addr);
185
186 /* Check for exception register overflow (we have lost error data) */
7946328f 187 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
48d9356e
MW		 188 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
189 "Occurred\n");
d22b8ed9
MW		 190 }
191
e2c6393f 192 if (err_chk)
472f16f3 193 vme_bus_error_handler(tsi148_bridge, error_addr, error_am);
e2c6393f 194 else
e31c51e4
MW		 195 dev_err(tsi148_bridge->parent,
196 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
197 error_addr, error_attrib);
d22b8ed9
MW		 198
199 /* Clear Status */
29848ac9 200 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
d22b8ed9
MW		 201
202 return TSI148_LCSR_INTC_VERRC;
203}
204
205/*
206 * Wake up IACK queue.
207 */
29848ac9 208static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
d22b8ed9 209{
886953e9 210 wake_up(&bridge->iack_queue);
d22b8ed9
MW		 211
212 return TSI148_LCSR_INTC_IACKC;
213}
214
215/*
216 * Calling VME bus interrupt callback if provided.
217 */
29848ac9
MW		 218static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
219 u32 stat)
d22b8ed9
MW		 220{
221 int vec, i, serviced = 0;
29848ac9
MW		 222 struct tsi148_driver *bridge;
223
224 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 225
226 for (i = 7; i > 0; i--) {
227 if (stat & (1 << i)) {
228 /*
7946328f
MW		 229 * Note: Even though the registers are defined as
230 * 32-bits in the spec, we only want to issue 8-bit
231 * IACK cycles on the bus, read from offset 3.
d22b8ed9 232 */
29848ac9 233 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
d22b8ed9 234
c813f592 235 vme_irq_handler(tsi148_bridge, i, vec);
d22b8ed9
MW		 236
237 serviced |= (1 << i);
238 }
239 }
240
241 return serviced;
242}
243
244/*
245 * Top level interrupt handler. Clears appropriate interrupt status bits and
246 * then calls appropriate sub handler(s).
247 */
29848ac9 248static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
d22b8ed9
MW		 249{
250 u32 stat, enable, serviced = 0;
29848ac9
MW		 251 struct vme_bridge *tsi148_bridge;
252 struct tsi148_driver *bridge;
253
254 tsi148_bridge = ptr;
255
256 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 257
258 /* Determine which interrupts are unmasked and set */
29848ac9
MW		 259 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
260 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
d22b8ed9
MW		 261
262 /* Only look at unmasked interrupts */
263 stat &= enable;
264
7946328f 265 if (unlikely(!stat))
d22b8ed9 266 return IRQ_NONE;
d22b8ed9
MW		 267
268 /* Call subhandlers as appropriate */
269 /* DMA irqs */
270 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
29848ac9 271 serviced |= tsi148_DMA_irqhandler(bridge, stat);
d22b8ed9
MW		 272
273 /* Location monitor irqs */
274 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
275 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
29848ac9 276 serviced |= tsi148_LM_irqhandler(bridge, stat);
d22b8ed9
MW		 277
278 /* Mail box irqs */
279 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
280 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
48d9356e 281 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 282
283 /* PCI bus error */
284 if (stat & TSI148_LCSR_INTS_PERRS)
48d9356e 285 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 286
287 /* VME bus error */
288 if (stat & TSI148_LCSR_INTS_VERRS)
29848ac9 289 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 290
291 /* IACK irq */
292 if (stat & TSI148_LCSR_INTS_IACKS)
29848ac9 293 serviced |= tsi148_IACK_irqhandler(bridge);
d22b8ed9
MW		 294
295 /* VME bus irqs */
296 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
297 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
298 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
299 TSI148_LCSR_INTS_IRQ1S))
29848ac9 300 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 301
302 /* Clear serviced interrupts */
29848ac9 303 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 304
305 return IRQ_HANDLED;
306}
307
29848ac9 308static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 309{
310 int result;
311 unsigned int tmp;
312 struct pci_dev *pdev;
29848ac9
MW		 313 struct tsi148_driver *bridge;
314
177581fa 315 pdev = to_pci_dev(tsi148_bridge->parent);
d22b8ed9 316
29848ac9 317 bridge = tsi148_bridge->driver_priv;
d22b8ed9 318
d22b8ed9
MW		 319 result = request_irq(pdev->irq,
320 tsi148_irqhandler,
321 IRQF_SHARED,
29848ac9 322 driver_name, tsi148_bridge);
d22b8ed9 323 if (result) {
48d9356e
MW		 324 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
325 "vector %02X\n", pdev->irq);
d22b8ed9
MW		 326 return result;
327 }
328
329 /* Enable and unmask interrupts */
330 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
331 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
332 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
333 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
334 TSI148_LCSR_INTEO_IACKEO;
335
29848ac9 336 /* This leaves the following interrupts masked.
d22b8ed9
MW		 337 * TSI148_LCSR_INTEO_VIEEO
338 * TSI148_LCSR_INTEO_SYSFLEO
339 * TSI148_LCSR_INTEO_ACFLEO
340 */
341
342 /* Don't enable Location Monitor interrupts here - they will be
343 * enabled when the location monitors are properly configured and
344 * a callback has been attached.
345 * TSI148_LCSR_INTEO_LM0EO
346 * TSI148_LCSR_INTEO_LM1EO
347 * TSI148_LCSR_INTEO_LM2EO
348 * TSI148_LCSR_INTEO_LM3EO
349 */
350
351 /* Don't enable VME interrupts until we add a handler, else the board
352 * will respond to it and we don't want that unless it knows how to
353 * properly deal with it.
354 * TSI148_LCSR_INTEO_IRQ7EO
355 * TSI148_LCSR_INTEO_IRQ6EO
356 * TSI148_LCSR_INTEO_IRQ5EO
357 * TSI148_LCSR_INTEO_IRQ4EO
358 * TSI148_LCSR_INTEO_IRQ3EO
359 * TSI148_LCSR_INTEO_IRQ2EO
360 * TSI148_LCSR_INTEO_IRQ1EO
361 */
362
363 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
364 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
365
366 return 0;
367}
368
a82ad05e
EC		 369static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
370 struct pci_dev *pdev)
d22b8ed9 371{
a82ad05e
EC		 372 struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
373
d22b8ed9 374 /* Turn off interrupts */
29848ac9
MW		 375 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
376 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9
MW		 377
378 /* Clear all interrupts */
29848ac9 379 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 380
381 /* Detach interrupt handler */
a82ad05e 382 free_irq(pdev->irq, tsi148_bridge);
d22b8ed9
MW		 383}
384
385/*
386 * Check to see if an IACk has been received, return true (1) or false (0).
387 */
5ade6c4d 388static int tsi148_iack_received(struct tsi148_driver *bridge)
d22b8ed9
MW		 389{
390 u32 tmp;
391
29848ac9 392 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 393
394 if (tmp & TSI148_LCSR_VICR_IRQS)
395 return 0;
396 else
397 return 1;
398}
399
400/*
c813f592 401 * Configure VME interrupt
d22b8ed9 402 */
5ade6c4d 403static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
29848ac9 404 int state, int sync)
d22b8ed9 405{
75155020 406 struct pci_dev *pdev;
c813f592 407 u32 tmp;
29848ac9
MW		 408 struct tsi148_driver *bridge;
409
410 bridge = tsi148_bridge->driver_priv;
d22b8ed9 411
c813f592
MW		 412 /* We need to do the ordering differently for enabling and disabling */
413 if (state == 0) {
29848ac9 414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 415 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
df455175 417
29848ac9 418 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
df455175 419 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 420 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
75155020 421
c813f592 422 if (sync != 0) {
177581fa 423 pdev = to_pci_dev(tsi148_bridge->parent);
c813f592
MW		 424 synchronize_irq(pdev->irq);
425 }
426 } else {
29848ac9 427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
c813f592 428 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
df455175 430
29848ac9 431 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
c813f592 432 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 433 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
c813f592 434 }
d22b8ed9
MW		 435}
436
437/*
438 * Generate a VME bus interrupt at the requested level & vector. Wait for
439 * interrupt to be acked.
d22b8ed9 440 */
5ade6c4d
EC		 441static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
442 int statid)
d22b8ed9
MW		 443{
444 u32 tmp;
29848ac9
MW		 445 struct tsi148_driver *bridge;
446
447 bridge = tsi148_bridge->driver_priv;
d22b8ed9 448
886953e9 449 mutex_lock(&bridge->vme_int);
d22b8ed9
MW		 450
451 /* Read VICR register */
29848ac9 452 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 453
454 /* Set Status/ID */
455 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
456 (statid & TSI148_LCSR_VICR_STID_M);
29848ac9 457 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 458
459 /* Assert VMEbus IRQ */
460 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
29848ac9 461 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 462
463 /* XXX Consider implementing a timeout? */
29848ac9
MW		 464 wait_event_interruptible(bridge->iack_queue,
465 tsi148_iack_received(bridge));
d22b8ed9 466
886953e9 467 mutex_unlock(&bridge->vme_int);
d22b8ed9
MW		 468
469 return 0;
470}
471
d22b8ed9
MW		 472/*
473 * Initialize a slave window with the requested attributes.
474 */
5ade6c4d 475static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
d22b8ed9 476 unsigned long long vme_base, unsigned long long size,
6af04b06 477 dma_addr_t pci_base, u32 aspace, u32 cycle)
d22b8ed9
MW		 478{
479 unsigned int i, addr = 0, granularity = 0;
480 unsigned int temp_ctl = 0;
481 unsigned int vme_base_low, vme_base_high;
482 unsigned int vme_bound_low, vme_bound_high;
483 unsigned int pci_offset_low, pci_offset_high;
484 unsigned long long vme_bound, pci_offset;
48d9356e 485 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 486 struct tsi148_driver *bridge;
487
48d9356e
MW		 488 tsi148_bridge = image->parent;
489 bridge = tsi148_bridge->driver_priv;
d22b8ed9 490
d22b8ed9
MW		 491 i = image->number;
492
493 switch (aspace) {
494 case VME_A16:
495 granularity = 0x10;
496 addr |= TSI148_LCSR_ITAT_AS_A16;
497 break;
498 case VME_A24:
499 granularity = 0x1000;
500 addr |= TSI148_LCSR_ITAT_AS_A24;
501 break;
502 case VME_A32:
503 granularity = 0x10000;
504 addr |= TSI148_LCSR_ITAT_AS_A32;
505 break;
506 case VME_A64:
507 granularity = 0x10000;
508 addr |= TSI148_LCSR_ITAT_AS_A64;
509 break;
d22b8ed9 510 default:
48d9356e 511 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 512 return -EINVAL;
513 break;
514 }
515
516 /* Convert 64-bit variables to 2x 32-bit variables */
517 reg_split(vme_base, &vme_base_high, &vme_base_low);
518
519 /*
520 * Bound address is a valid address for the window, adjust
521 * accordingly
522 */
523 vme_bound = vme_base + size - granularity;
524 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
525 pci_offset = (unsigned long long)pci_base - vme_base;
526 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
527
528 if (vme_base_low & (granularity - 1)) {
48d9356e 529 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
d22b8ed9
MW		 530 return -EINVAL;
531 }
532 if (vme_bound_low & (granularity - 1)) {
48d9356e 533 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
d22b8ed9
MW		 534 return -EINVAL;
535 }
536 if (pci_offset_low & (granularity - 1)) {
48d9356e
MW		 537 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
538 "alignment\n");
d22b8ed9
MW		 539 return -EINVAL;
540 }
541
d22b8ed9 542 /* Disable while we are mucking around */
29848ac9 543 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 544 TSI148_LCSR_OFFSET_ITAT);
545 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
29848ac9 546 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 547 TSI148_LCSR_OFFSET_ITAT);
548
549 /* Setup mapping */
29848ac9 550 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 551 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 552 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 553 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 554 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 555 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 556 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 557 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 558 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 559 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 560 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 561 TSI148_LCSR_OFFSET_ITOFL);
562
d22b8ed9
MW		 563 /* Setup 2eSST speeds */
564 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
565 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
566 case VME_2eSST160:
567 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
568 break;
569 case VME_2eSST267:
570 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
571 break;
572 case VME_2eSST320:
573 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
574 break;
575 }
576
577 /* Setup cycle types */
578 temp_ctl &= ~(0x1F << 7);
579 if (cycle & VME_BLT)
580 temp_ctl |= TSI148_LCSR_ITAT_BLT;
581 if (cycle & VME_MBLT)
582 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
583 if (cycle & VME_2eVME)
584 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
585 if (cycle & VME_2eSST)
586 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
587 if (cycle & VME_2eSSTB)
588 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
589
590 /* Setup address space */
591 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
592 temp_ctl |= addr;
593
594 temp_ctl &= ~0xF;
595 if (cycle & VME_SUPER)
596 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
597 if (cycle & VME_USER)
598 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
599 if (cycle & VME_PROG)
600 temp_ctl |= TSI148_LCSR_ITAT_PGM;
601 if (cycle & VME_DATA)
602 temp_ctl |= TSI148_LCSR_ITAT_DATA;
603
604 /* Write ctl reg without enable */
29848ac9 605 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 606 TSI148_LCSR_OFFSET_ITAT);
607
608 if (enabled)
609 temp_ctl |= TSI148_LCSR_ITAT_EN;
610
29848ac9 611 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 612 TSI148_LCSR_OFFSET_ITAT);
613
614 return 0;
615}
616
617/*
618 * Get slave window configuration.
d22b8ed9 619 */
5ade6c4d 620static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
d22b8ed9 621 unsigned long long *vme_base, unsigned long long *size,
6af04b06 622 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
d22b8ed9
MW		 623{
624 unsigned int i, granularity = 0, ctl = 0;
625 unsigned int vme_base_low, vme_base_high;
626 unsigned int vme_bound_low, vme_bound_high;
627 unsigned int pci_offset_low, pci_offset_high;
628 unsigned long long vme_bound, pci_offset;
29848ac9 629 struct tsi148_driver *bridge;
d22b8ed9 630
29848ac9 631 bridge = image->parent->driver_priv;
d22b8ed9
MW		 632
633 i = image->number;
634
635 /* Read registers */
29848ac9 636 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 637 TSI148_LCSR_OFFSET_ITAT);
638
29848ac9 639 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 640 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 641 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 642 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 643 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 644 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 645 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 646 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 647 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 648 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 649 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 650 TSI148_LCSR_OFFSET_ITOFL);
651
652 /* Convert 64-bit variables to 2x 32-bit variables */
653 reg_join(vme_base_high, vme_base_low, vme_base);
654 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
655 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
656
098ced8f 657 *pci_base = (dma_addr_t)(*vme_base + pci_offset);
d22b8ed9
MW		 658
659 *enabled = 0;
660 *aspace = 0;
661 *cycle = 0;
662
663 if (ctl & TSI148_LCSR_ITAT_EN)
664 *enabled = 1;
665
666 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
667 granularity = 0x10;
668 *aspace |= VME_A16;
669 }
670 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
671 granularity = 0x1000;
672 *aspace |= VME_A24;
673 }
674 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
675 granularity = 0x10000;
676 *aspace |= VME_A32;
677 }
678 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
679 granularity = 0x10000;
680 *aspace |= VME_A64;
681 }
682
683 /* Need granularity before we set the size */
684 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
685
686
687 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
688 *cycle |= VME_2eSST160;
689 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
690 *cycle |= VME_2eSST267;
691 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
692 *cycle |= VME_2eSST320;
693
694 if (ctl & TSI148_LCSR_ITAT_BLT)
695 *cycle |= VME_BLT;
696 if (ctl & TSI148_LCSR_ITAT_MBLT)
697 *cycle |= VME_MBLT;
698 if (ctl & TSI148_LCSR_ITAT_2eVME)
699 *cycle |= VME_2eVME;
700 if (ctl & TSI148_LCSR_ITAT_2eSST)
701 *cycle |= VME_2eSST;
702 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
703 *cycle |= VME_2eSSTB;
704
705 if (ctl & TSI148_LCSR_ITAT_SUPR)
706 *cycle |= VME_SUPER;
707 if (ctl & TSI148_LCSR_ITAT_NPRIV)
708 *cycle |= VME_USER;
709 if (ctl & TSI148_LCSR_ITAT_PGM)
710 *cycle |= VME_PROG;
711 if (ctl & TSI148_LCSR_ITAT_DATA)
712 *cycle |= VME_DATA;
713
714 return 0;
715}
716
717/*
718 * Allocate and map PCI Resource
719 */
720static int tsi148_alloc_resource(struct vme_master_resource *image,
721 unsigned long long size)
722{
723 unsigned long long existing_size;
724 int retval = 0;
725 struct pci_dev *pdev;
29848ac9
MW		 726 struct vme_bridge *tsi148_bridge;
727
728 tsi148_bridge = image->parent;
d22b8ed9 729
177581fa 730 pdev = to_pci_dev(tsi148_bridge->parent);
d22b8ed9 731
8fafb476
MW		 732 existing_size = (unsigned long long)(image->bus_resource.end -
733 image->bus_resource.start);
d22b8ed9
MW		 734
735 /* If the existing size is OK, return */
59c22904 736 if ((size != 0) && (existing_size == (size - 1)))
d22b8ed9
MW		 737 return 0;
738
739 if (existing_size != 0) {
740 iounmap(image->kern_base);
741 image->kern_base = NULL;
794a8946 742 kfree(image->bus_resource.name);
886953e9 743 release_resource(&image->bus_resource);
6d011dd8 744 memset(&image->bus_resource, 0, sizeof(image->bus_resource));
d22b8ed9
MW		 745 }
746
59c22904 747 /* Exit here if size is zero */
7946328f 748 if (size == 0)
59c22904 749 return 0;
59c22904 750
8fafb476 751 if (image->bus_resource.name == NULL) {
0aa3f139 752 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
8fafb476 753 if (image->bus_resource.name == NULL) {
d22b8ed9
MW		 754 retval = -ENOMEM;
755 goto err_name;
756 }
757 }
758
8fafb476 759 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
d22b8ed9
MW		 760 image->number);
761
8fafb476
MW		 762 image->bus_resource.start = 0;
763 image->bus_resource.end = (unsigned long)size;
764 image->bus_resource.flags = IORESOURCE_MEM;
d22b8ed9
MW		 765
766 retval = pci_bus_alloc_resource(pdev->bus,
da5ae8a9 767 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
d22b8ed9
MW		 768 0, NULL, NULL);
769 if (retval) {
48d9356e
MW		 770 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
771 "resource for window %d size 0x%lx start 0x%lx\n",
d22b8ed9 772 image->number, (unsigned long)size,
8fafb476 773 (unsigned long)image->bus_resource.start);
d22b8ed9
MW		 774 goto err_resource;
775 }
776
777 image->kern_base = ioremap_nocache(
8fafb476 778 image->bus_resource.start, size);
d22b8ed9 779 if (image->kern_base == NULL) {
48d9356e 780 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
d22b8ed9
MW		 781 retval = -ENOMEM;
782 goto err_remap;
783 }
784
785 return 0;
786
d22b8ed9 787err_remap:
886953e9 788 release_resource(&image->bus_resource);
d22b8ed9 789err_resource:
8fafb476 790 kfree(image->bus_resource.name);
6d011dd8 791 memset(&image->bus_resource, 0, sizeof(image->bus_resource));
d22b8ed9
MW		 792err_name:
793 return retval;
794}
795
796/*
797 * Free and unmap PCI Resource
798 */
799static void tsi148_free_resource(struct vme_master_resource *image)
800{
801 iounmap(image->kern_base);
802 image->kern_base = NULL;
886953e9 803 release_resource(&image->bus_resource);
8fafb476 804 kfree(image->bus_resource.name);
6d011dd8 805 memset(&image->bus_resource, 0, sizeof(image->bus_resource));
d22b8ed9
MW		 806}
807
808/*
809 * Set the attributes of an outbound window.
810 */
5ade6c4d 811static int tsi148_master_set(struct vme_master_resource *image, int enabled,
6af04b06
MW		 812 unsigned long long vme_base, unsigned long long size, u32 aspace,
813 u32 cycle, u32 dwidth)
d22b8ed9
MW		 814{
815 int retval = 0;
816 unsigned int i;
817 unsigned int temp_ctl = 0;
818 unsigned int pci_base_low, pci_base_high;
819 unsigned int pci_bound_low, pci_bound_high;
820 unsigned int vme_offset_low, vme_offset_high;
821 unsigned long long pci_bound, vme_offset, pci_base;
48d9356e 822 struct vme_bridge *tsi148_bridge;
29848ac9 823 struct tsi148_driver *bridge;
226572b1
JS		 824 struct pci_bus_region region;
825 struct pci_dev *pdev;
29848ac9 826
48d9356e
MW		 827 tsi148_bridge = image->parent;
828
829 bridge = tsi148_bridge->driver_priv;
d22b8ed9 830
177581fa 831 pdev = to_pci_dev(tsi148_bridge->parent);
226572b1 832
d22b8ed9
MW		 833 /* Verify input data */
834 if (vme_base & 0xFFFF) {
48d9356e
MW		 835 dev_err(tsi148_bridge->parent, "Invalid VME Window "
836 "alignment\n");
d22b8ed9
MW		 837 retval = -EINVAL;
838 goto err_window;
839 }
59c22904
MW		 840
841 if ((size == 0) && (enabled != 0)) {
48d9356e
MW		 842 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
843 "enabled windows\n");
d22b8ed9
MW		 844 retval = -EINVAL;
845 goto err_window;
846 }
847
886953e9 848 spin_lock(&image->lock);
d22b8ed9
MW		 849
850 /* Let's allocate the resource here rather than further up the stack as
25985edc 851 * it avoids pushing loads of bus dependent stuff up the stack. If size
59c22904 852 * is zero, any existing resource will be freed.
d22b8ed9
MW		 853 */
854 retval = tsi148_alloc_resource(image, size);
855 if (retval) {
886953e9 856 spin_unlock(&image->lock);
48d9356e 857 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
59c22904 858 "resource\n");
d22b8ed9
MW		 859 goto err_res;
860 }
861
59c22904
MW		 862 if (size == 0) {
863 pci_base = 0;
864 pci_bound = 0;
865 vme_offset = 0;
866 } else {
226572b1
JS		 867 pcibios_resource_to_bus(pdev->bus, &region,
868 &image->bus_resource);
869 pci_base = region.start;
59c22904
MW		 870
871 /*
872 * Bound address is a valid address for the window, adjust
873 * according to window granularity.
874 */
875 pci_bound = pci_base + (size - 0x10000);
876 vme_offset = vme_base - pci_base;
877 }
d22b8ed9
MW		 878
879 /* Convert 64-bit variables to 2x 32-bit variables */
880 reg_split(pci_base, &pci_base_high, &pci_base_low);
881 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
882 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
883
884 if (pci_base_low & 0xFFFF) {
886953e9 885 spin_unlock(&image->lock);
48d9356e 886 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
d22b8ed9
MW		 887 retval = -EINVAL;
888 goto err_gran;
889 }
890 if (pci_bound_low & 0xFFFF) {
886953e9 891 spin_unlock(&image->lock);
48d9356e 892 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
d22b8ed9
MW		 893 retval = -EINVAL;
894 goto err_gran;
895 }
896 if (vme_offset_low & 0xFFFF) {
886953e9 897 spin_unlock(&image->lock);
48d9356e
MW		 898 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
899 "alignment\n");
d22b8ed9
MW		 900 retval = -EINVAL;
901 goto err_gran;
902 }
903
904 i = image->number;
905
906 /* Disable while we are mucking around */
29848ac9 907 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 908 TSI148_LCSR_OFFSET_OTAT);
909 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
29848ac9 910 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 911 TSI148_LCSR_OFFSET_OTAT);
912
d22b8ed9
MW		 913 /* Setup 2eSST speeds */
914 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
915 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
916 case VME_2eSST160:
917 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
918 break;
919 case VME_2eSST267:
920 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
921 break;
922 case VME_2eSST320:
923 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
924 break;
925 }
926
927 /* Setup cycle types */
928 if (cycle & VME_BLT) {
929 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
930 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
931 }
932 if (cycle & VME_MBLT) {
933 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
934 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
935 }
936 if (cycle & VME_2eVME) {
937 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
938 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
939 }
940 if (cycle & VME_2eSST) {
941 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
942 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
943 }
944 if (cycle & VME_2eSSTB) {
48d9356e
MW		 945 dev_warn(tsi148_bridge->parent, "Currently not setting "
946 "Broadcast Select Registers\n");
d22b8ed9
MW		 947 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
948 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
949 }
950
951 /* Setup data width */
952 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
953 switch (dwidth) {
954 case VME_D16:
955 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
956 break;
957 case VME_D32:
958 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
959 break;
960 default:
886953e9 961 spin_unlock(&image->lock);
48d9356e 962 dev_err(tsi148_bridge->parent, "Invalid data width\n");
d22b8ed9
MW		 963 retval = -EINVAL;
964 goto err_dwidth;
965 }
966
967 /* Setup address space */
968 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
969 switch (aspace) {
970 case VME_A16:
971 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
972 break;
973 case VME_A24:
974 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
975 break;
976 case VME_A32:
977 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
978 break;
979 case VME_A64:
980 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
981 break;
982 case VME_CRCSR:
983 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
984 break;
985 case VME_USER1:
986 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
987 break;
988 case VME_USER2:
989 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
990 break;
991 case VME_USER3:
992 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
993 break;
994 case VME_USER4:
995 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
996 break;
997 default:
886953e9 998 spin_unlock(&image->lock);
48d9356e 999 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1000 retval = -EINVAL;
1001 goto err_aspace;
1002 break;
1003 }
1004
1005 temp_ctl &= ~(3<<4);
1006 if (cycle & VME_SUPER)
1007 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1008 if (cycle & VME_PROG)
1009 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1010
1011 /* Setup mapping */
29848ac9 1012 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1013 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1014 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1015 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1016 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1017 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1018 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1019 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1020 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1021 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1022 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1023 TSI148_LCSR_OFFSET_OTOFL);
1024
d22b8ed9 1025 /* Write ctl reg without enable */
29848ac9 1026 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1027 TSI148_LCSR_OFFSET_OTAT);
1028
1029 if (enabled)
1030 temp_ctl |= TSI148_LCSR_OTAT_EN;
1031
29848ac9 1032 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1033 TSI148_LCSR_OFFSET_OTAT);
1034
886953e9 1035 spin_unlock(&image->lock);
d22b8ed9
MW		 1036 return 0;
1037
1038err_aspace:
1039err_dwidth:
1040err_gran:
1041 tsi148_free_resource(image);
1042err_res:
1043err_window:
1044 return retval;
1045
1046}
1047
1048/*
1049 * Set the attributes of an outbound window.
1050 *
1051 * XXX Not parsing prefetch information.
1052 */
5ade6c4d 1053static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
6af04b06
MW		 1054 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1055 u32 *cycle, u32 *dwidth)
d22b8ed9
MW		 1056{
1057 unsigned int i, ctl;
1058 unsigned int pci_base_low, pci_base_high;
1059 unsigned int pci_bound_low, pci_bound_high;
1060 unsigned int vme_offset_low, vme_offset_high;
1061
1062 unsigned long long pci_base, pci_bound, vme_offset;
29848ac9
MW		 1063 struct tsi148_driver *bridge;
1064
1065 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1066
1067 i = image->number;
1068
29848ac9 1069 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1070 TSI148_LCSR_OFFSET_OTAT);
1071
29848ac9 1072 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1073 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1074 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1075 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1076 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1077 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1078 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1079 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1080 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1081 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1082 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1083 TSI148_LCSR_OFFSET_OTOFL);
1084
1085 /* Convert 64-bit variables to 2x 32-bit variables */
1086 reg_join(pci_base_high, pci_base_low, &pci_base);
1087 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1088 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1089
1090 *vme_base = pci_base + vme_offset;
1091 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1092
1093 *enabled = 0;
1094 *aspace = 0;
1095 *cycle = 0;
1096 *dwidth = 0;
1097
1098 if (ctl & TSI148_LCSR_OTAT_EN)
1099 *enabled = 1;
1100
1101 /* Setup address space */
1102 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1103 *aspace |= VME_A16;
1104 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1105 *aspace |= VME_A24;
1106 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1107 *aspace |= VME_A32;
1108 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1109 *aspace |= VME_A64;
1110 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1111 *aspace |= VME_CRCSR;
1112 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1113 *aspace |= VME_USER1;
1114 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1115 *aspace |= VME_USER2;
1116 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1117 *aspace |= VME_USER3;
1118 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1119 *aspace |= VME_USER4;
1120
1121 /* Setup 2eSST speeds */
1122 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1123 *cycle |= VME_2eSST160;
1124 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1125 *cycle |= VME_2eSST267;
1126 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1127 *cycle |= VME_2eSST320;
1128
1129 /* Setup cycle types */
7946328f 1130 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
d22b8ed9 1131 *cycle |= VME_SCT;
7946328f 1132 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
d22b8ed9 1133 *cycle |= VME_BLT;
7946328f 1134 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
d22b8ed9 1135 *cycle |= VME_MBLT;
7946328f 1136 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
d22b8ed9 1137 *cycle |= VME_2eVME;
7946328f 1138 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
d22b8ed9 1139 *cycle |= VME_2eSST;
7946328f 1140 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
d22b8ed9
MW		 1141 *cycle |= VME_2eSSTB;
1142
1143 if (ctl & TSI148_LCSR_OTAT_SUP)
1144 *cycle |= VME_SUPER;
1145 else
1146 *cycle |= VME_USER;
1147
1148 if (ctl & TSI148_LCSR_OTAT_PGM)
1149 *cycle |= VME_PROG;
1150 else
1151 *cycle |= VME_DATA;
1152
1153 /* Setup data width */
1154 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1155 *dwidth = VME_D16;
1156 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1157 *dwidth = VME_D32;
1158
1159 return 0;
1160}
1161
1162
5ade6c4d 1163static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
6af04b06
MW		 1164 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1165 u32 *cycle, u32 *dwidth)
d22b8ed9
MW		 1166{
1167 int retval;
1168
886953e9 1169 spin_lock(&image->lock);
d22b8ed9
MW		 1170
1171 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1172 cycle, dwidth);
1173
886953e9 1174 spin_unlock(&image->lock);
d22b8ed9
MW		 1175
1176 return retval;
1177}
1178
5ade6c4d 1179static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
d22b8ed9
MW		 1180 size_t count, loff_t offset)
1181{
1182 int retval, enabled;
1183 unsigned long long vme_base, size;
6af04b06 1184 u32 aspace, cycle, dwidth;
d3337eb1 1185 struct vme_error_handler *handler = NULL;
29848ac9 1186 struct vme_bridge *tsi148_bridge;
4e8764d9 1187 void __iomem *addr = image->kern_base + offset;
363e2e6f
MW		 1188 unsigned int done = 0;
1189 unsigned int count32;
29848ac9
MW		 1190
1191 tsi148_bridge = image->parent;
d22b8ed9 1192
886953e9 1193 spin_lock(&image->lock);
d22b8ed9 1194
0b049662
DK		 1195 if (err_chk) {
1196 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1197 &cycle, &dwidth);
1198 handler = vme_register_error_handler(tsi148_bridge, aspace,
1199 vme_base + offset, count);
1200 if (!handler) {
1201 spin_unlock(&image->lock);
1202 return -ENOMEM;
1203 }
1204 }
1205
363e2e6f 1206 /* The following code handles VME address alignment. We cannot use
a2a720e1
MW		 1207 * memcpy_xxx here because it may cut data transfers in to 8-bit
1208 * cycles when D16 or D32 cycles are required on the VME bus.
363e2e6f
MW		 1209 * On the other hand, the bridge itself assures that the maximum data
1210 * cycle configured for the transfer is used and splits it
1211 * automatically for non-aligned addresses, so we don't want the
1212 * overhead of needlessly forcing small transfers for the entire cycle.
1213 */
1214 if ((uintptr_t)addr & 0x1) {
1215 *(u8 *)buf = ioread8(addr);
1216 done += 1;
1217 if (done == count)
1218 goto out;
1219 }
f0342e66 1220 if ((uintptr_t)(addr + done) & 0x2) {
363e2e6f
MW		 1221 if ((count - done) < 2) {
1222 *(u8 *)(buf + done) = ioread8(addr + done);
1223 done += 1;
1224 goto out;
1225 } else {
1226 *(u16 *)(buf + done) = ioread16(addr + done);
1227 done += 2;
1228 }
1229 }
1230
1231 count32 = (count - done) & ~0x3;
a2a720e1
MW		 1232 while (done < count32) {
1233 *(u32 *)(buf + done) = ioread32(addr + done);
1234 done += 4;
363e2e6f
MW		 1235 }
1236
1237 if ((count - done) & 0x2) {
1238 *(u16 *)(buf + done) = ioread16(addr + done);
1239 done += 2;
1240 }
1241 if ((count - done) & 0x1) {
1242 *(u8 *)(buf + done) = ioread8(addr + done);
1243 done += 1;
1244 }
1245
1246out:
d22b8ed9
MW		 1247 retval = count;
1248
0b049662
DK		 1249 if (err_chk) {
1250 if (handler->num_errors) {
1251 dev_err(image->parent->parent,
1252 "First VME read error detected an at address 0x%llx\n",
1253 handler->first_error);
1254 retval = handler->first_error - (vme_base + offset);
1255 }
1256 vme_unregister_error_handler(handler);
d22b8ed9
MW		 1257 }
1258
886953e9 1259 spin_unlock(&image->lock);
d22b8ed9
MW		 1260
1261 return retval;
1262}
1263
1264
5ade6c4d 1265static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
d22b8ed9
MW		 1266 size_t count, loff_t offset)
1267{
1268 int retval = 0, enabled;
1269 unsigned long long vme_base, size;
6af04b06 1270 u32 aspace, cycle, dwidth;
4e8764d9 1271 void __iomem *addr = image->kern_base + offset;
363e2e6f
MW		 1272 unsigned int done = 0;
1273 unsigned int count32;
d22b8ed9 1274
d3337eb1 1275 struct vme_error_handler *handler = NULL;
29848ac9
MW		 1276 struct vme_bridge *tsi148_bridge;
1277 struct tsi148_driver *bridge;
1278
1279 tsi148_bridge = image->parent;
1280
1281 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1282
886953e9 1283 spin_lock(&image->lock);
d22b8ed9 1284
0b049662
DK		 1285 if (err_chk) {
1286 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1287 &cycle, &dwidth);
1288 handler = vme_register_error_handler(tsi148_bridge, aspace,
1289 vme_base + offset, count);
1290 if (!handler) {
1291 spin_unlock(&image->lock);
1292 return -ENOMEM;
1293 }
1294 }
1295
363e2e6f 1296 /* Here we apply for the same strategy we do in master_read
a2a720e1 1297 * function in order to assure the correct cycles.
363e2e6f
MW		 1298 */
1299 if ((uintptr_t)addr & 0x1) {
1300 iowrite8(*(u8 *)buf, addr);
1301 done += 1;
1302 if (done == count)
1303 goto out;
1304 }
f0342e66 1305 if ((uintptr_t)(addr + done) & 0x2) {
363e2e6f
MW		 1306 if ((count - done) < 2) {
1307 iowrite8(*(u8 *)(buf + done), addr + done);
1308 done += 1;
1309 goto out;
1310 } else {
1311 iowrite16(*(u16 *)(buf + done), addr + done);
1312 done += 2;
1313 }
1314 }
1315
1316 count32 = (count - done) & ~0x3;
a2a720e1
MW		 1317 while (done < count32) {
1318 iowrite32(*(u32 *)(buf + done), addr + done);
1319 done += 4;
363e2e6f
MW		 1320 }
1321
1322 if ((count - done) & 0x2) {
1323 iowrite16(*(u16 *)(buf + done), addr + done);
1324 done += 2;
1325 }
1326 if ((count - done) & 0x1) {
1327 iowrite8(*(u8 *)(buf + done), addr + done);
1328 done += 1;
1329 }
1330
1331out:
d22b8ed9
MW		 1332 retval = count;
1333
1334 /*
1335 * Writes are posted. We need to do a read on the VME bus to flush out
25985edc 1336 * all of the writes before we check for errors. We can't guarantee
d22b8ed9
MW		 1337 * that reading the data we have just written is safe. It is believed
1338 * that there isn't any read, write re-ordering, so we can read any
1339 * location in VME space, so lets read the Device ID from the tsi148's
1340 * own registers as mapped into CR/CSR space.
1341 *
1342 * We check for saved errors in the written address range/space.
1343 */
1344
0b049662
DK		 1345 if (err_chk) {
1346 ioread16(bridge->flush_image->kern_base + 0x7F000);
d22b8ed9 1347
0b049662
DK		 1348 if (handler->num_errors) {
1349 dev_warn(tsi148_bridge->parent,
1350 "First VME write error detected an at address 0x%llx\n",
1351 handler->first_error);
1352 retval = handler->first_error - (vme_base + offset);
1353 }
1354 vme_unregister_error_handler(handler);
d22b8ed9
MW		 1355 }
1356
886953e9 1357 spin_unlock(&image->lock);
d22b8ed9
MW		 1358
1359 return retval;
1360}
1361
1362/*
1363 * Perform an RMW cycle on the VME bus.
1364 *
1365 * Requires a previously configured master window, returns final value.
1366 */
5ade6c4d 1367static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
d22b8ed9
MW		 1368 unsigned int mask, unsigned int compare, unsigned int swap,
1369 loff_t offset)
1370{
1371 unsigned long long pci_addr;
1372 unsigned int pci_addr_high, pci_addr_low;
1373 u32 tmp, result;
1374 int i;
29848ac9 1375 struct tsi148_driver *bridge;
d22b8ed9 1376
29848ac9 1377 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1378
1379 /* Find the PCI address that maps to the desired VME address */
1380 i = image->number;
1381
1382 /* Locking as we can only do one of these at a time */
886953e9 1383 mutex_lock(&bridge->vme_rmw);
d22b8ed9
MW		 1384
1385 /* Lock image */
886953e9 1386 spin_lock(&image->lock);
d22b8ed9 1387
29848ac9 1388 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1389 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1390 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1391 TSI148_LCSR_OFFSET_OTSAL);
1392
1393 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1394 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1395
1396 /* Configure registers */
29848ac9
MW		 1397 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1398 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1399 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1400 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1401 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
d22b8ed9
MW		 1402
1403 /* Enable RMW */
29848ac9 1404 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1405 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1406 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9
MW		 1407
1408 /* Kick process off with a read to the required address. */
1409 result = ioread32be(image->kern_base + offset);
1410
1411 /* Disable RMW */
29848ac9 1412 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1413 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1414 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1415
886953e9 1416 spin_unlock(&image->lock);
d22b8ed9 1417
886953e9 1418 mutex_unlock(&bridge->vme_rmw);
d22b8ed9
MW		 1419
1420 return result;
1421}
1422
ac1a4f2c 1423static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
6af04b06 1424 u32 aspace, u32 cycle, u32 dwidth)
d22b8ed9 1425{
ac1a4f2c
MW		 1426 u32 val;
1427
1428 val = be32_to_cpu(*attr);
1429
d22b8ed9
MW		 1430 /* Setup 2eSST speeds */
1431 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1432 case VME_2eSST160:
ac1a4f2c 1433 val |= TSI148_LCSR_DSAT_2eSSTM_160;
d22b8ed9
MW		 1434 break;
1435 case VME_2eSST267:
ac1a4f2c 1436 val |= TSI148_LCSR_DSAT_2eSSTM_267;
d22b8ed9
MW		 1437 break;
1438 case VME_2eSST320:
ac1a4f2c 1439 val |= TSI148_LCSR_DSAT_2eSSTM_320;
d22b8ed9
MW		 1440 break;
1441 }
1442
1443 /* Setup cycle types */
7946328f 1444 if (cycle & VME_SCT)
ac1a4f2c 1445 val |= TSI148_LCSR_DSAT_TM_SCT;
7946328f
MW		 1446
1447 if (cycle & VME_BLT)
ac1a4f2c 1448 val |= TSI148_LCSR_DSAT_TM_BLT;
7946328f
MW		 1449
1450 if (cycle & VME_MBLT)
ac1a4f2c 1451 val |= TSI148_LCSR_DSAT_TM_MBLT;
7946328f
MW		 1452
1453 if (cycle & VME_2eVME)
ac1a4f2c 1454 val |= TSI148_LCSR_DSAT_TM_2eVME;
7946328f
MW		 1455
1456 if (cycle & VME_2eSST)
ac1a4f2c 1457 val |= TSI148_LCSR_DSAT_TM_2eSST;
7946328f 1458
d22b8ed9 1459 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1460 dev_err(dev, "Currently not setting Broadcast Select "
1461 "Registers\n");
ac1a4f2c 1462 val |= TSI148_LCSR_DSAT_TM_2eSSTB;
d22b8ed9
MW		 1463 }
1464
1465 /* Setup data width */
1466 switch (dwidth) {
1467 case VME_D16:
ac1a4f2c 1468 val |= TSI148_LCSR_DSAT_DBW_16;
d22b8ed9
MW		 1469 break;
1470 case VME_D32:
ac1a4f2c 1471 val |= TSI148_LCSR_DSAT_DBW_32;
d22b8ed9
MW		 1472 break;
1473 default:
48d9356e 1474 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1475 return -EINVAL;
1476 }
1477
1478 /* Setup address space */
1479 switch (aspace) {
1480 case VME_A16:
ac1a4f2c 1481 val |= TSI148_LCSR_DSAT_AMODE_A16;
d22b8ed9
MW		 1482 break;
1483 case VME_A24:
ac1a4f2c 1484 val |= TSI148_LCSR_DSAT_AMODE_A24;
d22b8ed9
MW		 1485 break;
1486 case VME_A32:
ac1a4f2c 1487 val |= TSI148_LCSR_DSAT_AMODE_A32;
d22b8ed9
MW		 1488 break;
1489 case VME_A64:
ac1a4f2c 1490 val |= TSI148_LCSR_DSAT_AMODE_A64;
d22b8ed9
MW		 1491 break;
1492 case VME_CRCSR:
ac1a4f2c 1493 val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
d22b8ed9
MW		 1494 break;
1495 case VME_USER1:
ac1a4f2c 1496 val |= TSI148_LCSR_DSAT_AMODE_USER1;
d22b8ed9
MW		 1497 break;
1498 case VME_USER2:
ac1a4f2c 1499 val |= TSI148_LCSR_DSAT_AMODE_USER2;
d22b8ed9
MW		 1500 break;
1501 case VME_USER3:
ac1a4f2c 1502 val |= TSI148_LCSR_DSAT_AMODE_USER3;
d22b8ed9
MW		 1503 break;
1504 case VME_USER4:
ac1a4f2c 1505 val |= TSI148_LCSR_DSAT_AMODE_USER4;
d22b8ed9
MW		 1506 break;
1507 default:
48d9356e 1508 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1509 return -EINVAL;
1510 break;
1511 }
1512
1513 if (cycle & VME_SUPER)
ac1a4f2c 1514 val |= TSI148_LCSR_DSAT_SUP;
d22b8ed9 1515 if (cycle & VME_PROG)
ac1a4f2c
MW		 1516 val |= TSI148_LCSR_DSAT_PGM;
1517
1518 *attr = cpu_to_be32(val);
d22b8ed9
MW		 1519
1520 return 0;
1521}
1522
ac1a4f2c 1523static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
6af04b06 1524 u32 aspace, u32 cycle, u32 dwidth)
d22b8ed9 1525{
ac1a4f2c
MW		 1526 u32 val;
1527
1528 val = be32_to_cpu(*attr);
1529
d22b8ed9
MW		 1530 /* Setup 2eSST speeds */
1531 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1532 case VME_2eSST160:
ac1a4f2c 1533 val |= TSI148_LCSR_DDAT_2eSSTM_160;
d22b8ed9
MW		 1534 break;
1535 case VME_2eSST267:
ac1a4f2c 1536 val |= TSI148_LCSR_DDAT_2eSSTM_267;
d22b8ed9
MW		 1537 break;
1538 case VME_2eSST320:
ac1a4f2c 1539 val |= TSI148_LCSR_DDAT_2eSSTM_320;
d22b8ed9
MW		 1540 break;
1541 }
1542
1543 /* Setup cycle types */
7946328f 1544 if (cycle & VME_SCT)
ac1a4f2c 1545 val |= TSI148_LCSR_DDAT_TM_SCT;
7946328f
MW		 1546
1547 if (cycle & VME_BLT)
ac1a4f2c 1548 val |= TSI148_LCSR_DDAT_TM_BLT;
7946328f
MW		 1549
1550 if (cycle & VME_MBLT)
ac1a4f2c 1551 val |= TSI148_LCSR_DDAT_TM_MBLT;
7946328f
MW		 1552
1553 if (cycle & VME_2eVME)
ac1a4f2c 1554 val |= TSI148_LCSR_DDAT_TM_2eVME;
7946328f
MW		 1555
1556 if (cycle & VME_2eSST)
ac1a4f2c 1557 val |= TSI148_LCSR_DDAT_TM_2eSST;
7946328f 1558
d22b8ed9 1559 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1560 dev_err(dev, "Currently not setting Broadcast Select "
1561 "Registers\n");
ac1a4f2c 1562 val |= TSI148_LCSR_DDAT_TM_2eSSTB;
d22b8ed9
MW		 1563 }
1564
1565 /* Setup data width */
1566 switch (dwidth) {
1567 case VME_D16:
ac1a4f2c 1568 val |= TSI148_LCSR_DDAT_DBW_16;
d22b8ed9
MW		 1569 break;
1570 case VME_D32:
ac1a4f2c 1571 val |= TSI148_LCSR_DDAT_DBW_32;
d22b8ed9
MW		 1572 break;
1573 default:
48d9356e 1574 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1575 return -EINVAL;
1576 }
1577
1578 /* Setup address space */
1579 switch (aspace) {
1580 case VME_A16:
ac1a4f2c 1581 val |= TSI148_LCSR_DDAT_AMODE_A16;
d22b8ed9
MW		 1582 break;
1583 case VME_A24:
ac1a4f2c 1584 val |= TSI148_LCSR_DDAT_AMODE_A24;
d22b8ed9
MW		 1585 break;
1586 case VME_A32:
ac1a4f2c 1587 val |= TSI148_LCSR_DDAT_AMODE_A32;
d22b8ed9
MW		 1588 break;
1589 case VME_A64:
ac1a4f2c 1590 val |= TSI148_LCSR_DDAT_AMODE_A64;
d22b8ed9
MW		 1591 break;
1592 case VME_CRCSR:
ac1a4f2c 1593 val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
d22b8ed9
MW		 1594 break;
1595 case VME_USER1:
ac1a4f2c 1596 val |= TSI148_LCSR_DDAT_AMODE_USER1;
d22b8ed9
MW		 1597 break;
1598 case VME_USER2:
ac1a4f2c 1599 val |= TSI148_LCSR_DDAT_AMODE_USER2;
d22b8ed9
MW		 1600 break;
1601 case VME_USER3:
ac1a4f2c 1602 val |= TSI148_LCSR_DDAT_AMODE_USER3;
d22b8ed9
MW		 1603 break;
1604 case VME_USER4:
ac1a4f2c 1605 val |= TSI148_LCSR_DDAT_AMODE_USER4;
d22b8ed9
MW		 1606 break;
1607 default:
48d9356e 1608 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1609 return -EINVAL;
1610 break;
1611 }
1612
1613 if (cycle & VME_SUPER)
ac1a4f2c 1614 val |= TSI148_LCSR_DDAT_SUP;
d22b8ed9 1615 if (cycle & VME_PROG)
ac1a4f2c
MW		 1616 val |= TSI148_LCSR_DDAT_PGM;
1617
1618 *attr = cpu_to_be32(val);
d22b8ed9
MW		 1619
1620 return 0;
1621}
1622
1623/*
1624 * Add a link list descriptor to the list
ac1a4f2c
MW		 1625 *
1626 * Note: DMA engine expects the DMA descriptor to be big endian.
d22b8ed9 1627 */
5ade6c4d
EC		 1628static int tsi148_dma_list_add(struct vme_dma_list *list,
1629 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
d22b8ed9
MW		 1630{
1631 struct tsi148_dma_entry *entry, *prev;
ac1a4f2c 1632 u32 address_high, address_low, val;
d22b8ed9
MW		 1633 struct vme_dma_pattern *pattern_attr;
1634 struct vme_dma_pci *pci_attr;
1635 struct vme_dma_vme *vme_attr;
d22b8ed9 1636 int retval = 0;
48d9356e
MW		 1637 struct vme_bridge *tsi148_bridge;
1638
1639 tsi148_bridge = list->parent->parent;
d22b8ed9 1640
bb9ea89e 1641 /* Descriptor must be aligned on 64-bit boundaries */
6d011dd8 1642 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
d22b8ed9 1643 if (entry == NULL) {
d22b8ed9
MW		 1644 retval = -ENOMEM;
1645 goto err_mem;
1646 }
1647
1648 /* Test descriptor alignment */
886953e9 1649 if ((unsigned long)&entry->descriptor & 0x7) {
48d9356e
MW		 1650 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1651 "byte boundary as required: %p\n",
886953e9 1652 &entry->descriptor);
d22b8ed9
MW		 1653 retval = -EINVAL;
1654 goto err_align;
1655 }
1656
1657 /* Given we are going to fill out the structure, we probably don't
1658 * need to zero it, but better safe than sorry for now.
1659 */
6d011dd8 1660 memset(&entry->descriptor, 0, sizeof(entry->descriptor));
d22b8ed9
MW		 1661
1662 /* Fill out source part */
1663 switch (src->type) {
1664 case VME_DMA_PATTERN:
c4d82fbb 1665 pattern_attr = src->private;
d22b8ed9 1666
ac1a4f2c
MW		 1667 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
1668
1669 val = TSI148_LCSR_DSAT_TYP_PAT;
1670
d22b8ed9 1671 /* Default behaviour is 32 bit pattern */
7946328f 1672 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
ac1a4f2c 1673 val |= TSI148_LCSR_DSAT_PSZ;
7946328f 1674
d22b8ed9 1675 /* It seems that the default behaviour is to increment */
7946328f 1676 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
ac1a4f2c
MW		 1677 val |= TSI148_LCSR_DSAT_NIN;
1678 entry->descriptor.dsat = cpu_to_be32(val);
d22b8ed9
MW		 1679 break;
1680 case VME_DMA_PCI:
c4d82fbb 1681 pci_attr = src->private;
d22b8ed9
MW		 1682
1683 reg_split((unsigned long long)pci_attr->address, &address_high,
1684 &address_low);
ac1a4f2c
MW		 1685 entry->descriptor.dsau = cpu_to_be32(address_high);
1686 entry->descriptor.dsal = cpu_to_be32(address_low);
1687 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
d22b8ed9
MW		 1688 break;
1689 case VME_DMA_VME:
c4d82fbb 1690 vme_attr = src->private;
d22b8ed9
MW		 1691
1692 reg_split((unsigned long long)vme_attr->address, &address_high,
1693 &address_low);
ac1a4f2c
MW		 1694 entry->descriptor.dsau = cpu_to_be32(address_high);
1695 entry->descriptor.dsal = cpu_to_be32(address_low);
1696 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
d22b8ed9
MW		 1697
1698 retval = tsi148_dma_set_vme_src_attributes(
886953e9 1699 tsi148_bridge->parent, &entry->descriptor.dsat,
48d9356e 1700 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1701 if (retval < 0)
d22b8ed9
MW		 1702 goto err_source;
1703 break;
1704 default:
48d9356e 1705 dev_err(tsi148_bridge->parent, "Invalid source type\n");
d22b8ed9
MW		 1706 retval = -EINVAL;
1707 goto err_source;
1708 break;
1709 }
1710
1711 /* Assume last link - this will be over-written by adding another */
ac1a4f2c
MW		 1712 entry->descriptor.dnlau = cpu_to_be32(0);
1713 entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
d22b8ed9
MW		 1714
1715 /* Fill out destination part */
1716 switch (dest->type) {
1717 case VME_DMA_PCI:
c4d82fbb 1718 pci_attr = dest->private;
d22b8ed9
MW		 1719
1720 reg_split((unsigned long long)pci_attr->address, &address_high,
1721 &address_low);
ac1a4f2c
MW		 1722 entry->descriptor.ddau = cpu_to_be32(address_high);
1723 entry->descriptor.ddal = cpu_to_be32(address_low);
1724 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
d22b8ed9
MW		 1725 break;
1726 case VME_DMA_VME:
c4d82fbb 1727 vme_attr = dest->private;
d22b8ed9
MW		 1728
1729 reg_split((unsigned long long)vme_attr->address, &address_high,
1730 &address_low);
ac1a4f2c
MW		 1731 entry->descriptor.ddau = cpu_to_be32(address_high);
1732 entry->descriptor.ddal = cpu_to_be32(address_low);
1733 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
d22b8ed9
MW		 1734
1735 retval = tsi148_dma_set_vme_dest_attributes(
886953e9 1736 tsi148_bridge->parent, &entry->descriptor.ddat,
48d9356e 1737 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1738 if (retval < 0)
d22b8ed9
MW		 1739 goto err_dest;
1740 break;
1741 default:
48d9356e 1742 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
d22b8ed9
MW		 1743 retval = -EINVAL;
1744 goto err_dest;
1745 break;
1746 }
1747
1748 /* Fill out count */
ac1a4f2c 1749 entry->descriptor.dcnt = cpu_to_be32((u32)count);
d22b8ed9
MW		 1750
1751 /* Add to list */
886953e9 1752 list_add_tail(&entry->list, &list->entries);
d22b8ed9 1753
b2383c90 1754 entry->dma_handle = dma_map_single(tsi148_bridge->parent,
6d011dd8
ME		 1755 &entry->descriptor,
1756 sizeof(entry->descriptor),
1757 DMA_TO_DEVICE);
b2383c90
DK		 1758 if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) {
1759 dev_err(tsi148_bridge->parent, "DMA mapping error\n");
1760 retval = -EINVAL;
1761 goto err_dma;
1762 }
1763
d22b8ed9 1764 /* Fill out previous descriptors "Next Address" */
886953e9 1765 if (entry->list.prev != &list->entries) {
ac1a4f2c
MW		 1766 reg_split((unsigned long long)entry->dma_handle, &address_high,
1767 &address_low);
b2383c90
DK		 1768 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1769 list);
f656eaee
DK		 1770 prev->descriptor.dnlau = cpu_to_be32(address_high);
1771 prev->descriptor.dnlal = cpu_to_be32(address_low);
ac1a4f2c 1772
d22b8ed9
MW		 1773 }
1774
1775 return 0;
1776
b2383c90 1777err_dma:
d22b8ed9
MW		 1778err_dest:
1779err_source:
1780err_align:
1781 kfree(entry);
1782err_mem:
1783 return retval;
1784}
1785
1786/*
1787 * Check to see if the provided DMA channel is busy.
1788 */
29848ac9 1789static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
d22b8ed9
MW		 1790{
1791 u32 tmp;
29848ac9
MW		 1792 struct tsi148_driver *bridge;
1793
1794 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1795
29848ac9 1796 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1797 TSI148_LCSR_OFFSET_DSTA);
1798
1799 if (tmp & TSI148_LCSR_DSTA_BSY)
1800 return 0;
1801 else
1802 return 1;
1803
1804}
1805
1806/*
1807 * Execute a previously generated link list
1808 *
1809 * XXX Need to provide control register configuration.
1810 */
5ade6c4d 1811static int tsi148_dma_list_exec(struct vme_dma_list *list)
d22b8ed9
MW		 1812{
1813 struct vme_dma_resource *ctrlr;
75c66b6d 1814 int channel, retval;
d22b8ed9 1815 struct tsi148_dma_entry *entry;
d22b8ed9
MW		 1816 u32 bus_addr_high, bus_addr_low;
1817 u32 val, dctlreg = 0;
48d9356e 1818 struct vme_bridge *tsi148_bridge;
29848ac9 1819 struct tsi148_driver *bridge;
d22b8ed9
MW		 1820
1821 ctrlr = list->parent;
1822
48d9356e
MW		 1823 tsi148_bridge = ctrlr->parent;
1824
1825 bridge = tsi148_bridge->driver_priv;
29848ac9 1826
886953e9 1827 mutex_lock(&ctrlr->mtx);
d22b8ed9
MW		 1828
1829 channel = ctrlr->number;
1830
886953e9 1831 if (!list_empty(&ctrlr->running)) {
d22b8ed9
MW		 1832 /*
1833 * XXX We have an active DMA transfer and currently haven't
1834 * sorted out the mechanism for "pending" DMA transfers.
1835 * Return busy.
1836 */
1837 /* Need to add to pending here */
886953e9 1838 mutex_unlock(&ctrlr->mtx);
d22b8ed9
MW		 1839 return -EBUSY;
1840 } else {
886953e9 1841 list_add(&list->list, &ctrlr->running);
d22b8ed9 1842 }
d22b8ed9
MW		 1843
1844 /* Get first bus address and write into registers */
886953e9 1845 entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
d22b8ed9
MW		 1846 list);
1847
886953e9 1848 mutex_unlock(&ctrlr->mtx);
d22b8ed9 1849
3abc48ae 1850 reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
d22b8ed9 1851
29848ac9 1852 iowrite32be(bus_addr_high, bridge->base +
d22b8ed9 1853 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
29848ac9 1854 iowrite32be(bus_addr_low, bridge->base +
d22b8ed9
MW		 1855 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1856
ac1a4f2c
MW		 1857 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1858 TSI148_LCSR_OFFSET_DCTL);
1859
d22b8ed9 1860 /* Start the operation */
29848ac9 1861 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
d22b8ed9
MW		 1862 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1863
75c66b6d 1864 retval = wait_event_interruptible(bridge->dma_queue[channel],
29848ac9 1865 tsi148_dma_busy(ctrlr->parent, channel));
ac1a4f2c 1866
75c66b6d
DK		 1867 if (retval) {
1868 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +
1869 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1870 /* Wait for the operation to abort */
1871 wait_event(bridge->dma_queue[channel],
1872 tsi148_dma_busy(ctrlr->parent, channel));
1873 retval = -EINTR;
1874 goto exit;
1875 }
1876
d22b8ed9
MW		 1877 /*
1878 * Read status register, this register is valid until we kick off a
1879 * new transfer.
1880 */
29848ac9 1881 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1882 TSI148_LCSR_OFFSET_DSTA);
1883
1884 if (val & TSI148_LCSR_DSTA_VBE) {
48d9356e 1885 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
d22b8ed9
MW		 1886 retval = -EIO;
1887 }
1888
75c66b6d 1889exit:
d22b8ed9 1890 /* Remove list from running list */
886953e9
EC		 1891 mutex_lock(&ctrlr->mtx);
1892 list_del(&list->list);
1893 mutex_unlock(&ctrlr->mtx);
d22b8ed9
MW		 1894
1895 return retval;
1896}
1897
1898/*
1899 * Clean up a previously generated link list
1900 *
1901 * We have a separate function, don't assume that the chain can't be reused.
1902 */
5ade6c4d 1903static int tsi148_dma_list_empty(struct vme_dma_list *list)
d22b8ed9
MW		 1904{
1905 struct list_head *pos, *temp;
7946328f 1906 struct tsi148_dma_entry *entry;
d22b8ed9 1907
3abc48ae
MW		 1908 struct vme_bridge *tsi148_bridge = list->parent->parent;
1909
d22b8ed9 1910 /* detach and free each entry */
886953e9 1911 list_for_each_safe(pos, temp, &list->entries) {
d22b8ed9
MW		 1912 list_del(pos);
1913 entry = list_entry(pos, struct tsi148_dma_entry, list);
3abc48ae
MW		 1914
1915 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
1916 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
d22b8ed9
MW		 1917 kfree(entry);
1918 }
1919
7946328f 1920 return 0;
d22b8ed9
MW		 1921}
1922
1923/*
1924 * All 4 location monitors reside at the same base - this is therefore a
1925 * system wide configuration.
1926 *
1927 * This does not enable the LM monitor - that should be done when the first
1928 * callback is attached and disabled when the last callback is removed.
1929 */
5ade6c4d 1930static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
6af04b06 1931 u32 aspace, u32 cycle)
d22b8ed9
MW		 1932{
1933 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1934 int i;
48d9356e 1935 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 1936 struct tsi148_driver *bridge;
1937
48d9356e
MW		 1938 tsi148_bridge = lm->parent;
1939
1940 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1941
886953e9 1942 mutex_lock(&lm->mtx);
d22b8ed9
MW		 1943
1944 /* If we already have a callback attached, we can't move it! */
42fb5031 1945 for (i = 0; i < lm->monitors; i++) {
29848ac9 1946 if (bridge->lm_callback[i] != NULL) {
886953e9 1947 mutex_unlock(&lm->mtx);
48d9356e
MW		 1948 dev_err(tsi148_bridge->parent, "Location monitor "
1949 "callback attached, can't reset\n");
d22b8ed9
MW		 1950 return -EBUSY;
1951 }
1952 }
1953
1954 switch (aspace) {
1955 case VME_A16:
1956 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1957 break;
1958 case VME_A24:
1959 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1960 break;
1961 case VME_A32:
1962 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1963 break;
1964 case VME_A64:
1965 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1966 break;
1967 default:
886953e9 1968 mutex_unlock(&lm->mtx);
48d9356e 1969 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1970 return -EINVAL;
1971 break;
1972 }
1973
1974 if (cycle & VME_SUPER)
1975 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1976 if (cycle & VME_USER)
1977 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1978 if (cycle & VME_PROG)
1979 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1980 if (cycle & VME_DATA)
1981 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1982
1983 reg_split(lm_base, &lm_base_high, &lm_base_low);
1984
29848ac9
MW		 1985 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1986 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1987 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 1988
886953e9 1989 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 1990
1991 return 0;
1992}
1993
1994/* Get configuration of the callback monitor and return whether it is enabled
1995 * or disabled.
1996 */
5ade6c4d 1997static int tsi148_lm_get(struct vme_lm_resource *lm,
6af04b06 1998 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
d22b8ed9
MW		 1999{
2000 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
29848ac9
MW		 2001 struct tsi148_driver *bridge;
2002
2003 bridge = lm->parent->driver_priv;
d22b8ed9 2004
886953e9 2005 mutex_lock(&lm->mtx);
d22b8ed9 2006
29848ac9
MW		 2007 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2008 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2009 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2010
2011 reg_join(lm_base_high, lm_base_low, lm_base);
2012
2013 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2014 enabled = 1;
2015
7946328f 2016 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
d22b8ed9 2017 *aspace |= VME_A16;
7946328f
MW		 2018
2019 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
d22b8ed9 2020 *aspace |= VME_A24;
7946328f
MW		 2021
2022 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
d22b8ed9 2023 *aspace |= VME_A32;
7946328f
MW		 2024
2025 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
d22b8ed9 2026 *aspace |= VME_A64;
7946328f 2027
d22b8ed9
MW		 2028
2029 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2030 *cycle |= VME_SUPER;
2031 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2032 *cycle |= VME_USER;
2033 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2034 *cycle |= VME_PROG;
2035 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2036 *cycle |= VME_DATA;
2037
886953e9 2038 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2039
2040 return enabled;
2041}
2042
2043/*
2044 * Attach a callback to a specific location monitor.
2045 *
2046 * Callback will be passed the monitor triggered.
2047 */
5ade6c4d 2048static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
fa54b326 2049 void (*callback)(void *), void *data)
d22b8ed9
MW		 2050{
2051 u32 lm_ctl, tmp;
48d9356e 2052 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 2053 struct tsi148_driver *bridge;
2054
48d9356e
MW		 2055 tsi148_bridge = lm->parent;
2056
2057 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2058
886953e9 2059 mutex_lock(&lm->mtx);
d22b8ed9
MW		 2060
2061 /* Ensure that the location monitor is configured - need PGM or DATA */
29848ac9 2062 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2063 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
886953e9 2064 mutex_unlock(&lm->mtx);
48d9356e
MW		 2065 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2066 "configured\n");
d22b8ed9
MW		 2067 return -EINVAL;
2068 }
2069
2070 /* Check that a callback isn't already attached */
29848ac9 2071 if (bridge->lm_callback[monitor] != NULL) {
886953e9 2072 mutex_unlock(&lm->mtx);
48d9356e 2073 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
d22b8ed9
MW		 2074 return -EBUSY;
2075 }
2076
2077 /* Attach callback */
29848ac9 2078 bridge->lm_callback[monitor] = callback;
fa54b326 2079 bridge->lm_data[monitor] = data;
d22b8ed9
MW		 2080
2081 /* Enable Location Monitor interrupt */
29848ac9 2082 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2083 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2084 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2085
29848ac9 2086 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2087 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2088 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2089
2090 /* Ensure that global Location Monitor Enable set */
2091 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2092 lm_ctl |= TSI148_LCSR_LMAT_EN;
29848ac9 2093 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2094 }
2095
886953e9 2096 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2097
2098 return 0;
2099}
2100
2101/*
2102 * Detach a callback function forn a specific location monitor.
2103 */
5ade6c4d 2104static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
d22b8ed9
MW		 2105{
2106 u32 lm_en, tmp;
29848ac9
MW		 2107 struct tsi148_driver *bridge;
2108
2109 bridge = lm->parent->driver_priv;
d22b8ed9 2110
886953e9 2111 mutex_lock(&lm->mtx);
d22b8ed9
MW		 2112
2113 /* Disable Location Monitor and ensure previous interrupts are clear */
29848ac9 2114 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2115 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2116 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2117
29848ac9 2118 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2119 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2120 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2121
2122 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
29848ac9 2123 bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 2124
2125 /* Detach callback */
29848ac9 2126 bridge->lm_callback[monitor] = NULL;
fa54b326 2127 bridge->lm_data[monitor] = NULL;
d22b8ed9
MW		 2128
2129 /* If all location monitors disabled, disable global Location Monitor */
2130 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2131 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
29848ac9 2132 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2133 tmp &= ~TSI148_LCSR_LMAT_EN;
29848ac9 2134 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2135 }
2136
886953e9 2137 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2138
2139 return 0;
2140}
2141
2142/*
2143 * Determine Geographical Addressing
2144 */
5ade6c4d 2145static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
d22b8ed9 2146{
7946328f 2147 u32 slot = 0;
29848ac9
MW		 2148 struct tsi148_driver *bridge;
2149
2150 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2151
638f199d 2152 if (!geoid) {
29848ac9 2153 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
638f199d
MW		 2154 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2155 } else
2156 slot = geoid;
2157
d22b8ed9
MW		 2158 return (int)slot;
2159}
2160
8a508ff4 2161static void *tsi148_alloc_consistent(struct device *parent, size_t size,
7f58f025
MV		 2162 dma_addr_t *dma)
2163{
2164 struct pci_dev *pdev;
2165
2166 /* Find pci_dev container of dev */
177581fa 2167 pdev = to_pci_dev(parent);
7f58f025
MV		 2168
2169 return pci_alloc_consistent(pdev, size, dma);
2170}
2171
8a508ff4
HS		 2172static void tsi148_free_consistent(struct device *parent, size_t size,
2173 void *vaddr, dma_addr_t dma)
7f58f025
MV		 2174{
2175 struct pci_dev *pdev;
2176
2177 /* Find pci_dev container of dev */
177581fa 2178 pdev = to_pci_dev(parent);
7f58f025
MV		 2179
2180 pci_free_consistent(pdev, size, vaddr, dma);
2181}
2182
d22b8ed9
MW		 2183/*
2184 * Configure CR/CSR space
2185 *
2186 * Access to the CR/CSR can be configured at power-up. The location of the
2187 * CR/CSR registers in the CR/CSR address space is determined by the boards
2188 * Auto-ID or Geographic address. This function ensures that the window is
2189 * enabled at an offset consistent with the boards geopgraphic address.
2190 *
2191 * Each board has a 512kB window, with the highest 4kB being used for the
2192 * boards registers, this means there is a fix length 508kB window which must
2193 * be mapped onto PCI memory.
2194 */
29848ac9
MW		 2195static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2196 struct pci_dev *pdev)
d22b8ed9
MW		 2197{
2198 u32 cbar, crat, vstat;
2199 u32 crcsr_bus_high, crcsr_bus_low;
2200 int retval;
29848ac9
MW		 2201 struct tsi148_driver *bridge;
2202
2203 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2204
2205 /* Allocate mem for CR/CSR image */
88b2608c
JP		 2206 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2207 &bridge->crcsr_bus);
29848ac9 2208 if (bridge->crcsr_kernel == NULL) {
48d9356e
MW		 2209 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2210 "CR/CSR image\n");
d22b8ed9
MW		 2211 return -ENOMEM;
2212 }
2213
29848ac9 2214 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
d22b8ed9 2215
29848ac9
MW		 2216 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2217 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
d22b8ed9
MW		 2218
2219 /* Ensure that the CR/CSR is configured at the correct offset */
29848ac9 2220 cbar = ioread32be(bridge->base + TSI148_CBAR);
d22b8ed9
MW		 2221 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2222
29848ac9 2223 vstat = tsi148_slot_get(tsi148_bridge);
d22b8ed9
MW		 2224
2225 if (cbar != vstat) {
638f199d 2226 cbar = vstat;
48d9356e 2227 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
29848ac9 2228 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
d22b8ed9 2229 }
48d9356e 2230 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
d22b8ed9 2231
29848ac9 2232 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2981795c
MW		 2233 if (crat & TSI148_LCSR_CRAT_EN)
2234 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2235 else {
48d9356e 2236 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
d22b8ed9 2237 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
29848ac9 2238 bridge->base + TSI148_LCSR_CRAT);
2981795c 2239 }
d22b8ed9
MW		 2240
2241 /* If we want flushed, error-checked writes, set up a window
2242 * over the CR/CSR registers. We read from here to safely flush
2243 * through VME writes.
2244 */
7946328f 2245 if (err_chk) {
29848ac9
MW		 2246 retval = tsi148_master_set(bridge->flush_image, 1,
2247 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2248 VME_D16);
d22b8ed9 2249 if (retval)
48d9356e
MW		 2250 dev_err(tsi148_bridge->parent, "Configuring flush image"
2251 " failed\n");
d22b8ed9
MW		 2252 }
2253
2254 return 0;
2255
2256}
2257
29848ac9
MW		 2258static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2259 struct pci_dev *pdev)
d22b8ed9
MW		 2260{
2261 u32 crat;
29848ac9
MW		 2262 struct tsi148_driver *bridge;
2263
2264 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2265
2266 /* Turn off CR/CSR space */
29848ac9 2267 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
d22b8ed9 2268 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
29848ac9 2269 bridge->base + TSI148_LCSR_CRAT);
d22b8ed9
MW		 2270
2271 /* Free image */
29848ac9
MW		 2272 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2273 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
d22b8ed9 2274
29848ac9
MW		 2275 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2276 bridge->crcsr_bus);
d22b8ed9
MW		 2277}
2278
2279static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2280{
2281 int retval, i, master_num;
2282 u32 data;
b49c32ba 2283 struct list_head *pos = NULL, *n;
29848ac9
MW		 2284 struct vme_bridge *tsi148_bridge;
2285 struct tsi148_driver *tsi148_device;
d22b8ed9
MW		 2286 struct vme_master_resource *master_image;
2287 struct vme_slave_resource *slave_image;
2288 struct vme_dma_resource *dma_ctrlr;
42fb5031 2289 struct vme_lm_resource *lm;
d22b8ed9
MW		 2290
2291 /* If we want to support more than one of each bridge, we need to
2292 * dynamically generate this so we get one per device
2293 */
6d011dd8 2294 tsi148_bridge = kzalloc(sizeof(*tsi148_bridge), GFP_KERNEL);
d22b8ed9 2295 if (tsi148_bridge == NULL) {
d22b8ed9
MW		 2296 retval = -ENOMEM;
2297 goto err_struct;
2298 }
326071b3 2299 vme_init_bridge(tsi148_bridge);
d22b8ed9 2300
6d011dd8 2301 tsi148_device = kzalloc(sizeof(*tsi148_device), GFP_KERNEL);
29848ac9 2302 if (tsi148_device == NULL) {
29848ac9
MW		 2303 retval = -ENOMEM;
2304 goto err_driver;
2305 }
2306
29848ac9
MW		 2307 tsi148_bridge->driver_priv = tsi148_device;
2308
d22b8ed9
MW		 2309 /* Enable the device */
2310 retval = pci_enable_device(pdev);
2311 if (retval) {
2312 dev_err(&pdev->dev, "Unable to enable device\n");
2313 goto err_enable;
2314 }
2315
2316 /* Map Registers */
2317 retval = pci_request_regions(pdev, driver_name);
2318 if (retval) {
2319 dev_err(&pdev->dev, "Unable to reserve resources\n");
2320 goto err_resource;
2321 }
2322
2323 /* map registers in BAR 0 */
29848ac9
MW		 2324 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2325 4096);
2326 if (!tsi148_device->base) {
d22b8ed9
MW		 2327 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2328 retval = -EIO;
2329 goto err_remap;
2330 }
2331
2332 /* Check to see if the mapping worked out */
29848ac9 2333 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
d22b8ed9
MW		 2334 if (data != PCI_VENDOR_ID_TUNDRA) {
2335 dev_err(&pdev->dev, "CRG region check failed\n");
2336 retval = -EIO;
2337 goto err_test;
2338 }
2339
2340 /* Initialize wait queues & mutual exclusion flags */
886953e9
EC		 2341 init_waitqueue_head(&tsi148_device->dma_queue[0]);
2342 init_waitqueue_head(&tsi148_device->dma_queue[1]);
2343 init_waitqueue_head(&tsi148_device->iack_queue);
2344 mutex_init(&tsi148_device->vme_int);
2345 mutex_init(&tsi148_device->vme_rmw);
d22b8ed9 2346
886953e9 2347 tsi148_bridge->parent = &pdev->dev;
d22b8ed9
MW		 2348 strcpy(tsi148_bridge->name, driver_name);
2349
2350 /* Setup IRQ */
2351 retval = tsi148_irq_init(tsi148_bridge);
2352 if (retval != 0) {
2353 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2354 goto err_irq;
2355 }
2356
2357 /* If we are going to flush writes, we need to read from the VME bus.
2358 * We need to do this safely, thus we read the devices own CR/CSR
2359 * register. To do this we must set up a window in CR/CSR space and
2360 * hence have one less master window resource available.
2361 */
2362 master_num = TSI148_MAX_MASTER;
7946328f 2363 if (err_chk) {
d22b8ed9 2364 master_num--;
29848ac9 2365
32414878 2366 tsi148_device->flush_image =
6d011dd8
ME		 2367 kmalloc(sizeof(*tsi148_device->flush_image),
2368 GFP_KERNEL);
29848ac9 2369 if (tsi148_device->flush_image == NULL) {
d22b8ed9
MW		 2370 retval = -ENOMEM;
2371 goto err_master;
2372 }
29848ac9 2373 tsi148_device->flush_image->parent = tsi148_bridge;
886953e9 2374 spin_lock_init(&tsi148_device->flush_image->lock);
29848ac9
MW		 2375 tsi148_device->flush_image->locked = 1;
2376 tsi148_device->flush_image->number = master_num;
886953e9 2377 memset(&tsi148_device->flush_image->bus_resource, 0,
6d011dd8 2378 sizeof(tsi148_device->flush_image->bus_resource));
29848ac9 2379 tsi148_device->flush_image->kern_base = NULL;
d22b8ed9
MW		 2380 }
2381
2382 /* Add master windows to list */
d22b8ed9 2383 for (i = 0; i < master_num; i++) {
6d011dd8 2384 master_image = kmalloc(sizeof(*master_image), GFP_KERNEL);
d22b8ed9 2385 if (master_image == NULL) {
d22b8ed9
MW		 2386 retval = -ENOMEM;
2387 goto err_master;
2388 }
2389 master_image->parent = tsi148_bridge;
886953e9 2390 spin_lock_init(&master_image->lock);
d22b8ed9
MW		 2391 master_image->locked = 0;
2392 master_image->number = i;
2393 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
08e03c26
MW		 2394 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2395 VME_USER3 | VME_USER4;
d22b8ed9
MW		 2396 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2397 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2398 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2399 VME_PROG | VME_DATA;
2400 master_image->width_attr = VME_D16 | VME_D32;
886953e9 2401 memset(&master_image->bus_resource, 0,
6d011dd8 2402 sizeof(master_image->bus_resource));
d22b8ed9 2403 master_image->kern_base = NULL;
886953e9
EC		 2404 list_add_tail(&master_image->list,
2405 &tsi148_bridge->master_resources);
d22b8ed9
MW		 2406 }
2407
2408 /* Add slave windows to list */
d22b8ed9 2409 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
6d011dd8 2410 slave_image = kmalloc(sizeof(*slave_image), GFP_KERNEL);
d22b8ed9 2411 if (slave_image == NULL) {
d22b8ed9
MW		 2412 retval = -ENOMEM;
2413 goto err_slave;
2414 }
2415 slave_image->parent = tsi148_bridge;
886953e9 2416 mutex_init(&slave_image->mtx);
d22b8ed9
MW		 2417 slave_image->locked = 0;
2418 slave_image->number = i;
2419 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
08e03c26 2420 VME_A64;
d22b8ed9
MW		 2421 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2422 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2423 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2424 VME_PROG | VME_DATA;
886953e9
EC		 2425 list_add_tail(&slave_image->list,
2426 &tsi148_bridge->slave_resources);
d22b8ed9
MW		 2427 }
2428
2429 /* Add dma engines to list */
d22b8ed9 2430 for (i = 0; i < TSI148_MAX_DMA; i++) {
6d011dd8 2431 dma_ctrlr = kmalloc(sizeof(*dma_ctrlr), GFP_KERNEL);
d22b8ed9 2432 if (dma_ctrlr == NULL) {
d22b8ed9
MW		 2433 retval = -ENOMEM;
2434 goto err_dma;
2435 }
2436 dma_ctrlr->parent = tsi148_bridge;
886953e9 2437 mutex_init(&dma_ctrlr->mtx);
d22b8ed9
MW		 2438 dma_ctrlr->locked = 0;
2439 dma_ctrlr->number = i;
4f723df4
MW		 2440 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2441 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2442 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2443 VME_DMA_PATTERN_TO_MEM;
886953e9
EC		 2444 INIT_LIST_HEAD(&dma_ctrlr->pending);
2445 INIT_LIST_HEAD(&dma_ctrlr->running);
2446 list_add_tail(&dma_ctrlr->list,
2447 &tsi148_bridge->dma_resources);
d22b8ed9
MW		 2448 }
2449
42fb5031 2450 /* Add location monitor to list */
6d011dd8 2451 lm = kmalloc(sizeof(*lm), GFP_KERNEL);
42fb5031 2452 if (lm == NULL) {
42fb5031
MW		 2453 retval = -ENOMEM;
2454 goto err_lm;
2455 }
2456 lm->parent = tsi148_bridge;
886953e9 2457 mutex_init(&lm->mtx);
42fb5031
MW		 2458 lm->locked = 0;
2459 lm->number = 1;
2460 lm->monitors = 4;
886953e9 2461 list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
42fb5031 2462
d22b8ed9
MW		 2463 tsi148_bridge->slave_get = tsi148_slave_get;
2464 tsi148_bridge->slave_set = tsi148_slave_set;
2465 tsi148_bridge->master_get = tsi148_master_get;
2466 tsi148_bridge->master_set = tsi148_master_set;
2467 tsi148_bridge->master_read = tsi148_master_read;
2468 tsi148_bridge->master_write = tsi148_master_write;
2469 tsi148_bridge->master_rmw = tsi148_master_rmw;
2470 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2471 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2472 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
c813f592
MW		 2473 tsi148_bridge->irq_set = tsi148_irq_set;
2474 tsi148_bridge->irq_generate = tsi148_irq_generate;
d22b8ed9
MW		 2475 tsi148_bridge->lm_set = tsi148_lm_set;
2476 tsi148_bridge->lm_get = tsi148_lm_get;
2477 tsi148_bridge->lm_attach = tsi148_lm_attach;
2478 tsi148_bridge->lm_detach = tsi148_lm_detach;
2479 tsi148_bridge->slot_get = tsi148_slot_get;
7f58f025
MV		 2480 tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2481 tsi148_bridge->free_consistent = tsi148_free_consistent;
d22b8ed9 2482
29848ac9 2483 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9 2484 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
7946328f 2485 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
29848ac9 2486 if (!geoid)
638f199d
MW		 2487 dev_info(&pdev->dev, "VME geographical address is %d\n",
2488 data & TSI148_LCSR_VSTAT_GA_M);
29848ac9 2489 else
638f199d
MW		 2490 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2491 geoid);
29848ac9 2492
d22b8ed9
MW		 2493 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2494 err_chk ? "enabled" : "disabled");
2495
0686ab7a
WY		 2496 retval = tsi148_crcsr_init(tsi148_bridge, pdev);
2497 if (retval) {
d22b8ed9
MW		 2498 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2499 goto err_crcsr;
4839737b 2500 }
d22b8ed9 2501
d22b8ed9
MW		 2502 retval = vme_register_bridge(tsi148_bridge);
2503 if (retval != 0) {
2504 dev_err(&pdev->dev, "Chip Registration failed.\n");
2505 goto err_reg;
2506 }
2507
29848ac9
MW		 2508 pci_set_drvdata(pdev, tsi148_bridge);
2509
d22b8ed9 2510 /* Clear VME bus "board fail", and "power-up reset" lines */
29848ac9 2511 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2512 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2513 data |= TSI148_LCSR_VSTAT_CPURST;
29848ac9 2514 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2515
2516 return 0;
2517
d22b8ed9 2518err_reg:
29848ac9 2519 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9 2520err_crcsr:
42fb5031
MW		 2521err_lm:
2522 /* resources are stored in link list */
b49c32ba 2523 list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) {
42fb5031
MW		 2524 lm = list_entry(pos, struct vme_lm_resource, list);
2525 list_del(pos);
2526 kfree(lm);
2527 }
d22b8ed9
MW		 2528err_dma:
2529 /* resources are stored in link list */
b49c32ba 2530 list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) {
d22b8ed9
MW		 2531 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2532 list_del(pos);
2533 kfree(dma_ctrlr);
2534 }
2535err_slave:
2536 /* resources are stored in link list */
b49c32ba 2537 list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) {
d22b8ed9
MW		 2538 slave_image = list_entry(pos, struct vme_slave_resource, list);
2539 list_del(pos);
2540 kfree(slave_image);
2541 }
2542err_master:
2543 /* resources are stored in link list */
b49c32ba 2544 list_for_each_safe(pos, n, &tsi148_bridge->master_resources) {
7946328f
MW		 2545 master_image = list_entry(pos, struct vme_master_resource,
2546 list);
d22b8ed9
MW		 2547 list_del(pos);
2548 kfree(master_image);
2549 }
2550
a82ad05e 2551 tsi148_irq_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2552err_irq:
2553err_test:
29848ac9 2554 iounmap(tsi148_device->base);
d22b8ed9
MW		 2555err_remap:
2556 pci_release_regions(pdev);
2557err_resource:
2558 pci_disable_device(pdev);
2559err_enable:
29848ac9
MW		 2560 kfree(tsi148_device);
2561err_driver:
d22b8ed9
MW		 2562 kfree(tsi148_bridge);
2563err_struct:
2564 return retval;
2565
2566}
2567
2568static void tsi148_remove(struct pci_dev *pdev)
2569{
2570 struct list_head *pos = NULL;
b558ba2f 2571 struct list_head *tmplist;
d22b8ed9
MW		 2572 struct vme_master_resource *master_image;
2573 struct vme_slave_resource *slave_image;
2574 struct vme_dma_resource *dma_ctrlr;
2575 int i;
29848ac9
MW		 2576 struct tsi148_driver *bridge;
2577 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2578
2579 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2580
d22b8ed9 2581
29848ac9 2582 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
d22b8ed9
MW		 2583
2584 /*
2585 * Shutdown all inbound and outbound windows.
2586 */
2587 for (i = 0; i < 8; i++) {
29848ac9 2588 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 2589 TSI148_LCSR_OFFSET_ITAT);
29848ac9 2590 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 2591 TSI148_LCSR_OFFSET_OTAT);
2592 }
2593
2594 /*
2595 * Shutdown Location monitor.
2596 */
29848ac9 2597 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2598
2599 /*
2600 * Shutdown CRG map.
2601 */
29848ac9 2602 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
d22b8ed9
MW		 2603
2604 /*
2605 * Clear error status.
2606 */
29848ac9
MW		 2607 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2608 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2609 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
d22b8ed9
MW		 2610
2611 /*
2612 * Remove VIRQ interrupt (if any)
2613 */
29848ac9
MW		 2614 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2615 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
d22b8ed9 2616
d22b8ed9
MW		 2617 /*
2618 * Map all Interrupts to PCI INTA
2619 */
29848ac9
MW		 2620 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2621 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
d22b8ed9 2622
a82ad05e 2623 tsi148_irq_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2624
2625 vme_unregister_bridge(tsi148_bridge);
2626
29848ac9 2627 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2628
2629 /* resources are stored in link list */
b558ba2f 2630 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
d22b8ed9
MW		 2631 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2632 list_del(pos);
2633 kfree(dma_ctrlr);
2634 }
2635
2636 /* resources are stored in link list */
b558ba2f 2637 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
d22b8ed9
MW		 2638 slave_image = list_entry(pos, struct vme_slave_resource, list);
2639 list_del(pos);
2640 kfree(slave_image);
2641 }
2642
2643 /* resources are stored in link list */
b558ba2f 2644 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
638f199d
MW		 2645 master_image = list_entry(pos, struct vme_master_resource,
2646 list);
d22b8ed9
MW		 2647 list_del(pos);
2648 kfree(master_image);
2649 }
2650
29848ac9 2651 iounmap(bridge->base);
d22b8ed9
MW		 2652
2653 pci_release_regions(pdev);
2654
2655 pci_disable_device(pdev);
2656
29848ac9
MW		 2657 kfree(tsi148_bridge->driver_priv);
2658
d22b8ed9
MW		 2659 kfree(tsi148_bridge);
2660}
2661
01c07143 2662module_pci_driver(tsi148_driver);
d22b8ed9
MW		 2663
2664MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2665module_param(err_chk, bool, 0);
2666
638f199d
MW		 2667MODULE_PARM_DESC(geoid, "Override geographical addressing");
2668module_param(geoid, int, 0);
2669
d22b8ed9
MW		 2670MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2671MODULE_LICENSE("GPL");
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