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1da177e4 1/*
a8018766 2 * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net>
7785925d 3 *
1da177e4
LT
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1da177e4
LT
13 */
14
15#include <asm/io.h>
16
17#include <linux/delay.h>
18#include <linux/moduleparam.h>
339f0723 19#include <linux/module.h>
1da177e4 20
de0d6dbd 21#include "w1_internal.h"
1da177e4 22
a9fb1c7b 23static int w1_delay_parm = 1;
1da177e4
LT
24module_param_named(delay_coef, w1_delay_parm, int, 0);
25
8f1e1251
MF
26static int w1_disable_irqs = 0;
27module_param_named(disable_irqs, w1_disable_irqs, int, 0);
28
1da177e4
LT
29static u8 w1_crc8_table[] = {
30 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
31 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
32 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
33 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
34 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
35 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
36 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
37 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
38 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
39 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
40 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
41 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
42 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
43 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
44 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
45 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
46};
47
70d484bf 48static void w1_delay(unsigned long tm)
1da177e4
LT
49{
50 udelay(tm * w1_delay_parm);
51}
52
be57ce26
EP
53static void w1_write_bit(struct w1_master *dev, int bit);
54static u8 w1_read_bit(struct w1_master *dev);
55
56/**
b3be177a
DF
57 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
58 * @dev: the master device
59 * @bit: 0 - write a 0, 1 - write a 0 read the level
be57ce26 60 */
eb8470db 61u8 w1_touch_bit(struct w1_master *dev, int bit)
1da177e4
LT
62{
63 if (dev->bus_master->touch_bit)
64 return dev->bus_master->touch_bit(dev->bus_master->data, bit);
be57ce26 65 else if (bit)
1da177e4 66 return w1_read_bit(dev);
be57ce26
EP
67 else {
68 w1_write_bit(dev, 0);
23c36c1a 69 return 0;
be57ce26 70 }
1da177e4 71}
eb8470db 72EXPORT_SYMBOL_GPL(w1_touch_bit);
1da177e4 73
be57ce26 74/**
b3be177a
DF
75 * w1_write_bit() - Generates a write-0 or write-1 cycle.
76 * @dev: the master device
77 * @bit: bit to write
78 *
be57ce26
EP
79 * Only call if dev->bus_master->touch_bit is NULL
80 */
81static void w1_write_bit(struct w1_master *dev, int bit)
1da177e4 82{
8f1e1251
MF
83 unsigned long flags = 0;
84
85 if(w1_disable_irqs) local_irq_save(flags);
86
1da177e4
LT
87 if (bit) {
88 dev->bus_master->write_bit(dev->bus_master->data, 0);
89 w1_delay(6);
90 dev->bus_master->write_bit(dev->bus_master->data, 1);
91 w1_delay(64);
92 } else {
93 dev->bus_master->write_bit(dev->bus_master->data, 0);
94 w1_delay(60);
95 dev->bus_master->write_bit(dev->bus_master->data, 1);
96 w1_delay(10);
97 }
8f1e1251
MF
98
99 if(w1_disable_irqs) local_irq_restore(flags);
1da177e4
LT
100}
101
6a158c0d 102/**
b3be177a
DF
103 * w1_pre_write() - pre-write operations
104 * @dev: the master device
105 *
6a158c0d
DF
106 * Pre-write operation, currently only supporting strong pullups.
107 * Program the hardware for a strong pullup, if one has been requested and
108 * the hardware supports it.
6a158c0d
DF
109 */
110static void w1_pre_write(struct w1_master *dev)
111{
112 if (dev->pullup_duration &&
113 dev->enable_pullup && dev->bus_master->set_pullup) {
114 dev->bus_master->set_pullup(dev->bus_master->data,
115 dev->pullup_duration);
116 }
117}
118
119/**
b3be177a
DF
120 * w1_post_write() - post-write options
121 * @dev: the master device
122 *
6a158c0d
DF
123 * Post-write operation, currently only supporting strong pullups.
124 * If a strong pullup was requested, clear it if the hardware supports
125 * them, or execute the delay otherwise, in either case clear the request.
6a158c0d
DF
126 */
127static void w1_post_write(struct w1_master *dev)
128{
129 if (dev->pullup_duration) {
130 if (dev->enable_pullup && dev->bus_master->set_pullup)
131 dev->bus_master->set_pullup(dev->bus_master->data, 0);
132 else
133 msleep(dev->pullup_duration);
134 dev->pullup_duration = 0;
135 }
136}
137
be57ce26 138/**
b3be177a
DF
139 * w1_write_8() - Writes 8 bits.
140 * @dev: the master device
141 * @byte: the byte to write
be57ce26 142 */
1da177e4
LT
143void w1_write_8(struct w1_master *dev, u8 byte)
144{
145 int i;
146
6a158c0d
DF
147 if (dev->bus_master->write_byte) {
148 w1_pre_write(dev);
1da177e4 149 dev->bus_master->write_byte(dev->bus_master->data, byte);
6a158c0d 150 }
1da177e4 151 else
6a158c0d
DF
152 for (i = 0; i < 8; ++i) {
153 if (i == 7)
154 w1_pre_write(dev);
be57ce26 155 w1_touch_bit(dev, (byte >> i) & 0x1);
6a158c0d
DF
156 }
157 w1_post_write(dev);
1da177e4 158}
339f0723 159EXPORT_SYMBOL_GPL(w1_write_8);
1da177e4 160
be57ce26
EP
161
162/**
b3be177a
DF
163 * w1_read_bit() - Generates a write-1 cycle and samples the level.
164 * @dev: the master device
165 *
be57ce26
EP
166 * Only call if dev->bus_master->touch_bit is NULL
167 */
168static u8 w1_read_bit(struct w1_master *dev)
1da177e4
LT
169{
170 int result;
8f1e1251 171 unsigned long flags = 0;
1da177e4 172
3fd306c8
JW
173 /* sample timing is critical here */
174 local_irq_save(flags);
1da177e4
LT
175 dev->bus_master->write_bit(dev->bus_master->data, 0);
176 w1_delay(6);
177 dev->bus_master->write_bit(dev->bus_master->data, 1);
178 w1_delay(9);
179
180 result = dev->bus_master->read_bit(dev->bus_master->data);
3fd306c8
JW
181 local_irq_restore(flags);
182
1da177e4
LT
183 w1_delay(55);
184
185 return result & 0x1;
186}
187
6b729861 188/**
b3be177a
DF
189 * w1_triplet() - * Does a triplet - used for searching ROM addresses.
190 * @dev: the master device
191 * @bdir: the bit to write if both id_bit and comp_bit are 0
192 *
6b729861
EP
193 * Return bits:
194 * bit 0 = id_bit
195 * bit 1 = comp_bit
196 * bit 2 = dir_taken
197 * If both bits 0 & 1 are set, the search should be restarted.
198 *
b3be177a 199 * Return: bit fields - see above
6b729861
EP
200 */
201u8 w1_triplet(struct w1_master *dev, int bdir)
202{
23c36c1a
DM
203 if (dev->bus_master->triplet)
204 return dev->bus_master->triplet(dev->bus_master->data, bdir);
6b729861
EP
205 else {
206 u8 id_bit = w1_touch_bit(dev, 1);
207 u8 comp_bit = w1_touch_bit(dev, 1);
208 u8 retval;
209
23c36c1a
DM
210 if (id_bit && comp_bit)
211 return 0x03; /* error */
6b729861 212
23c36c1a 213 if (!id_bit && !comp_bit) {
6b729861
EP
214 /* Both bits are valid, take the direction given */
215 retval = bdir ? 0x04 : 0;
216 } else {
217 /* Only one bit is valid, take that direction */
218 bdir = id_bit;
219 retval = id_bit ? 0x05 : 0x02;
220 }
221
23c36c1a 222 if (dev->bus_master->touch_bit)
6b729861
EP
223 w1_touch_bit(dev, bdir);
224 else
225 w1_write_bit(dev, bdir);
23c36c1a 226 return retval;
6b729861
EP
227 }
228}
dd6478d6 229EXPORT_SYMBOL_GPL(w1_triplet);
6b729861 230
be57ce26 231/**
b3be177a
DF
232 * w1_read_8() - Reads 8 bits.
233 * @dev: the master device
be57ce26 234 *
b3be177a 235 * Return: the byte read
be57ce26 236 */
34e453d4 237u8 w1_read_8(struct w1_master *dev)
1da177e4
LT
238{
239 int i;
240 u8 res = 0;
241
242 if (dev->bus_master->read_byte)
243 res = dev->bus_master->read_byte(dev->bus_master->data);
244 else
245 for (i = 0; i < 8; ++i)
be57ce26 246 res |= (w1_touch_bit(dev,1) << i);
1da177e4
LT
247
248 return res;
249}
34e453d4 250EXPORT_SYMBOL_GPL(w1_read_8);
1da177e4 251
be57ce26 252/**
b3be177a
DF
253 * w1_write_block() - Writes a series of bytes.
254 * @dev: the master device
255 * @buf: pointer to the data to write
256 * @len: the number of bytes to write
be57ce26
EP
257 */
258void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
1da177e4
LT
259{
260 int i;
261
6a158c0d
DF
262 if (dev->bus_master->write_block) {
263 w1_pre_write(dev);
1da177e4 264 dev->bus_master->write_block(dev->bus_master->data, buf, len);
6a158c0d 265 }
1da177e4
LT
266 else
267 for (i = 0; i < len; ++i)
6a158c0d
DF
268 w1_write_8(dev, buf[i]); /* calls w1_pre_write */
269 w1_post_write(dev);
1da177e4 270}
339f0723 271EXPORT_SYMBOL_GPL(w1_write_block);
1da177e4 272
9be62e0b 273/**
b3be177a
DF
274 * w1_touch_block() - Touches a series of bytes.
275 * @dev: the master device
276 * @buf: pointer to the data to write
277 * @len: the number of bytes to write
9be62e0b
EP
278 */
279void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
280{
281 int i, j;
282 u8 tmp;
283
284 for (i = 0; i < len; ++i) {
285 tmp = 0;
286 for (j = 0; j < 8; ++j) {
287 if (j == 7)
288 w1_pre_write(dev);
289 tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
290 }
291
292 buf[i] = tmp;
293 }
294}
295EXPORT_SYMBOL_GPL(w1_touch_block);
296
be57ce26 297/**
b3be177a
DF
298 * w1_read_block() - Reads a series of bytes.
299 * @dev: the master device
300 * @buf: pointer to the buffer to fill
301 * @len: the number of bytes to read
302 * Return: the number of bytes read
be57ce26 303 */
1da177e4
LT
304u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
305{
306 int i;
307 u8 ret;
308
309 if (dev->bus_master->read_block)
310 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
311 else {
312 for (i = 0; i < len; ++i)
313 buf[i] = w1_read_8(dev);
314 ret = len;
315 }
316
317 return ret;
318}
339f0723 319EXPORT_SYMBOL_GPL(w1_read_block);
1da177e4 320
be57ce26 321/**
b3be177a
DF
322 * w1_reset_bus() - Issues a reset bus sequence.
323 * @dev: the master device
324 * Return: 0=Device present, 1=No device present or error
be57ce26 325 */
1da177e4
LT
326int w1_reset_bus(struct w1_master *dev)
327{
be57ce26 328 int result;
8f1e1251
MF
329 unsigned long flags = 0;
330
331 if(w1_disable_irqs) local_irq_save(flags);
1da177e4
LT
332
333 if (dev->bus_master->reset_bus)
334 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
335 else {
336 dev->bus_master->write_bit(dev->bus_master->data, 0);
8e3dae2b
DF
337 /* minimum 480, max ? us
338 * be nice and sleep, except 18b20 spec lists 960us maximum,
339 * so until we can sleep with microsecond accuracy, spin.
340 * Feel free to come up with some other way to give up the
341 * cpu for such a short amount of time AND get it back in
342 * the maximum amount of time.
343 */
8f1e1251 344 w1_delay(500);
1da177e4
LT
345 dev->bus_master->write_bit(dev->bus_master->data, 1);
346 w1_delay(70);
347
348 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
0db71fec 349 /* minimum 70 (above) + 430 = 500 us
8e3dae2b
DF
350 * There aren't any timing requirements between a reset and
351 * the following transactions. Sleeping is safe here.
352 */
8f1e1251 353 /* w1_delay(430); min required time */
8e3dae2b 354 msleep(1);
1da177e4
LT
355 }
356
8f1e1251
MF
357 if(w1_disable_irqs) local_irq_restore(flags);
358
1da177e4
LT
359 return result;
360}
339f0723 361EXPORT_SYMBOL_GPL(w1_reset_bus);
1da177e4
LT
362
363u8 w1_calc_crc8(u8 * data, int len)
364{
365 u8 crc = 0;
366
367 while (len--)
368 crc = w1_crc8_table[crc ^ *data++];
369
370 return crc;
371}
339f0723 372EXPORT_SYMBOL_GPL(w1_calc_crc8);
1da177e4 373
12003375 374void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
1da177e4
LT
375{
376 dev->attempts++;
377 if (dev->bus_master->search)
c30c9b15
DF
378 dev->bus_master->search(dev->bus_master->data, dev,
379 search_type, cb);
1da177e4 380 else
12003375 381 w1_search(dev, search_type, cb);
1da177e4
LT
382}
383
ea7d8f65 384/**
b3be177a
DF
385 * w1_reset_select_slave() - reset and select a slave
386 * @sl: the slave to select
387 *
ea7d8f65 388 * Resets the bus and then selects the slave by sending either a skip rom
b3be177a
DF
389 * or a rom match. A skip rom is issued if there is only one device
390 * registered on the bus.
ea7d8f65
EP
391 * The w1 master lock must be held.
392 *
b3be177a 393 * Return: 0=success, anything else=error
ea7d8f65
EP
394 */
395int w1_reset_select_slave(struct w1_slave *sl)
396{
397 if (w1_reset_bus(sl->master))
398 return -1;
399
400 if (sl->master->slave_count == 1)
401 w1_write_8(sl->master, W1_SKIP_ROM);
402 else {
403 u8 match[9] = {W1_MATCH_ROM, };
f00a1892
EP
404 u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
405
406 memcpy(&match[1], &rn, 8);
ea7d8f65
EP
407 w1_write_block(sl->master, match, 9);
408 }
409 return 0;
410}
339f0723 411EXPORT_SYMBOL_GPL(w1_reset_select_slave);
6a158c0d 412
67dfd54c 413/**
b3be177a
DF
414 * w1_reset_resume_command() - resume instead of another match ROM
415 * @dev: the master device
416 *
67dfd54c
JFD
417 * When the workflow with a slave amongst many requires several
418 * successive commands a reset between each, this function is similar
419 * to doing a reset then a match ROM for the last matched ROM. The
420 * advantage being that the matched ROM step is skipped in favor of the
421 * resume command. The slave must support the command of course.
422 *
423 * If the bus has only one slave, traditionnaly the match ROM is skipped
424 * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
425 * doesn't work of course, but the resume command is the next best thing.
426 *
427 * The w1 master lock must be held.
67dfd54c
JFD
428 */
429int w1_reset_resume_command(struct w1_master *dev)
430{
431 if (w1_reset_bus(dev))
432 return -1;
433
434 /* This will make only the last matched slave perform a skip ROM. */
435 w1_write_8(dev, W1_RESUME_CMD);
436 return 0;
437}
438EXPORT_SYMBOL_GPL(w1_reset_resume_command);
439
6a158c0d 440/**
b3be177a
DF
441 * w1_next_pullup() - register for a strong pullup
442 * @dev: the master device
443 * @delay: time in milliseconds
444 *
6a158c0d
DF
445 * Put out a strong pull-up of the specified duration after the next write
446 * operation. Not all hardware supports strong pullups. Hardware that
447 * doesn't support strong pullups will sleep for the given time after the
448 * write operation without a strong pullup. This is a one shot request for
449 * the next write, specifying zero will clear a previous request.
450 * The w1 master lock must be held.
451 *
b3be177a 452 * Return: 0=success, anything else=error
6a158c0d
DF
453 */
454void w1_next_pullup(struct w1_master *dev, int delay)
455{
456 dev->pullup_duration = delay;
457}
458EXPORT_SYMBOL_GPL(w1_next_pullup);