[mirror_ubuntu-artful-kernel.git] / drivers / w1 / w1_io.c

/*
 *	w1_io.c
 *
 * Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
 *
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#include <asm/io.h>

#include <linux/delay.h>
#include <linux/moduleparam.h>

#include "w1.h"
#include "w1_log.h"
#include "w1_io.h"

int w1_delay_parm = 1;
module_param_named(delay_coef, w1_delay_parm, int, 0);

static u8 w1_crc8_table[] = {
	0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
	157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
	35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
	190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
	70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
	219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
	101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
	248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
	140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
	17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
	175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
	50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
	202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
	87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
	233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
	116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
};

void w1_delay(unsigned long tm)
{
	udelay(tm * w1_delay_parm);
}

static void w1_write_bit(struct w1_master *dev, int bit);
static u8 w1_read_bit(struct w1_master *dev);

/**
 * Generates a write-0 or write-1 cycle and samples the level.
 */
u8 w1_touch_bit(struct w1_master *dev, int bit)
{
	if (dev->bus_master->touch_bit)
		return dev->bus_master->touch_bit(dev->bus_master->data, bit);
	else if (bit)
		return w1_read_bit(dev);
	else {
		w1_write_bit(dev, 0);
		return(0);
	}
}

/**
 * Generates a write-0 or write-1 cycle.
 * Only call if dev->bus_master->touch_bit is NULL
 */
static void w1_write_bit(struct w1_master *dev, int bit)
{
	if (bit) {
		dev->bus_master->write_bit(dev->bus_master->data, 0);
		w1_delay(6);
		dev->bus_master->write_bit(dev->bus_master->data, 1);
		w1_delay(64);
	} else {
		dev->bus_master->write_bit(dev->bus_master->data, 0);
		w1_delay(60);
		dev->bus_master->write_bit(dev->bus_master->data, 1);
		w1_delay(10);
	}
}

/**
 * Writes 8 bits.
 *
 * @param dev     the master device
 * @param byte    the byte to write
 */
void w1_write_8(struct w1_master *dev, u8 byte)
{
	int i;

	if (dev->bus_master->write_byte)
		dev->bus_master->write_byte(dev->bus_master->data, byte);
	else
		for (i = 0; i < 8; ++i)
			w1_touch_bit(dev, (byte >> i) & 0x1);
}


/**
 * Generates a write-1 cycle and samples the level.
 * Only call if dev->bus_master->touch_bit is NULL
 */
static u8 w1_read_bit(struct w1_master *dev)
{
	int result;

	dev->bus_master->write_bit(dev->bus_master->data, 0);
	w1_delay(6);
	dev->bus_master->write_bit(dev->bus_master->data, 1);
	w1_delay(9);

	result = dev->bus_master->read_bit(dev->bus_master->data);
	w1_delay(55);

	return result & 0x1;
}

/**
 * Reads 8 bits.
 *
 * @param dev     the master device
 * @return        the byte read
 */
u8 w1_read_8(struct w1_master * dev)
{
	int i;
	u8 res = 0;

	if (dev->bus_master->read_byte)
		res = dev->bus_master->read_byte(dev->bus_master->data);
	else
		for (i = 0; i < 8; ++i)
			res |= (w1_touch_bit(dev,1) << i);

	return res;
}

/**
 * Writes a series of bytes.
 *
 * @param dev     the master device
 * @param buf     pointer to the data to write
 * @param len     the number of bytes to write
 * @return        the byte read
 */
void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
{
	int i;

	if (dev->bus_master->write_block)
		dev->bus_master->write_block(dev->bus_master->data, buf, len);
	else
		for (i = 0; i < len; ++i)
			w1_write_8(dev, buf[i]);
}

/**
 * Reads a series of bytes.
 *
 * @param dev     the master device
 * @param buf     pointer to the buffer to fill
 * @param len     the number of bytes to read
 * @return        the number of bytes read
 */
u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
{
	int i;
	u8 ret;

	if (dev->bus_master->read_block)
		ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
	else {
		for (i = 0; i < len; ++i)
			buf[i] = w1_read_8(dev);
		ret = len;
	}

	return ret;
}

/**
 * Issues a reset bus sequence.
 *
 * @param  dev The bus master pointer
 * @return     0=Device present, 1=No device present or error
 */
int w1_reset_bus(struct w1_master *dev)
{
	int result;

	if (dev->bus_master->reset_bus)
		result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
	else {
		dev->bus_master->write_bit(dev->bus_master->data, 0);
		w1_delay(480);
		dev->bus_master->write_bit(dev->bus_master->data, 1);
		w1_delay(70);

		result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
		w1_delay(410);
	}

	return result;
}

u8 w1_calc_crc8(u8 * data, int len)
{
	u8 crc = 0;

	while (len--)
		crc = w1_crc8_table[crc ^ *data++];

	return crc;
}

void w1_search_devices(struct w1_master *dev, w1_slave_found_callback cb)
{
	dev->attempts++;
	if (dev->bus_master->search)
		dev->bus_master->search(dev->bus_master->data, cb);
	else
		w1_search(dev);
}

EXPORT_SYMBOL(w1_touch_bit);
EXPORT_SYMBOL(w1_write_8);
EXPORT_SYMBOL(w1_read_8);
EXPORT_SYMBOL(w1_reset_bus);
EXPORT_SYMBOL(w1_calc_crc8);
EXPORT_SYMBOL(w1_delay);
EXPORT_SYMBOL(w1_read_block);
EXPORT_SYMBOL(w1_write_block);
EXPORT_SYMBOL(w1_search_devices);
Commit	Line	Data
1da177e4	1	/*
7785925d	2	* w1_io.c
1da177e4 LT	3	*
1da177e4 LT	4	* Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
7785925d	5	*
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <asm/io.h>
	23
	24	#include <linux/delay.h>
	25	#include <linux/moduleparam.h>
	26
	27	#include "w1.h"
	28	#include "w1_log.h"
	29	#include "w1_io.h"
	30
	31	int w1_delay_parm = 1;
	32	module_param_named(delay_coef, w1_delay_parm, int, 0);
	33
	34	static u8 w1_crc8_table[] = {
	35	0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
	36	157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
	37	35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
	38	190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
	39	70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
	40	219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
	41	101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
	42	248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
	43	140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
	44	17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
	45	175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
	46	50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
	47	202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
	48	87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
	49	233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
	50	116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
	51	};
	52
	53	void w1_delay(unsigned long tm)
	54	{
	55	udelay(tm * w1_delay_parm);
	56	}
	57
be57ce26 EP	58	static void w1_write_bit(struct w1_master *dev, int bit);
	59	static u8 w1_read_bit(struct w1_master *dev);
	60
	61	/**
	62	* Generates a write-0 or write-1 cycle and samples the level.
	63	*/
1da177e4 LT	64	u8 w1_touch_bit(struct w1_master *dev, int bit)
	65	{
	66	if (dev->bus_master->touch_bit)
	67	return dev->bus_master->touch_bit(dev->bus_master->data, bit);
be57ce26	68	else if (bit)
1da177e4	69	return w1_read_bit(dev);
be57ce26 EP	70	else {
	71	w1_write_bit(dev, 0);
	72	return(0);
	73	}
1da177e4 LT	74	}
1da177e4 LT	75
be57ce26 EP	76	/**
	77	* Generates a write-0 or write-1 cycle.
	78	* Only call if dev->bus_master->touch_bit is NULL
	79	*/
	80	static void w1_write_bit(struct w1_master *dev, int bit)
1da177e4 LT	81	{
	82	if (bit) {
	83	dev->bus_master->write_bit(dev->bus_master->data, 0);
	84	w1_delay(6);
	85	dev->bus_master->write_bit(dev->bus_master->data, 1);
	86	w1_delay(64);
	87	} else {
	88	dev->bus_master->write_bit(dev->bus_master->data, 0);
	89	w1_delay(60);
	90	dev->bus_master->write_bit(dev->bus_master->data, 1);
	91	w1_delay(10);
	92	}
	93	}
	94
be57ce26 EP	95	/**
	96	* Writes 8 bits.
	97	*
	98	* @param dev the master device
	99	* @param byte the byte to write
	100	*/
1da177e4 LT	101	void w1_write_8(struct w1_master *dev, u8 byte)
	102	{
	103	int i;
	104
	105	if (dev->bus_master->write_byte)
	106	dev->bus_master->write_byte(dev->bus_master->data, byte);
	107	else
	108	for (i = 0; i < 8; ++i)
be57ce26	109	w1_touch_bit(dev, (byte >> i) & 0x1);
1da177e4 LT	110	}
1da177e4 LT	111
be57ce26 EP	112
	113	/**
	114	* Generates a write-1 cycle and samples the level.
	115	* Only call if dev->bus_master->touch_bit is NULL
	116	*/
	117	static u8 w1_read_bit(struct w1_master *dev)
1da177e4 LT	118	{
	119	int result;
	120
	121	dev->bus_master->write_bit(dev->bus_master->data, 0);
	122	w1_delay(6);
	123	dev->bus_master->write_bit(dev->bus_master->data, 1);
	124	w1_delay(9);
	125
	126	result = dev->bus_master->read_bit(dev->bus_master->data);
	127	w1_delay(55);
	128
	129	return result & 0x1;
	130	}
	131
be57ce26 EP	132	/**
	133	* Reads 8 bits.
	134	*
	135	* @param dev the master device
	136	* @return the byte read
	137	*/
1da177e4 LT	138	u8 w1_read_8(struct w1_master * dev)
	139	{
	140	int i;
	141	u8 res = 0;
	142
	143	if (dev->bus_master->read_byte)
	144	res = dev->bus_master->read_byte(dev->bus_master->data);
	145	else
	146	for (i = 0; i < 8; ++i)
be57ce26	147	res \|= (w1_touch_bit(dev,1) << i);
1da177e4 LT	148
	149	return res;
	150	}
	151
be57ce26 EP	152	/**
	153	* Writes a series of bytes.
	154	*
	155	* @param dev the master device
	156	* @param buf pointer to the data to write
	157	* @param len the number of bytes to write
	158	* @return the byte read
	159	*/
	160	void w1_write_block(struct w1_master dev, const u8 buf, int len)
1da177e4 LT	161	{
	162	int i;
	163
	164	if (dev->bus_master->write_block)
	165	dev->bus_master->write_block(dev->bus_master->data, buf, len);
	166	else
	167	for (i = 0; i < len; ++i)
	168	w1_write_8(dev, buf[i]);
	169	}
	170
be57ce26 EP	171	/**
	172	* Reads a series of bytes.
	173	*
	174	* @param dev the master device
	175	* @param buf pointer to the buffer to fill
	176	* @param len the number of bytes to read
	177	* @return the number of bytes read
	178	*/
1da177e4 LT	179	u8 w1_read_block(struct w1_master dev, u8 buf, int len)
	180	{
	181	int i;
	182	u8 ret;
	183
	184	if (dev->bus_master->read_block)
	185	ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
	186	else {
	187	for (i = 0; i < len; ++i)
	188	buf[i] = w1_read_8(dev);
	189	ret = len;
	190	}
	191
	192	return ret;
	193	}
	194
be57ce26 EP	195	/**
	196	* Issues a reset bus sequence.
	197	*
	198	* @param dev The bus master pointer
	199	* @return 0=Device present, 1=No device present or error
	200	*/
1da177e4 LT	201	int w1_reset_bus(struct w1_master *dev)
1da177e4 LT	202	{
be57ce26	203	int result;
1da177e4 LT	204
	205	if (dev->bus_master->reset_bus)
	206	result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
	207	else {
	208	dev->bus_master->write_bit(dev->bus_master->data, 0);
	209	w1_delay(480);
	210	dev->bus_master->write_bit(dev->bus_master->data, 1);
	211	w1_delay(70);
	212
	213	result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
	214	w1_delay(410);
	215	}
	216
	217	return result;
	218	}
	219
	220	u8 w1_calc_crc8(u8 * data, int len)
	221	{
	222	u8 crc = 0;
	223
	224	while (len--)
	225	crc = w1_crc8_table[crc ^ *data++];
	226
	227	return crc;
	228	}
	229
	230	void w1_search_devices(struct w1_master *dev, w1_slave_found_callback cb)
	231	{
	232	dev->attempts++;
	233	if (dev->bus_master->search)
	234	dev->bus_master->search(dev->bus_master->data, cb);
	235	else
	236	w1_search(dev);
	237	}
	238
be57ce26	239	EXPORT_SYMBOL(w1_touch_bit);
1da177e4	240	EXPORT_SYMBOL(w1_write_8);
1da177e4 LT	241	EXPORT_SYMBOL(w1_read_8);
	242	EXPORT_SYMBOL(w1_reset_bus);
	243	EXPORT_SYMBOL(w1_calc_crc8);
	244	EXPORT_SYMBOL(w1_delay);
	245	EXPORT_SYMBOL(w1_read_block);
	246	EXPORT_SYMBOL(w1_write_block);
	247	EXPORT_SYMBOL(w1_search_devices);