[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / aspeed_wdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2016 IBM Corporation
 *
 * Joel Stanley <joel@jms.id.au>
 */

#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/watchdog.h>

struct aspeed_wdt {
	struct watchdog_device	wdd;
	void __iomem		*base;
	u32			ctrl;
};

struct aspeed_wdt_config {
	u32 ext_pulse_width_mask;
};

static const struct aspeed_wdt_config ast2400_config = {
	.ext_pulse_width_mask = 0xff,
};

static const struct aspeed_wdt_config ast2500_config = {
	.ext_pulse_width_mask = 0xfffff,
};

static const struct of_device_id aspeed_wdt_of_table[] = {
	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
	{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
	{ .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
	{ },
};
MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);

#define WDT_STATUS		0x00
#define WDT_RELOAD_VALUE	0x04
#define WDT_RESTART		0x08
#define WDT_CTRL		0x0C
#define   WDT_CTRL_BOOT_SECONDARY	BIT(7)
#define   WDT_CTRL_RESET_MODE_SOC	(0x00 << 5)
#define   WDT_CTRL_RESET_MODE_FULL_CHIP	(0x01 << 5)
#define   WDT_CTRL_RESET_MODE_ARM_CPU	(0x10 << 5)
#define   WDT_CTRL_1MHZ_CLK		BIT(4)
#define   WDT_CTRL_WDT_EXT		BIT(3)
#define   WDT_CTRL_WDT_INTR		BIT(2)
#define   WDT_CTRL_RESET_SYSTEM		BIT(1)
#define   WDT_CTRL_ENABLE		BIT(0)
#define WDT_TIMEOUT_STATUS	0x10
#define   WDT_TIMEOUT_STATUS_BOOT_SECONDARY	BIT(1)
#define WDT_CLEAR_TIMEOUT_STATUS	0x14
#define   WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION	BIT(0)

/*
 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
 * enabled), specifically:
 *
 * * Pulse duration
 * * Drive mode: push-pull vs open-drain
 * * Polarity: Active high or active low
 *
 * Pulse duration configuration is available on both the AST2400 and AST2500,
 * though the field changes between SoCs:
 *
 * AST2400: Bits 7:0
 * AST2500: Bits 19:0
 *
 * This difference is captured in struct aspeed_wdt_config.
 *
 * The AST2500 exposes the drive mode and polarity options, but not in a
 * regular fashion. For read purposes, bit 31 represents active high or low,
 * and bit 30 represents push-pull or open-drain. With respect to write, magic
 * values need to be written to the top byte to change the state of the drive
 * mode and polarity bits. Any other value written to the top byte has no
 * effect on the state of the drive mode or polarity bits. However, the pulse
 * width value must be preserved (as desired) if written.
 */
#define WDT_RESET_WIDTH		0x18
#define   WDT_RESET_WIDTH_ACTIVE_HIGH	BIT(31)
#define     WDT_ACTIVE_HIGH_MAGIC	(0xA5 << 24)
#define     WDT_ACTIVE_LOW_MAGIC	(0x5A << 24)
#define   WDT_RESET_WIDTH_PUSH_PULL	BIT(30)
#define     WDT_PUSH_PULL_MAGIC		(0xA8 << 24)
#define     WDT_OPEN_DRAIN_MAGIC	(0x8A << 24)

#define WDT_RESTART_MAGIC	0x4755

/* 32 bits at 1MHz, in milliseconds */
#define WDT_MAX_TIMEOUT_MS	4294967
#define WDT_DEFAULT_TIMEOUT	30
#define WDT_RATE_1MHZ		1000000

static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
{
	return container_of(wdd, struct aspeed_wdt, wdd);
}

static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
{
	wdt->ctrl |= WDT_CTRL_ENABLE;

	writel(0, wdt->base + WDT_CTRL);
	writel(count, wdt->base + WDT_RELOAD_VALUE);
	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	writel(wdt->ctrl, wdt->base + WDT_CTRL);
}

static int aspeed_wdt_start(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);

	return 0;
}

static int aspeed_wdt_stop(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	wdt->ctrl &= ~WDT_CTRL_ENABLE;
	writel(wdt->ctrl, wdt->base + WDT_CTRL);

	return 0;
}

static int aspeed_wdt_ping(struct watchdog_device *wdd)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);

	return 0;
}

static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
				  unsigned int timeout)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	u32 actual;

	wdd->timeout = timeout;

	actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);

	writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);

	return 0;
}

static int aspeed_wdt_restart(struct watchdog_device *wdd,
			      unsigned long action, void *data)
{
	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);

	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);

	mdelay(1000);

	return 0;
}

/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
static ssize_t access_cs0_show(struct device *dev,
			       struct device_attribute *attr, char *buf)
{
	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
	u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);

	return sprintf(buf, "%u\n",
		      !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
}

static ssize_t access_cs0_store(struct device *dev,
				struct device_attribute *attr, const char *buf,
				size_t size)
{
	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
	unsigned long val;

	if (kstrtoul(buf, 10, &val))
		return -EINVAL;

	if (val)
		writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
		       wdt->base + WDT_CLEAR_TIMEOUT_STATUS);

	return size;
}

/*
 * This attribute exists only if the system has booted from the alternate
 * flash with 'alt-boot' option.
 *
 * At alternate flash the 'access_cs0' sysfs node provides:
 *   ast2400: a way to get access to the primary SPI flash chip at CS0
 *            after booting from the alternate chip at CS1.
 *   ast2500: a way to restore the normal address mapping from
 *            (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
 *
 * Clearing the boot code selection and timeout counter also resets to the
 * initial state the chip select line mapping. When the SoC is in normal
 * mapping state (i.e. booted from CS0), clearing those bits does nothing for
 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
 * wdt2 expiration) the behavior differs as described above.
 *
 * This option can be used with wdt2 (watchdog1) only.
 */
static DEVICE_ATTR_RW(access_cs0);

static struct attribute *bswitch_attrs[] = {
	&dev_attr_access_cs0.attr,
	NULL
};
ATTRIBUTE_GROUPS(bswitch);

static const struct watchdog_ops aspeed_wdt_ops = {
	.start		= aspeed_wdt_start,
	.stop		= aspeed_wdt_stop,
	.ping		= aspeed_wdt_ping,
	.set_timeout	= aspeed_wdt_set_timeout,
	.restart	= aspeed_wdt_restart,
	.owner		= THIS_MODULE,
};

static const struct watchdog_info aspeed_wdt_info = {
	.options	= WDIOF_KEEPALIVEPING
			| WDIOF_MAGICCLOSE
			| WDIOF_SETTIMEOUT,
	.identity	= KBUILD_MODNAME,
};

static int aspeed_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct aspeed_wdt_config *config;
	const struct of_device_id *ofdid;
	struct aspeed_wdt *wdt;
	struct device_node *np;
	const char *reset_type;
	u32 duration;
	u32 status;
	int ret;

	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	wdt->wdd.info = &aspeed_wdt_info;
	wdt->wdd.ops = &aspeed_wdt_ops;
	wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
	wdt->wdd.parent = dev;

	wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
	watchdog_init_timeout(&wdt->wdd, 0, dev);

	np = dev->of_node;

	ofdid = of_match_node(aspeed_wdt_of_table, np);
	if (!ofdid)
		return -EINVAL;
	config = ofdid->data;

	/*
	 * On clock rates:
	 *  - ast2400 wdt can run at PCLK, or 1MHz
	 *  - ast2500 only runs at 1MHz, hard coding bit 4 to 1
	 *  - ast2600 always runs at 1MHz
	 *
	 * Set the ast2400 to run at 1MHz as it simplifies the driver.
	 */
	if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
		wdt->ctrl = WDT_CTRL_1MHZ_CLK;

	/*
	 * Control reset on a per-device basis to ensure the
	 * host is not affected by a BMC reboot
	 */
	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
	if (ret) {
		wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
	} else {
		if (!strcmp(reset_type, "cpu"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
				     WDT_CTRL_RESET_SYSTEM;
		else if (!strcmp(reset_type, "soc"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
				     WDT_CTRL_RESET_SYSTEM;
		else if (!strcmp(reset_type, "system"))
			wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
				     WDT_CTRL_RESET_SYSTEM;
		else if (strcmp(reset_type, "none"))
			return -EINVAL;
	}
	if (of_property_read_bool(np, "aspeed,external-signal"))
		wdt->ctrl |= WDT_CTRL_WDT_EXT;
	if (of_property_read_bool(np, "aspeed,alt-boot"))
		wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;

	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
		/*
		 * The watchdog is running, but invoke aspeed_wdt_start() to
		 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
		 * configuration conforms to the driver's expectations.
		 * Primarily, ensure we're using the 1MHz clock source.
		 */
		aspeed_wdt_start(&wdt->wdd);
		set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	}

	if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
		(of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
		u32 reg = readl(wdt->base + WDT_RESET_WIDTH);

		reg &= config->ext_pulse_width_mask;
		if (of_property_read_bool(np, "aspeed,ext-push-pull"))
			reg |= WDT_PUSH_PULL_MAGIC;
		else
			reg |= WDT_OPEN_DRAIN_MAGIC;

		writel(reg, wdt->base + WDT_RESET_WIDTH);

		reg &= config->ext_pulse_width_mask;
		if (of_property_read_bool(np, "aspeed,ext-active-high"))
			reg |= WDT_ACTIVE_HIGH_MAGIC;
		else
			reg |= WDT_ACTIVE_LOW_MAGIC;

		writel(reg, wdt->base + WDT_RESET_WIDTH);
	}

	if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
		u32 max_duration = config->ext_pulse_width_mask + 1;

		if (duration == 0 || duration > max_duration) {
			dev_err(dev, "Invalid pulse duration: %uus\n",
				duration);
			duration = max(1U, min(max_duration, duration));
			dev_info(dev, "Pulse duration set to %uus\n",
				 duration);
		}

		/*
		 * The watchdog is always configured with a 1MHz source, so
		 * there is no need to scale the microsecond value. However we
		 * need to offset it - from the datasheet:
		 *
		 * "This register decides the asserting duration of wdt_ext and
		 * wdt_rstarm signal. The default value is 0xFF. It means the
		 * default asserting duration of wdt_ext and wdt_rstarm is
		 * 256us."
		 *
		 * This implies a value of 0 gives a 1us pulse.
		 */
		writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
	}

	status = readl(wdt->base + WDT_TIMEOUT_STATUS);
	if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
		wdt->wdd.bootstatus = WDIOF_CARDRESET;

		if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
		    of_device_is_compatible(np, "aspeed,ast2500-wdt"))
			wdt->wdd.groups = bswitch_groups;
	}

	dev_set_drvdata(dev, wdt);

	return devm_watchdog_register_device(dev, &wdt->wdd);
}

static struct platform_driver aspeed_watchdog_driver = {
	.probe = aspeed_wdt_probe,
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = of_match_ptr(aspeed_wdt_of_table),
	},
};

static int __init aspeed_wdt_init(void)
{
	return platform_driver_register(&aspeed_watchdog_driver);
}
arch_initcall(aspeed_wdt_init);

static void __exit aspeed_wdt_exit(void)
{
	platform_driver_unregister(&aspeed_watchdog_driver);
}
module_exit(aspeed_wdt_exit);

MODULE_DESCRIPTION("Aspeed Watchdog Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
efa859f7 JS	2	/*
	3	* Copyright 2016 IBM Corporation
	4	*
	5	* Joel Stanley <joel@jms.id.au>
efa859f7 JS	6	*/
	7
	8	#include <linux/delay.h>
	9	#include <linux/io.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/watchdog.h>
	15
	16	struct aspeed_wdt {
	17	struct watchdog_device wdd;
	18	void __iomem *base;
	19	u32 ctrl;
	20	};
	21
012c0460 AJ	22	struct aspeed_wdt_config {
	23	u32 ext_pulse_width_mask;
	24	};
	25
	26	static const struct aspeed_wdt_config ast2400_config = {
	27	.ext_pulse_width_mask = 0xff,
	28	};
	29
	30	static const struct aspeed_wdt_config ast2500_config = {
	31	.ext_pulse_width_mask = 0xfffff,
	32	};
	33
efa859f7	34	static const struct of_device_id aspeed_wdt_of_table[] = {
012c0460 AJ	35	{ .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
012c0460 AJ	36	{ .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
b3528b48	37	{ .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
efa859f7 JS	38	{ },
	39	};
	40	MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
	41
	42	#define WDT_STATUS 0x00
	43	#define WDT_RELOAD_VALUE 0x04
	44	#define WDT_RESTART 0x08
	45	#define WDT_CTRL 0x0C
6ffa3402	46	#define WDT_CTRL_BOOT_SECONDARY BIT(7)
efa859f7 JS	47	#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
efa859f7 JS	48	#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
b7f0b8ad	49	#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
efa859f7 JS	50	#define WDT_CTRL_1MHZ_CLK BIT(4)
	51	#define WDT_CTRL_WDT_EXT BIT(3)
	52	#define WDT_CTRL_WDT_INTR BIT(2)
	53	#define WDT_CTRL_RESET_SYSTEM BIT(1)
	54	#define WDT_CTRL_ENABLE BIT(0)
49d4d277 EJ	55	#define WDT_TIMEOUT_STATUS 0x10
49d4d277 EJ	56	#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
3d9e89bd IM	57	#define WDT_CLEAR_TIMEOUT_STATUS 0x14
3d9e89bd IM	58	#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
efa859f7	59
012c0460 AJ	60	/*
	61	* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
	62	* enabled), specifically:
	63	*
	64	* * Pulse duration
	65	* * Drive mode: push-pull vs open-drain
	66	* * Polarity: Active high or active low
	67	*
	68	* Pulse duration configuration is available on both the AST2400 and AST2500,
	69	* though the field changes between SoCs:
	70	*
	71	* AST2400: Bits 7:0
	72	* AST2500: Bits 19:0
	73	*
	74	* This difference is captured in struct aspeed_wdt_config.
	75	*
	76	* The AST2500 exposes the drive mode and polarity options, but not in a
	77	* regular fashion. For read purposes, bit 31 represents active high or low,
	78	* and bit 30 represents push-pull or open-drain. With respect to write, magic
	79	* values need to be written to the top byte to change the state of the drive
	80	* mode and polarity bits. Any other value written to the top byte has no
	81	* effect on the state of the drive mode or polarity bits. However, the pulse
	82	* width value must be preserved (as desired) if written.
	83	*/
	84	#define WDT_RESET_WIDTH 0x18
	85	#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
	86	#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
	87	#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
	88	#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
	89	#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
	90	#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
	91
efa859f7 JS	92	#define WDT_RESTART_MAGIC 0x4755
	93
	94	/* 32 bits at 1MHz, in milliseconds */
	95	#define WDT_MAX_TIMEOUT_MS 4294967
	96	#define WDT_DEFAULT_TIMEOUT 30
	97	#define WDT_RATE_1MHZ 1000000
	98
	99	static struct aspeed_wdt to_aspeed_wdt(struct watchdog_device wdd)
	100	{
	101	return container_of(wdd, struct aspeed_wdt, wdd);
	102	}
	103
	104	static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
	105	{
	106	wdt->ctrl \|= WDT_CTRL_ENABLE;
	107
	108	writel(0, wdt->base + WDT_CTRL);
	109	writel(count, wdt->base + WDT_RELOAD_VALUE);
	110	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	111	writel(wdt->ctrl, wdt->base + WDT_CTRL);
	112	}
	113
	114	static int aspeed_wdt_start(struct watchdog_device *wdd)
	115	{
	116	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	117
	118	aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
	119
	120	return 0;
	121	}
	122
	123	static int aspeed_wdt_stop(struct watchdog_device *wdd)
	124	{
	125	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	126
	127	wdt->ctrl &= ~WDT_CTRL_ENABLE;
	128	writel(wdt->ctrl, wdt->base + WDT_CTRL);
	129
	130	return 0;
	131	}
	132
	133	static int aspeed_wdt_ping(struct watchdog_device *wdd)
	134	{
	135	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	136
	137	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	138
	139	return 0;
	140	}
	141
	142	static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
	143	unsigned int timeout)
	144	{
	145	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
	146	u32 actual;
	147
	148	wdd->timeout = timeout;
	149
	150	actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
	151
	152	writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
	153	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
	154
	155	return 0;
156	}
157
158	static int aspeed_wdt_restart(struct watchdog_device *wdd,
159	unsigned long action, void *data)
160	{
161	struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
162
6ffa3402	163	wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
efa859f7 JS	164	aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
	165
	166	mdelay(1000);
	167
	168	return 0;
	169	}
	170
3d9e89bd IM	171	/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
	172	static ssize_t access_cs0_show(struct device *dev,
	173	struct device_attribute attr, char buf)
	174	{
	175	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
	176	u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
	177
	178	return sprintf(buf, "%u\n",
	179	!(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
	180	}
	181
	182	static ssize_t access_cs0_store(struct device *dev,
	183	struct device_attribute attr, const char buf,
	184	size_t size)
	185	{
	186	struct aspeed_wdt *wdt = dev_get_drvdata(dev);
	187	unsigned long val;
	188
	189	if (kstrtoul(buf, 10, &val))
	190	return -EINVAL;
	191
	192	if (val)
	193	writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
	194	wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
	195
	196	return size;
	197	}
	198
	199	/*
	200	* This attribute exists only if the system has booted from the alternate
	201	* flash with 'alt-boot' option.
	202	*
	203	* At alternate flash the 'access_cs0' sysfs node provides:
	204	* ast2400: a way to get access to the primary SPI flash chip at CS0
	205	* after booting from the alternate chip at CS1.
	206	* ast2500: a way to restore the normal address mapping from
	207	* (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
	208	*
	209	* Clearing the boot code selection and timeout counter also resets to the
	210	* initial state the chip select line mapping. When the SoC is in normal
	211	* mapping state (i.e. booted from CS0), clearing those bits does nothing for
	212	* both versions of the SoC. For alternate boot mode (booted from CS1 due to
	213	* wdt2 expiration) the behavior differs as described above.
	214	*
	215	* This option can be used with wdt2 (watchdog1) only.
	216	*/
	217	static DEVICE_ATTR_RW(access_cs0);
	218
	219	static struct attribute *bswitch_attrs[] = {
	220	&dev_attr_access_cs0.attr,
	221	NULL
	222	};
	223	ATTRIBUTE_GROUPS(bswitch);
	224
efa859f7 JS	225	static const struct watchdog_ops aspeed_wdt_ops = {
	226	.start = aspeed_wdt_start,
	227	.stop = aspeed_wdt_stop,
	228	.ping = aspeed_wdt_ping,
	229	.set_timeout = aspeed_wdt_set_timeout,
	230	.restart = aspeed_wdt_restart,
	231	.owner = THIS_MODULE,
	232	};
	233
	234	static const struct watchdog_info aspeed_wdt_info = {
	235	.options = WDIOF_KEEPALIVEPING
	236	\| WDIOF_MAGICCLOSE
	237	\| WDIOF_SETTIMEOUT,
	238	.identity = KBUILD_MODNAME,
	239	};
	240
efa859f7 JS	241	static int aspeed_wdt_probe(struct platform_device *pdev)
efa859f7 JS	242	{
eda21ee9	243	struct device *dev = &pdev->dev;
012c0460 AJ	244	const struct aspeed_wdt_config *config;
012c0460 AJ	245	const struct of_device_id *ofdid;
efa859f7	246	struct aspeed_wdt *wdt;
b7f0b8ad CB	247	struct device_node *np;
b7f0b8ad CB	248	const char *reset_type;
012c0460	249	u32 duration;
49d4d277	250	u32 status;
efa859f7 JS	251	int ret;
efa859f7 JS	252
eda21ee9	253	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
efa859f7 JS	254	if (!wdt)
	255	return -ENOMEM;
	256
0f0a6a28	257	wdt->base = devm_platform_ioremap_resource(pdev, 0);
efa859f7 JS	258	if (IS_ERR(wdt->base))
	259	return PTR_ERR(wdt->base);
	260
efa859f7 JS	261	wdt->wdd.info = &aspeed_wdt_info;
	262	wdt->wdd.ops = &aspeed_wdt_ops;
	263	wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
eda21ee9	264	wdt->wdd.parent = dev;
efa859f7 JS	265
efa859f7 JS	266	wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
eda21ee9	267	watchdog_init_timeout(&wdt->wdd, 0, dev);
efa859f7	268
eda21ee9	269	np = dev->of_node;
012c0460 AJ	270
	271	ofdid = of_match_node(aspeed_wdt_of_table, np);
	272	if (!ofdid)
	273	return -EINVAL;
	274	config = ofdid->data;
	275
c0457125 JS	276	/*
	277	* On clock rates:
	278	* - ast2400 wdt can run at PCLK, or 1MHz
	279	* - ast2500 only runs at 1MHz, hard coding bit 4 to 1
	280	* - ast2600 always runs at 1MHz
	281	*
	282	* Set the ast2400 to run at 1MHz as it simplifies the driver.
	283	*/
	284	if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
	285	wdt->ctrl = WDT_CTRL_1MHZ_CLK;
b7f0b8ad	286
efa859f7 JS	287	/*
efa859f7 JS	288	* Control reset on a per-device basis to ensure the
b7f0b8ad	289	* host is not affected by a BMC reboot
efa859f7	290	*/
b7f0b8ad CB	291	ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
	292	if (ret) {
	293	wdt->ctrl \|= WDT_CTRL_RESET_MODE_SOC \| WDT_CTRL_RESET_SYSTEM;
	294	} else {
	295	if (!strcmp(reset_type, "cpu"))
d2fc8db6 MM	296	wdt->ctrl \|= WDT_CTRL_RESET_MODE_ARM_CPU \|
d2fc8db6 MM	297	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad	298	else if (!strcmp(reset_type, "soc"))
d2fc8db6 MM	299	wdt->ctrl \|= WDT_CTRL_RESET_MODE_SOC \|
d2fc8db6 MM	300	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad	301	else if (!strcmp(reset_type, "system"))
d2fc8db6 MM	302	wdt->ctrl \|= WDT_CTRL_RESET_MODE_FULL_CHIP \|
d2fc8db6 MM	303	WDT_CTRL_RESET_SYSTEM;
b7f0b8ad CB	304	else if (strcmp(reset_type, "none"))
	305	return -EINVAL;
	306	}
	307	if (of_property_read_bool(np, "aspeed,external-signal"))
	308	wdt->ctrl \|= WDT_CTRL_WDT_EXT;
6ffa3402 MM	309	if (of_property_read_bool(np, "aspeed,alt-boot"))
6ffa3402 MM	310	wdt->ctrl \|= WDT_CTRL_BOOT_SECONDARY;
b7f0b8ad	311
efa859f7	312	if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
9f3e13c7 AJ	313	/*
	314	* The watchdog is running, but invoke aspeed_wdt_start() to
	315	* write wdt->ctrl to WDT_CTRL to ensure the watchdog's
	316	* configuration conforms to the driver's expectations.
	317	* Primarily, ensure we're using the 1MHz clock source.
	318	*/
efa859f7 JS	319	aspeed_wdt_start(&wdt->wdd);
	320	set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
	321	}
	322
b3528b48 RC	323	if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) \|\|
b3528b48 RC	324	(of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
012c0460 AJ	325	u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
	326
	327	reg &= config->ext_pulse_width_mask;
	328	if (of_property_read_bool(np, "aspeed,ext-push-pull"))
	329	reg \|= WDT_PUSH_PULL_MAGIC;
	330	else
	331	reg \|= WDT_OPEN_DRAIN_MAGIC;
	332
	333	writel(reg, wdt->base + WDT_RESET_WIDTH);
	334
	335	reg &= config->ext_pulse_width_mask;
	336	if (of_property_read_bool(np, "aspeed,ext-active-high"))
	337	reg \|= WDT_ACTIVE_HIGH_MAGIC;
	338	else
	339	reg \|= WDT_ACTIVE_LOW_MAGIC;
	340
	341	writel(reg, wdt->base + WDT_RESET_WIDTH);
	342	}
	343
	344	if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
	345	u32 max_duration = config->ext_pulse_width_mask + 1;
	346
	347	if (duration == 0 \|\| duration > max_duration) {
eda21ee9 GR	348	dev_err(dev, "Invalid pulse duration: %uus\n",
eda21ee9 GR	349	duration);
012c0460	350	duration = max(1U, min(max_duration, duration));
eda21ee9 GR	351	dev_info(dev, "Pulse duration set to %uus\n",
eda21ee9 GR	352	duration);
012c0460 AJ	353	}
	354
	355	/*
	356	* The watchdog is always configured with a 1MHz source, so
	357	* there is no need to scale the microsecond value. However we
	358	* need to offset it - from the datasheet:
	359	*
	360	* "This register decides the asserting duration of wdt_ext and
	361	* wdt_rstarm signal. The default value is 0xFF. It means the
	362	* default asserting duration of wdt_ext and wdt_rstarm is
	363	* 256us."
	364	*
	365	* This implies a value of 0 gives a 1us pulse.
	366	*/
	367	writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
	368	}
	369
49d4d277	370	status = readl(wdt->base + WDT_TIMEOUT_STATUS);
3d9e89bd	371	if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
49d4d277 EJ	372	wdt->wdd.bootstatus = WDIOF_CARDRESET;
49d4d277 EJ	373
3d9e89bd IM	374	if (of_device_is_compatible(np, "aspeed,ast2400-wdt") \|\|
	375	of_device_is_compatible(np, "aspeed,ast2500-wdt"))
	376	wdt->wdd.groups = bswitch_groups;
	377	}
	378
	379	dev_set_drvdata(dev, wdt);
	380
4ab05433	381	return devm_watchdog_register_device(dev, &wdt->wdd);
efa859f7 JS	382	}
	383
	384	static struct platform_driver aspeed_watchdog_driver = {
	385	.probe = aspeed_wdt_probe,
efa859f7 JS	386	.driver = {
	387	.name = KBUILD_MODNAME,
	388	.of_match_table = of_match_ptr(aspeed_wdt_of_table),
	389	},
	390	};
d4238aa4 AJ	391
	392	static int __init aspeed_wdt_init(void)
	393	{
	394	return platform_driver_register(&aspeed_watchdog_driver);
	395	}
	396	arch_initcall(aspeed_wdt_init);
	397
	398	static void __exit aspeed_wdt_exit(void)
	399	{
	400	platform_driver_unregister(&aspeed_watchdog_driver);
	401	}
	402	module_exit(aspeed_wdt_exit);
efa859f7 JS	403
	404	MODULE_DESCRIPTION("Aspeed Watchdog Driver");
	405	MODULE_LICENSE("GPL");