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efa859f7 JS |
1 | /* |
2 | * Copyright 2016 IBM Corporation | |
3 | * | |
4 | * Joel Stanley <joel@jms.id.au> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/delay.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/watchdog.h> | |
19 | ||
20 | struct aspeed_wdt { | |
21 | struct watchdog_device wdd; | |
22 | void __iomem *base; | |
23 | u32 ctrl; | |
24 | }; | |
25 | ||
012c0460 AJ |
26 | struct aspeed_wdt_config { |
27 | u32 ext_pulse_width_mask; | |
28 | }; | |
29 | ||
30 | static const struct aspeed_wdt_config ast2400_config = { | |
31 | .ext_pulse_width_mask = 0xff, | |
32 | }; | |
33 | ||
34 | static const struct aspeed_wdt_config ast2500_config = { | |
35 | .ext_pulse_width_mask = 0xfffff, | |
36 | }; | |
37 | ||
efa859f7 | 38 | static const struct of_device_id aspeed_wdt_of_table[] = { |
012c0460 AJ |
39 | { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config }, |
40 | { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config }, | |
0335532e | 41 | { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config }, |
efa859f7 JS |
42 | { }, |
43 | }; | |
44 | MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); | |
45 | ||
46 | #define WDT_STATUS 0x00 | |
47 | #define WDT_RELOAD_VALUE 0x04 | |
48 | #define WDT_RESTART 0x08 | |
49 | #define WDT_CTRL 0x0C | |
7b2c229a | 50 | #define WDT_CTRL_BOOT_SECONDARY BIT(7) |
efa859f7 JS |
51 | #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) |
52 | #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) | |
b7f0b8ad | 53 | #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) |
efa859f7 JS |
54 | #define WDT_CTRL_1MHZ_CLK BIT(4) |
55 | #define WDT_CTRL_WDT_EXT BIT(3) | |
56 | #define WDT_CTRL_WDT_INTR BIT(2) | |
57 | #define WDT_CTRL_RESET_SYSTEM BIT(1) | |
58 | #define WDT_CTRL_ENABLE BIT(0) | |
59 | ||
012c0460 AJ |
60 | /* |
61 | * WDT_RESET_WIDTH controls the characteristics of the external pulse (if | |
62 | * enabled), specifically: | |
63 | * | |
64 | * * Pulse duration | |
65 | * * Drive mode: push-pull vs open-drain | |
66 | * * Polarity: Active high or active low | |
67 | * | |
68 | * Pulse duration configuration is available on both the AST2400 and AST2500, | |
69 | * though the field changes between SoCs: | |
70 | * | |
71 | * AST2400: Bits 7:0 | |
72 | * AST2500: Bits 19:0 | |
73 | * | |
74 | * This difference is captured in struct aspeed_wdt_config. | |
75 | * | |
76 | * The AST2500 exposes the drive mode and polarity options, but not in a | |
77 | * regular fashion. For read purposes, bit 31 represents active high or low, | |
78 | * and bit 30 represents push-pull or open-drain. With respect to write, magic | |
79 | * values need to be written to the top byte to change the state of the drive | |
80 | * mode and polarity bits. Any other value written to the top byte has no | |
81 | * effect on the state of the drive mode or polarity bits. However, the pulse | |
82 | * width value must be preserved (as desired) if written. | |
83 | */ | |
84 | #define WDT_RESET_WIDTH 0x18 | |
85 | #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) | |
86 | #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) | |
87 | #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) | |
88 | #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) | |
89 | #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) | |
90 | #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) | |
91 | ||
efa859f7 JS |
92 | #define WDT_RESTART_MAGIC 0x4755 |
93 | ||
94 | /* 32 bits at 1MHz, in milliseconds */ | |
95 | #define WDT_MAX_TIMEOUT_MS 4294967 | |
96 | #define WDT_DEFAULT_TIMEOUT 30 | |
97 | #define WDT_RATE_1MHZ 1000000 | |
98 | ||
99 | static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd) | |
100 | { | |
101 | return container_of(wdd, struct aspeed_wdt, wdd); | |
102 | } | |
103 | ||
104 | static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) | |
105 | { | |
106 | wdt->ctrl |= WDT_CTRL_ENABLE; | |
107 | ||
108 | writel(0, wdt->base + WDT_CTRL); | |
109 | writel(count, wdt->base + WDT_RELOAD_VALUE); | |
110 | writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); | |
111 | writel(wdt->ctrl, wdt->base + WDT_CTRL); | |
112 | } | |
113 | ||
114 | static int aspeed_wdt_start(struct watchdog_device *wdd) | |
115 | { | |
116 | struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); | |
117 | ||
118 | aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static int aspeed_wdt_stop(struct watchdog_device *wdd) | |
124 | { | |
125 | struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); | |
126 | ||
127 | wdt->ctrl &= ~WDT_CTRL_ENABLE; | |
128 | writel(wdt->ctrl, wdt->base + WDT_CTRL); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | static int aspeed_wdt_ping(struct watchdog_device *wdd) | |
134 | { | |
135 | struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); | |
136 | ||
137 | writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | static int aspeed_wdt_set_timeout(struct watchdog_device *wdd, | |
143 | unsigned int timeout) | |
144 | { | |
145 | struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); | |
146 | u32 actual; | |
147 | ||
148 | wdd->timeout = timeout; | |
149 | ||
150 | actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000); | |
151 | ||
152 | writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); | |
153 | writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | static int aspeed_wdt_restart(struct watchdog_device *wdd, | |
159 | unsigned long action, void *data) | |
160 | { | |
161 | struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); | |
162 | ||
7b2c229a | 163 | wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY; |
efa859f7 JS |
164 | aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000); |
165 | ||
166 | mdelay(1000); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static const struct watchdog_ops aspeed_wdt_ops = { | |
172 | .start = aspeed_wdt_start, | |
173 | .stop = aspeed_wdt_stop, | |
174 | .ping = aspeed_wdt_ping, | |
175 | .set_timeout = aspeed_wdt_set_timeout, | |
176 | .restart = aspeed_wdt_restart, | |
177 | .owner = THIS_MODULE, | |
178 | }; | |
179 | ||
180 | static const struct watchdog_info aspeed_wdt_info = { | |
181 | .options = WDIOF_KEEPALIVEPING | |
182 | | WDIOF_MAGICCLOSE | |
183 | | WDIOF_SETTIMEOUT, | |
184 | .identity = KBUILD_MODNAME, | |
185 | }; | |
186 | ||
efa859f7 JS |
187 | static int aspeed_wdt_probe(struct platform_device *pdev) |
188 | { | |
012c0460 AJ |
189 | const struct aspeed_wdt_config *config; |
190 | const struct of_device_id *ofdid; | |
efa859f7 JS |
191 | struct aspeed_wdt *wdt; |
192 | struct resource *res; | |
b7f0b8ad CB |
193 | struct device_node *np; |
194 | const char *reset_type; | |
012c0460 | 195 | u32 duration; |
efa859f7 JS |
196 | int ret; |
197 | ||
198 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); | |
199 | if (!wdt) | |
200 | return -ENOMEM; | |
201 | ||
202 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
203 | wdt->base = devm_ioremap_resource(&pdev->dev, res); | |
204 | if (IS_ERR(wdt->base)) | |
205 | return PTR_ERR(wdt->base); | |
206 | ||
207 | /* | |
208 | * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only | |
209 | * runs at 1MHz. We chose to always run at 1MHz, as there's no | |
210 | * good reason to have a faster watchdog counter. | |
211 | */ | |
212 | wdt->wdd.info = &aspeed_wdt_info; | |
213 | wdt->wdd.ops = &aspeed_wdt_ops; | |
214 | wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; | |
215 | wdt->wdd.parent = &pdev->dev; | |
216 | ||
217 | wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; | |
218 | watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev); | |
219 | ||
012c0460 AJ |
220 | np = pdev->dev.of_node; |
221 | ||
222 | ofdid = of_match_node(aspeed_wdt_of_table, np); | |
223 | if (!ofdid) | |
224 | return -EINVAL; | |
225 | config = ofdid->data; | |
226 | ||
b7f0b8ad CB |
227 | wdt->ctrl = WDT_CTRL_1MHZ_CLK; |
228 | ||
efa859f7 JS |
229 | /* |
230 | * Control reset on a per-device basis to ensure the | |
b7f0b8ad | 231 | * host is not affected by a BMC reboot |
efa859f7 | 232 | */ |
b7f0b8ad CB |
233 | ret = of_property_read_string(np, "aspeed,reset-type", &reset_type); |
234 | if (ret) { | |
235 | wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; | |
236 | } else { | |
237 | if (!strcmp(reset_type, "cpu")) | |
afd2a5d9 MM |
238 | wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | |
239 | WDT_CTRL_RESET_SYSTEM; | |
b7f0b8ad | 240 | else if (!strcmp(reset_type, "soc")) |
afd2a5d9 MM |
241 | wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | |
242 | WDT_CTRL_RESET_SYSTEM; | |
b7f0b8ad | 243 | else if (!strcmp(reset_type, "system")) |
afd2a5d9 MM |
244 | wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | |
245 | WDT_CTRL_RESET_SYSTEM; | |
b7f0b8ad CB |
246 | else if (strcmp(reset_type, "none")) |
247 | return -EINVAL; | |
248 | } | |
249 | if (of_property_read_bool(np, "aspeed,external-signal")) | |
250 | wdt->ctrl |= WDT_CTRL_WDT_EXT; | |
7b2c229a MM |
251 | if (of_property_read_bool(np, "aspeed,alt-boot")) |
252 | wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY; | |
b7f0b8ad CB |
253 | |
254 | writel(wdt->ctrl, wdt->base + WDT_CTRL); | |
efa859f7 JS |
255 | |
256 | if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) { | |
257 | aspeed_wdt_start(&wdt->wdd); | |
258 | set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); | |
259 | } | |
260 | ||
0335532e RC |
261 | if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) || |
262 | (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) { | |
012c0460 AJ |
263 | u32 reg = readl(wdt->base + WDT_RESET_WIDTH); |
264 | ||
265 | reg &= config->ext_pulse_width_mask; | |
266 | if (of_property_read_bool(np, "aspeed,ext-push-pull")) | |
267 | reg |= WDT_PUSH_PULL_MAGIC; | |
268 | else | |
269 | reg |= WDT_OPEN_DRAIN_MAGIC; | |
270 | ||
271 | writel(reg, wdt->base + WDT_RESET_WIDTH); | |
272 | ||
273 | reg &= config->ext_pulse_width_mask; | |
274 | if (of_property_read_bool(np, "aspeed,ext-active-high")) | |
275 | reg |= WDT_ACTIVE_HIGH_MAGIC; | |
276 | else | |
277 | reg |= WDT_ACTIVE_LOW_MAGIC; | |
278 | ||
279 | writel(reg, wdt->base + WDT_RESET_WIDTH); | |
280 | } | |
281 | ||
282 | if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) { | |
283 | u32 max_duration = config->ext_pulse_width_mask + 1; | |
284 | ||
285 | if (duration == 0 || duration > max_duration) { | |
286 | dev_err(&pdev->dev, "Invalid pulse duration: %uus\n", | |
287 | duration); | |
288 | duration = max(1U, min(max_duration, duration)); | |
289 | dev_info(&pdev->dev, "Pulse duration set to %uus\n", | |
290 | duration); | |
291 | } | |
292 | ||
293 | /* | |
294 | * The watchdog is always configured with a 1MHz source, so | |
295 | * there is no need to scale the microsecond value. However we | |
296 | * need to offset it - from the datasheet: | |
297 | * | |
298 | * "This register decides the asserting duration of wdt_ext and | |
299 | * wdt_rstarm signal. The default value is 0xFF. It means the | |
300 | * default asserting duration of wdt_ext and wdt_rstarm is | |
301 | * 256us." | |
302 | * | |
303 | * This implies a value of 0 gives a 1us pulse. | |
304 | */ | |
305 | writel(duration - 1, wdt->base + WDT_RESET_WIDTH); | |
306 | } | |
307 | ||
7db1634d | 308 | ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd); |
efa859f7 JS |
309 | if (ret) { |
310 | dev_err(&pdev->dev, "failed to register\n"); | |
311 | return ret; | |
312 | } | |
313 | ||
efa859f7 JS |
314 | return 0; |
315 | } | |
316 | ||
317 | static struct platform_driver aspeed_watchdog_driver = { | |
318 | .probe = aspeed_wdt_probe, | |
efa859f7 JS |
319 | .driver = { |
320 | .name = KBUILD_MODNAME, | |
321 | .of_match_table = of_match_ptr(aspeed_wdt_of_table), | |
322 | }, | |
323 | }; | |
324 | module_platform_driver(aspeed_watchdog_driver); | |
325 | ||
326 | MODULE_DESCRIPTION("Aspeed Watchdog Driver"); | |
327 | MODULE_LICENSE("GPL"); |