[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / at91sam9_wdt.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Watchdog driver for Atmel AT91SAM9x processors.
 *
 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
 *
 */

/*
 * The Watchdog Timer Mode Register can be only written to once. If the
 * timeout need to be set from Linux, be sure that the bootstrap or the
 * bootloader doesn't write to this register.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/types.h>
#include <linux/watchdog.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
#include <linux/bitops.h>
#include <linux/uaccess.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include "at91sam9_wdt.h"

#define DRV_NAME "AT91SAM9 Watchdog"

#define wdt_read(wdt, field) \
	readl_relaxed((wdt)->base + (field))
#define wdt_write(wtd, field, val) \
	writel_relaxed((val), (wdt)->base + (field))

/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
 * use this to convert a watchdog
 * value from/to milliseconds.
 */
#define ticks_to_hz_rounddown(t)	((((t) + 1) * HZ) >> 8)
#define ticks_to_hz_roundup(t)		(((((t) + 1) * HZ) + 255) >> 8)
#define ticks_to_secs(t)		(((t) + 1) >> 8)
#define secs_to_ticks(s)		((s) ? (((s) << 8) - 1) : 0)

#define WDT_MR_RESET	0x3FFF2FFF

/* Watchdog max counter value in ticks */
#define WDT_COUNTER_MAX_TICKS	0xFFF

/* Watchdog max delta/value in secs */
#define WDT_COUNTER_MAX_SECS	ticks_to_secs(WDT_COUNTER_MAX_TICKS)

/* Hardware timeout in seconds */
#define WDT_HW_TIMEOUT 2

/* Timer heartbeat (500ms) */
#define WDT_TIMEOUT	(HZ/2)

/* User land timeout */
#define WDT_HEARTBEAT 15
static int heartbeat;
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
	"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

#define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
struct at91wdt {
	struct watchdog_device wdd;
	void __iomem *base;
	unsigned long next_heartbeat;	/* the next_heartbeat for the timer */
	struct timer_list timer;	/* The timer that pings the watchdog */
	u32 mr;
	u32 mr_mask;
	unsigned long heartbeat;	/* WDT heartbeat in jiffies */
	bool nowayout;
	unsigned int irq;
	struct clk *sclk;
};

/* ......................................................................... */

static irqreturn_t wdt_interrupt(int irq, void *dev_id)
{
	struct at91wdt *wdt = (struct at91wdt *)dev_id;

	if (wdt_read(wdt, AT91_WDT_SR)) {
		pr_crit("at91sam9 WDT software reset\n");
		emergency_restart();
		pr_crit("Reboot didn't ?????\n");
	}

	return IRQ_HANDLED;
}

/*
 * Reload the watchdog timer.  (ie, pat the watchdog)
 */
static inline void at91_wdt_reset(struct at91wdt *wdt)
{
	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
}

/*
 * Timer tick
 */
static void at91_ping(struct timer_list *t)
{
	struct at91wdt *wdt = from_timer(wdt, t, timer);
	if (time_before(jiffies, wdt->next_heartbeat) ||
	    !watchdog_active(&wdt->wdd)) {
		at91_wdt_reset(wdt);
		mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
	} else {
		pr_crit("I will reset your machine !\n");
	}
}

static int at91_wdt_start(struct watchdog_device *wdd)
{
	struct at91wdt *wdt = to_wdt(wdd);
	/* calculate when the next userspace timeout will be */
	wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
	return 0;
}

static int at91_wdt_stop(struct watchdog_device *wdd)
{
	/* The watchdog timer hardware can not be stopped... */
	return 0;
}

static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
{
	wdd->timeout = new_timeout;
	return at91_wdt_start(wdd);
}

static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt)
{
	u32 tmp;
	u32 delta;
	u32 value;
	int err;
	u32 mask = wdt->mr_mask;
	unsigned long min_heartbeat = 1;
	unsigned long max_heartbeat;
	struct device *dev = &pdev->dev;

	tmp = wdt_read(wdt, AT91_WDT_MR);
	if ((tmp & mask) != (wdt->mr & mask)) {
		if (tmp == WDT_MR_RESET) {
			wdt_write(wdt, AT91_WDT_MR, wdt->mr);
			tmp = wdt_read(wdt, AT91_WDT_MR);
		}
	}

	if (tmp & AT91_WDT_WDDIS) {
		if (wdt->mr & AT91_WDT_WDDIS)
			return 0;
		dev_err(dev, "watchdog is disabled\n");
		return -EINVAL;
	}

	value = tmp & AT91_WDT_WDV;
	delta = (tmp & AT91_WDT_WDD) >> 16;

	if (delta < value)
		min_heartbeat = ticks_to_hz_roundup(value - delta);

	max_heartbeat = ticks_to_hz_rounddown(value);
	if (!max_heartbeat) {
		dev_err(dev,
			"heartbeat is too small for the system to handle it correctly\n");
		return -EINVAL;
	}

	/*
	 * Try to reset the watchdog counter 4 or 2 times more often than
	 * actually requested, to avoid spurious watchdog reset.
	 * If this is not possible because of the min_heartbeat value, reset
	 * it at the min_heartbeat period.
	 */
	if ((max_heartbeat / 4) >= min_heartbeat)
		wdt->heartbeat = max_heartbeat / 4;
	else if ((max_heartbeat / 2) >= min_heartbeat)
		wdt->heartbeat = max_heartbeat / 2;
	else
		wdt->heartbeat = min_heartbeat;

	if (max_heartbeat < min_heartbeat + 4)
		dev_warn(dev,
			 "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");

	if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
		err = request_irq(wdt->irq, wdt_interrupt,
				  IRQF_SHARED | IRQF_IRQPOLL |
				  IRQF_NO_SUSPEND,
				  pdev->name, wdt);
		if (err)
			return err;
	}

	if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
		dev_warn(dev,
			 "watchdog already configured differently (mr = %x expecting %x)\n",
			 tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);

	timer_setup(&wdt->timer, at91_ping, 0);

	/*
	 * Use min_heartbeat the first time to avoid spurious watchdog reset:
	 * we don't know for how long the watchdog counter is running, and
	 *  - resetting it right now might trigger a watchdog fault reset
	 *  - waiting for heartbeat time might lead to a watchdog timeout
	 *    reset
	 */
	mod_timer(&wdt->timer, jiffies + min_heartbeat);

	/* Try to set timeout from device tree first */
	if (watchdog_init_timeout(&wdt->wdd, 0, dev))
		watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
	watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
	err = watchdog_register_device(&wdt->wdd);
	if (err)
		goto out_stop_timer;

	wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;

	return 0;

out_stop_timer:
	del_timer(&wdt->timer);
	return err;
}

/* ......................................................................... */

static const struct watchdog_info at91_wdt_info = {
	.identity	= DRV_NAME,
	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
						WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops at91_wdt_ops = {
	.owner =	THIS_MODULE,
	.start =	at91_wdt_start,
	.stop =		at91_wdt_stop,
	.set_timeout =	at91_wdt_set_timeout,
};

#if defined(CONFIG_OF)
static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
{
	u32 min = 0;
	u32 max = WDT_COUNTER_MAX_SECS;
	const char *tmp;

	/* Get the interrupts property */
	wdt->irq = irq_of_parse_and_map(np, 0);
	if (!wdt->irq)
		dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");

	if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
					&max)) {
		if (!max || max > WDT_COUNTER_MAX_SECS)
			max = WDT_COUNTER_MAX_SECS;

		if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
						0, &min)) {
			if (min >= max)
				min = max - 1;
		}
	}

	min = secs_to_ticks(min);
	max = secs_to_ticks(max);

	wdt->mr_mask = 0x3FFFFFFF;
	wdt->mr = 0;
	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	    !strcmp(tmp, "software")) {
		wdt->mr |= AT91_WDT_WDFIEN;
		wdt->mr_mask &= ~AT91_WDT_WDRPROC;
	} else {
		wdt->mr |= AT91_WDT_WDRSTEN;
	}

	if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
	    !strcmp(tmp, "proc"))
		wdt->mr |= AT91_WDT_WDRPROC;

	if (of_property_read_bool(np, "atmel,disable")) {
		wdt->mr |= AT91_WDT_WDDIS;
		wdt->mr_mask &= AT91_WDT_WDDIS;
	}

	if (of_property_read_bool(np, "atmel,idle-halt"))
		wdt->mr |= AT91_WDT_WDIDLEHLT;

	if (of_property_read_bool(np, "atmel,dbg-halt"))
		wdt->mr |= AT91_WDT_WDDBGHLT;

	wdt->mr |= max | ((max - min) << 16);

	return 0;
}
#else
static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt)
{
	return 0;
}
#endif

static int __init at91wdt_probe(struct platform_device *pdev)
{
	int err;
	struct at91wdt *wdt;

	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
	if (!wdt)
		return -ENOMEM;

	wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD |
		  AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT;
	wdt->mr_mask = 0x3FFFFFFF;
	wdt->nowayout = nowayout;
	wdt->wdd.parent = &pdev->dev;
	wdt->wdd.info = &at91_wdt_info;
	wdt->wdd.ops = &at91_wdt_ops;
	wdt->wdd.timeout = WDT_HEARTBEAT;
	wdt->wdd.min_timeout = 1;
	wdt->wdd.max_timeout = 0xFFFF;

	wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	wdt->sclk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt->sclk))
		return PTR_ERR(wdt->sclk);

	err = clk_prepare_enable(wdt->sclk);
	if (err) {
		dev_err(&pdev->dev, "Could not enable slow clock\n");
		return err;
	}

	if (pdev->dev.of_node) {
		err = of_at91wdt_init(pdev->dev.of_node, wdt);
		if (err)
			goto err_clk;
	}

	err = at91_wdt_init(pdev, wdt);
	if (err)
		goto err_clk;

	platform_set_drvdata(pdev, wdt);

	pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
		wdt->wdd.timeout, wdt->nowayout);

	return 0;

err_clk:
	clk_disable_unprepare(wdt->sclk);

	return err;
}

static int __exit at91wdt_remove(struct platform_device *pdev)
{
	struct at91wdt *wdt = platform_get_drvdata(pdev);
	watchdog_unregister_device(&wdt->wdd);

	pr_warn("I quit now, hardware will probably reboot!\n");
	del_timer(&wdt->timer);
	clk_disable_unprepare(wdt->sclk);

	return 0;
}

#if defined(CONFIG_OF)
static const struct of_device_id at91_wdt_dt_ids[] = {
	{ .compatible = "atmel,at91sam9260-wdt" },
	{ /* sentinel */ }
};

MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
#endif

static struct platform_driver at91wdt_driver = {
	.remove		= __exit_p(at91wdt_remove),
	.driver		= {
		.name	= "at91_wdt",
		.of_match_table = of_match_ptr(at91_wdt_dt_ids),
	},
};

module_platform_driver_probe(at91wdt_driver, at91wdt_probe);

MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
MODULE_LICENSE("GPL");
Commit	Line	Data
2e62c498	1	// SPDX-License-Identifier: GPL-2.0+
e6bb42e3 RC	2	/*
	3	* Watchdog driver for Atmel AT91SAM9x processors.
	4	*
	5	* Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
	6	*
e6bb42e3 RC	7	*/
	8
	9	/*
	10	* The Watchdog Timer Mode Register can be only written to once. If the
	11	* timeout need to be set from Linux, be sure that the bootstrap or the
	12	* bootloader doesn't write to this register.
	13	*/
	14
27c766aa JP	15	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	16
a97a09bd	17	#include <linux/clk.h>
e6bb42e3	18	#include <linux/errno.h>
e6bb42e3	19	#include <linux/init.h>
5161b31d	20	#include <linux/interrupt.h>
2af29b78	21	#include <linux/io.h>
e6bb42e3	22	#include <linux/kernel.h>
e6bb42e3 RC	23	#include <linux/module.h>
	24	#include <linux/moduleparam.h>
	25	#include <linux/platform_device.h>
5161b31d	26	#include <linux/reboot.h>
e6bb42e3 RC	27	#include <linux/types.h>
	28	#include <linux/watchdog.h>
	29	#include <linux/jiffies.h>
	30	#include <linux/timer.h>
	31	#include <linux/bitops.h>
	32	#include <linux/uaccess.h>
be49bbae	33	#include <linux/of.h>
5161b31d	34	#include <linux/of_irq.h>
e6bb42e3	35
e7b39145	36	#include "at91sam9_wdt.h"
e6bb42e3 RC	37
	38	#define DRV_NAME "AT91SAM9 Watchdog"
	39
5161b31d	40	#define wdt_read(wdt, field) \
feccebe9	41	readl_relaxed((wdt)->base + (field))
5161b31d	42	#define wdt_write(wtd, field, val) \
feccebe9	43	writel_relaxed((val), (wdt)->base + (field))
c1c30a29	44
e6bb42e3 RC	45	/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
	46	* use this to convert a watchdog
	47	* value from/to milliseconds.
	48	*/
5161b31d BB	49	#define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8)
	50	#define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8)
	51	#define ticks_to_secs(t) (((t) + 1) >> 8)
1444797f	52	#define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
5161b31d BB	53
	54	#define WDT_MR_RESET 0x3FFF2FFF
	55
	56	/* Watchdog max counter value in ticks */
	57	#define WDT_COUNTER_MAX_TICKS 0xFFF
	58
	59	/* Watchdog max delta/value in secs */
	60	#define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS)
e6bb42e3 RC	61
	62	/* Hardware timeout in seconds */
	63	#define WDT_HW_TIMEOUT 2
	64
	65	/* Timer heartbeat (500ms) */
	66	#define WDT_TIMEOUT (HZ/2)
	67
	68	/* User land timeout */
	69	#define WDT_HEARTBEAT 15
c1fd5f64	70	static int heartbeat;
e6bb42e3 RC	71	module_param(heartbeat, int, 0);
	72	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
	73	"(default = " __MODULE_STRING(WDT_HEARTBEAT) ")");
	74
86a1e189 WVS	75	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	76	module_param(nowayout, bool, 0);
e6bb42e3 RC	77	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	78	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	79
5161b31d BB	80	#define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd)
	81	struct at91wdt {
	82	struct watchdog_device wdd;
c1c30a29	83	void __iomem *base;
e6bb42e3	84	unsigned long next_heartbeat; /* the next_heartbeat for the timer */
e6bb42e3	85	struct timer_list timer; /* The timer that pings the watchdog */
5161b31d BB	86	u32 mr;
	87	u32 mr_mask;
	88	unsigned long heartbeat; /* WDT heartbeat in jiffies */
	89	bool nowayout;
	90	unsigned int irq;
a97a09bd	91	struct clk *sclk;
5161b31d	92	};
e6bb42e3 RC	93
	94	/* ......................................................................... */
	95
5161b31d BB	96	static irqreturn_t wdt_interrupt(int irq, void *dev_id)
	97	{
	98	struct at91wdt wdt = (struct at91wdt )dev_id;
	99
	100	if (wdt_read(wdt, AT91_WDT_SR)) {
	101	pr_crit("at91sam9 WDT software reset\n");
	102	emergency_restart();
	103	pr_crit("Reboot didn't ?????\n");
	104	}
	105
	106	return IRQ_HANDLED;
	107	}
	108
e6bb42e3 RC	109	/*
	110	* Reload the watchdog timer. (ie, pat the watchdog)
	111	*/
5161b31d	112	static inline void at91_wdt_reset(struct at91wdt *wdt)
e6bb42e3	113	{
5161b31d	114	wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY \| AT91_WDT_WDRSTT);
e6bb42e3 RC	115	}
	116
	117	/*
	118	* Timer tick
	119	*/
e99e88a9	120	static void at91_ping(struct timer_list *t)
e6bb42e3	121	{
e99e88a9	122	struct at91wdt *wdt = from_timer(wdt, t, timer);
5161b31d BB	123	if (time_before(jiffies, wdt->next_heartbeat) \|\|
	124	!watchdog_active(&wdt->wdd)) {
	125	at91_wdt_reset(wdt);
	126	mod_timer(&wdt->timer, jiffies + wdt->heartbeat);
	127	} else {
27c766aa	128	pr_crit("I will reset your machine !\n");
5161b31d	129	}
490ac7af	130	}
e6bb42e3	131
490ac7af WY	132	static int at91_wdt_start(struct watchdog_device *wdd)
490ac7af WY	133	{
5161b31d BB	134	struct at91wdt *wdt = to_wdt(wdd);
	135	/* calculate when the next userspace timeout will be */
	136	wdt->next_heartbeat = jiffies + wdd->timeout * HZ;
490ac7af	137	return 0;
e6bb42e3 RC	138	}
e6bb42e3 RC	139
490ac7af	140	static int at91_wdt_stop(struct watchdog_device *wdd)
e6bb42e3	141	{
490ac7af WY	142	/* The watchdog timer hardware can not be stopped... */
	143	return 0;
	144	}
e6bb42e3	145
490ac7af WY	146	static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout)
	147	{
	148	wdd->timeout = new_timeout;
5161b31d	149	return at91_wdt_start(wdd);
e6bb42e3 RC	150	}
e6bb42e3 RC	151
5161b31d	152	static int at91_wdt_init(struct platform_device pdev, struct at91wdt wdt)
e6bb42e3	153	{
5161b31d BB	154	u32 tmp;
	155	u32 delta;
	156	u32 value;
	157	int err;
	158	u32 mask = wdt->mr_mask;
	159	unsigned long min_heartbeat = 1;
f72fa00f	160	unsigned long max_heartbeat;
5161b31d BB	161	struct device *dev = &pdev->dev;
	162
	163	tmp = wdt_read(wdt, AT91_WDT_MR);
	164	if ((tmp & mask) != (wdt->mr & mask)) {
	165	if (tmp == WDT_MR_RESET) {
	166	wdt_write(wdt, AT91_WDT_MR, wdt->mr);
	167	tmp = wdt_read(wdt, AT91_WDT_MR);
	168	}
	169	}
	170
	171	if (tmp & AT91_WDT_WDDIS) {
	172	if (wdt->mr & AT91_WDT_WDDIS)
	173	return 0;
	174	dev_err(dev, "watchdog is disabled\n");
	175	return -EINVAL;
	176	}
	177
	178	value = tmp & AT91_WDT_WDV;
	179	delta = (tmp & AT91_WDT_WDD) >> 16;
	180
	181	if (delta < value)
	182	min_heartbeat = ticks_to_hz_roundup(value - delta);
	183
f72fa00f BB	184	max_heartbeat = ticks_to_hz_rounddown(value);
f72fa00f BB	185	if (!max_heartbeat) {
5161b31d BB	186	dev_err(dev,
	187	"heartbeat is too small for the system to handle it correctly\n");
	188	return -EINVAL;
	189	}
	190
f72fa00f BB	191	/*
	192	* Try to reset the watchdog counter 4 or 2 times more often than
	193	* actually requested, to avoid spurious watchdog reset.
	194	* If this is not possible because of the min_heartbeat value, reset
	195	* it at the min_heartbeat period.
	196	*/
	197	if ((max_heartbeat / 4) >= min_heartbeat)
	198	wdt->heartbeat = max_heartbeat / 4;
	199	else if ((max_heartbeat / 2) >= min_heartbeat)
	200	wdt->heartbeat = max_heartbeat / 2;
	201	else
5161b31d	202	wdt->heartbeat = min_heartbeat;
f72fa00f BB	203
f72fa00f BB	204	if (max_heartbeat < min_heartbeat + 4)
5161b31d BB	205	dev_warn(dev,
5161b31d BB	206	"min heartbeat and max heartbeat might be too close for the system to handle it correctly\n");
e6bb42e3	207
5161b31d BB	208	if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) {
5161b31d BB	209	err = request_irq(wdt->irq, wdt_interrupt,
d677772e BB	210	IRQF_SHARED \| IRQF_IRQPOLL \|
d677772e BB	211	IRQF_NO_SUSPEND,
5161b31d BB	212	pdev->name, wdt);
	213	if (err)
	214	return err;
	215	}
	216
	217	if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask))
	218	dev_warn(dev,
	219	"watchdog already configured differently (mr = %x expecting %x)\n",
	220	tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask);
	221
e99e88a9	222	timer_setup(&wdt->timer, at91_ping, 0);
a04c3f01 BB	223
	224	/*
	225	* Use min_heartbeat the first time to avoid spurious watchdog reset:
	226	* we don't know for how long the watchdog counter is running, and
	227	* - resetting it right now might trigger a watchdog fault reset
	228	* - waiting for heartbeat time might lead to a watchdog timeout
	229	* reset
	230	*/
	231	mod_timer(&wdt->timer, jiffies + min_heartbeat);
5161b31d BB	232
	233	/* Try to set timeout from device tree first */
	234	if (watchdog_init_timeout(&wdt->wdd, 0, dev))
	235	watchdog_init_timeout(&wdt->wdd, heartbeat, dev);
	236	watchdog_set_nowayout(&wdt->wdd, wdt->nowayout);
	237	err = watchdog_register_device(&wdt->wdd);
	238	if (err)
	239	goto out_stop_timer;
	240
	241	wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ;
e6bb42e3 RC	242
e6bb42e3 RC	243	return 0;
5161b31d BB	244
	245	out_stop_timer:
	246	del_timer(&wdt->timer);
	247	return err;
e6bb42e3 RC	248	}
e6bb42e3 RC	249
490ac7af WY	250	/* ......................................................................... */
490ac7af WY	251
e6bb42e3 RC	252	static const struct watchdog_info at91_wdt_info = {
e6bb42e3 RC	253	.identity = DRV_NAME,
e73a7802 WVS	254	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
e73a7802 WVS	255	WDIOF_MAGICCLOSE,
e6bb42e3 RC	256	};
e6bb42e3 RC	257
490ac7af WY	258	static const struct watchdog_ops at91_wdt_ops = {
	259	.owner = THIS_MODULE,
	260	.start = at91_wdt_start,
	261	.stop = at91_wdt_stop,
490ac7af	262	.set_timeout = at91_wdt_set_timeout,
e6bb42e3 RC	263	};
e6bb42e3 RC	264
5161b31d BB	265	#if defined(CONFIG_OF)
	266	static int of_at91wdt_init(struct device_node np, struct at91wdt wdt)
	267	{
	268	u32 min = 0;
	269	u32 max = WDT_COUNTER_MAX_SECS;
	270	const char *tmp;
	271
	272	/* Get the interrupts property */
	273	wdt->irq = irq_of_parse_and_map(np, 0);
	274	if (!wdt->irq)
	275	dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n");
	276
	277	if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0,
	278	&max)) {
	279	if (!max \|\| max > WDT_COUNTER_MAX_SECS)
	280	max = WDT_COUNTER_MAX_SECS;
	281
	282	if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec",
	283	0, &min)) {
	284	if (min >= max)
	285	min = max - 1;
	286	}
	287	}
	288
	289	min = secs_to_ticks(min);
	290	max = secs_to_ticks(max);
	291
	292	wdt->mr_mask = 0x3FFFFFFF;
	293	wdt->mr = 0;
	294	if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
	295	!strcmp(tmp, "software")) {
	296	wdt->mr \|= AT91_WDT_WDFIEN;
	297	wdt->mr_mask &= ~AT91_WDT_WDRPROC;
	298	} else {
	299	wdt->mr \|= AT91_WDT_WDRSTEN;
	300	}
	301
	302	if (!of_property_read_string(np, "atmel,reset-type", &tmp) &&
	303	!strcmp(tmp, "proc"))
	304	wdt->mr \|= AT91_WDT_WDRPROC;
	305
	306	if (of_property_read_bool(np, "atmel,disable")) {
	307	wdt->mr \|= AT91_WDT_WDDIS;
	308	wdt->mr_mask &= AT91_WDT_WDDIS;
	309	}
	310
	311	if (of_property_read_bool(np, "atmel,idle-halt"))
	312	wdt->mr \|= AT91_WDT_WDIDLEHLT;
	313
	314	if (of_property_read_bool(np, "atmel,dbg-halt"))
	315	wdt->mr \|= AT91_WDT_WDDBGHLT;
	316
	317	wdt->mr \|= max \| ((max - min) << 16);
	318
	319	return 0;
	320	}
	321	#else
	322	static inline int of_at91wdt_init(struct device_node np, struct at91wdt wdt)
	323	{
	324	return 0;
	325	}
	326	#endif
e6bb42e3 RC	327
	328	static int __init at91wdt_probe(struct platform_device *pdev)
	329	{
5161b31d BB	330	int err;
5161b31d BB	331	struct at91wdt *wdt;
e6bb42e3	332
5161b31d BB	333	wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
5161b31d BB	334	if (!wdt)
c1c30a29	335	return -ENOMEM;
c1c30a29	336
5161b31d BB	337	wdt->mr = (WDT_HW_TIMEOUT * 256) \| AT91_WDT_WDRSTEN \| AT91_WDT_WDD \|
	338	AT91_WDT_WDDBGHLT \| AT91_WDT_WDIDLEHLT;
	339	wdt->mr_mask = 0x3FFFFFFF;
	340	wdt->nowayout = nowayout;
	341	wdt->wdd.parent = &pdev->dev;
	342	wdt->wdd.info = &at91_wdt_info;
	343	wdt->wdd.ops = &at91_wdt_ops;
	344	wdt->wdd.timeout = WDT_HEARTBEAT;
	345	wdt->wdd.min_timeout = 1;
	346	wdt->wdd.max_timeout = 0xFFFF;
490ac7af	347
0f0a6a28	348	wdt->base = devm_platform_ioremap_resource(pdev, 0);
5161b31d BB	349	if (IS_ERR(wdt->base))
	350	return PTR_ERR(wdt->base);
	351
a97a09bd AB	352	wdt->sclk = devm_clk_get(&pdev->dev, NULL);
	353	if (IS_ERR(wdt->sclk))
	354	return PTR_ERR(wdt->sclk);
	355
	356	err = clk_prepare_enable(wdt->sclk);
	357	if (err) {
	358	dev_err(&pdev->dev, "Could not enable slow clock\n");
	359	return err;
	360	}
	361
5161b31d BB	362	if (pdev->dev.of_node) {
	363	err = of_at91wdt_init(pdev->dev.of_node, wdt);
	364	if (err)
a97a09bd	365	goto err_clk;
5161b31d	366	}
e6bb42e3	367
5161b31d BB	368	err = at91_wdt_init(pdev, wdt);
5161b31d BB	369	if (err)
a97a09bd	370	goto err_clk;
e6bb42e3	371
5161b31d	372	platform_set_drvdata(pdev, wdt);
e6bb42e3	373
27c766aa	374	pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n",
5161b31d	375	wdt->wdd.timeout, wdt->nowayout);
e6bb42e3 RC	376
e6bb42e3 RC	377	return 0;
a97a09bd AB	378
	379	err_clk:
	380	clk_disable_unprepare(wdt->sclk);
	381
	382	return err;
e6bb42e3 RC	383	}
	384
	385	static int __exit at91wdt_remove(struct platform_device *pdev)
	386	{
5161b31d BB	387	struct at91wdt *wdt = platform_get_drvdata(pdev);
5161b31d BB	388	watchdog_unregister_device(&wdt->wdd);
e6bb42e3	389
490ac7af	390	pr_warn("I quit now, hardware will probably reboot!\n");
5161b31d	391	del_timer(&wdt->timer);
a97a09bd	392	clk_disable_unprepare(wdt->sclk);
e6bb42e3	393
490ac7af	394	return 0;
e6bb42e3 RC	395	}
e6bb42e3 RC	396
be49bbae	397	#if defined(CONFIG_OF)
6c41e474	398	static const struct of_device_id at91_wdt_dt_ids[] = {
be49bbae FP	399	{ .compatible = "atmel,at91sam9260-wdt" },
	400	{ /* sentinel */ }
	401	};
	402
	403	MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids);
	404	#endif
	405
e6bb42e3 RC	406	static struct platform_driver at91wdt_driver = {
e6bb42e3 RC	407	.remove = __exit_p(at91wdt_remove),
e6bb42e3 RC	408	.driver = {
e6bb42e3 RC	409	.name = "at91_wdt",
be49bbae	410	.of_match_table = of_match_ptr(at91_wdt_dt_ids),
e6bb42e3 RC	411	},
	412	};
	413
1cb9204c	414	module_platform_driver_probe(at91wdt_driver, at91wdt_probe);
e6bb42e3 RC	415
	416	MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>");
	417	MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors");
	418	MODULE_LICENSE("GPL");