]>
Commit | Line | Data |
---|---|---|
e6bb42e3 RC |
1 | /* |
2 | * Watchdog driver for Atmel AT91SAM9x processors. | |
3 | * | |
4 | * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * The Watchdog Timer Mode Register can be only written to once. If the | |
14 | * timeout need to be set from Linux, be sure that the bootstrap or the | |
15 | * bootloader doesn't write to this register. | |
16 | */ | |
17 | ||
27c766aa JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
e6bb42e3 | 20 | #include <linux/errno.h> |
e6bb42e3 | 21 | #include <linux/init.h> |
5161b31d | 22 | #include <linux/interrupt.h> |
2af29b78 | 23 | #include <linux/io.h> |
e6bb42e3 | 24 | #include <linux/kernel.h> |
e6bb42e3 RC |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/platform_device.h> | |
5161b31d | 28 | #include <linux/reboot.h> |
e6bb42e3 RC |
29 | #include <linux/types.h> |
30 | #include <linux/watchdog.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/timer.h> | |
33 | #include <linux/bitops.h> | |
34 | #include <linux/uaccess.h> | |
be49bbae | 35 | #include <linux/of.h> |
5161b31d | 36 | #include <linux/of_irq.h> |
e6bb42e3 | 37 | |
e7b39145 | 38 | #include "at91sam9_wdt.h" |
e6bb42e3 RC |
39 | |
40 | #define DRV_NAME "AT91SAM9 Watchdog" | |
41 | ||
5161b31d BB |
42 | #define wdt_read(wdt, field) \ |
43 | __raw_readl((wdt)->base + (field)) | |
44 | #define wdt_write(wtd, field, val) \ | |
45 | __raw_writel((val), (wdt)->base + (field)) | |
c1c30a29 | 46 | |
e6bb42e3 RC |
47 | /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz, |
48 | * use this to convert a watchdog | |
49 | * value from/to milliseconds. | |
50 | */ | |
5161b31d BB |
51 | #define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8) |
52 | #define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8) | |
53 | #define ticks_to_secs(t) (((t) + 1) >> 8) | |
1444797f | 54 | #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0) |
5161b31d BB |
55 | |
56 | #define WDT_MR_RESET 0x3FFF2FFF | |
57 | ||
58 | /* Watchdog max counter value in ticks */ | |
59 | #define WDT_COUNTER_MAX_TICKS 0xFFF | |
60 | ||
61 | /* Watchdog max delta/value in secs */ | |
62 | #define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS) | |
e6bb42e3 RC |
63 | |
64 | /* Hardware timeout in seconds */ | |
65 | #define WDT_HW_TIMEOUT 2 | |
66 | ||
67 | /* Timer heartbeat (500ms) */ | |
68 | #define WDT_TIMEOUT (HZ/2) | |
69 | ||
70 | /* User land timeout */ | |
71 | #define WDT_HEARTBEAT 15 | |
c1fd5f64 | 72 | static int heartbeat; |
e6bb42e3 RC |
73 | module_param(heartbeat, int, 0); |
74 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. " | |
75 | "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")"); | |
76 | ||
86a1e189 WVS |
77 | static bool nowayout = WATCHDOG_NOWAYOUT; |
78 | module_param(nowayout, bool, 0); | |
e6bb42e3 RC |
79 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
80 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
81 | ||
5161b31d BB |
82 | #define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd) |
83 | struct at91wdt { | |
84 | struct watchdog_device wdd; | |
c1c30a29 | 85 | void __iomem *base; |
e6bb42e3 | 86 | unsigned long next_heartbeat; /* the next_heartbeat for the timer */ |
e6bb42e3 | 87 | struct timer_list timer; /* The timer that pings the watchdog */ |
5161b31d BB |
88 | u32 mr; |
89 | u32 mr_mask; | |
90 | unsigned long heartbeat; /* WDT heartbeat in jiffies */ | |
91 | bool nowayout; | |
92 | unsigned int irq; | |
93 | }; | |
e6bb42e3 RC |
94 | |
95 | /* ......................................................................... */ | |
96 | ||
5161b31d BB |
97 | static irqreturn_t wdt_interrupt(int irq, void *dev_id) |
98 | { | |
99 | struct at91wdt *wdt = (struct at91wdt *)dev_id; | |
100 | ||
101 | if (wdt_read(wdt, AT91_WDT_SR)) { | |
102 | pr_crit("at91sam9 WDT software reset\n"); | |
103 | emergency_restart(); | |
104 | pr_crit("Reboot didn't ?????\n"); | |
105 | } | |
106 | ||
107 | return IRQ_HANDLED; | |
108 | } | |
109 | ||
e6bb42e3 RC |
110 | /* |
111 | * Reload the watchdog timer. (ie, pat the watchdog) | |
112 | */ | |
5161b31d | 113 | static inline void at91_wdt_reset(struct at91wdt *wdt) |
e6bb42e3 | 114 | { |
5161b31d | 115 | wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); |
e6bb42e3 RC |
116 | } |
117 | ||
118 | /* | |
119 | * Timer tick | |
120 | */ | |
121 | static void at91_ping(unsigned long data) | |
122 | { | |
5161b31d BB |
123 | struct at91wdt *wdt = (struct at91wdt *)data; |
124 | if (time_before(jiffies, wdt->next_heartbeat) || | |
125 | !watchdog_active(&wdt->wdd)) { | |
126 | at91_wdt_reset(wdt); | |
127 | mod_timer(&wdt->timer, jiffies + wdt->heartbeat); | |
128 | } else { | |
27c766aa | 129 | pr_crit("I will reset your machine !\n"); |
5161b31d | 130 | } |
490ac7af | 131 | } |
e6bb42e3 | 132 | |
490ac7af WY |
133 | static int at91_wdt_start(struct watchdog_device *wdd) |
134 | { | |
5161b31d BB |
135 | struct at91wdt *wdt = to_wdt(wdd); |
136 | /* calculate when the next userspace timeout will be */ | |
137 | wdt->next_heartbeat = jiffies + wdd->timeout * HZ; | |
490ac7af | 138 | return 0; |
e6bb42e3 RC |
139 | } |
140 | ||
490ac7af | 141 | static int at91_wdt_stop(struct watchdog_device *wdd) |
e6bb42e3 | 142 | { |
490ac7af WY |
143 | /* The watchdog timer hardware can not be stopped... */ |
144 | return 0; | |
145 | } | |
e6bb42e3 | 146 | |
490ac7af WY |
147 | static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout) |
148 | { | |
149 | wdd->timeout = new_timeout; | |
5161b31d | 150 | return at91_wdt_start(wdd); |
e6bb42e3 RC |
151 | } |
152 | ||
5161b31d | 153 | static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt) |
e6bb42e3 | 154 | { |
5161b31d BB |
155 | u32 tmp; |
156 | u32 delta; | |
157 | u32 value; | |
158 | int err; | |
159 | u32 mask = wdt->mr_mask; | |
160 | unsigned long min_heartbeat = 1; | |
f72fa00f | 161 | unsigned long max_heartbeat; |
5161b31d BB |
162 | struct device *dev = &pdev->dev; |
163 | ||
164 | tmp = wdt_read(wdt, AT91_WDT_MR); | |
165 | if ((tmp & mask) != (wdt->mr & mask)) { | |
166 | if (tmp == WDT_MR_RESET) { | |
167 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); | |
168 | tmp = wdt_read(wdt, AT91_WDT_MR); | |
169 | } | |
170 | } | |
171 | ||
172 | if (tmp & AT91_WDT_WDDIS) { | |
173 | if (wdt->mr & AT91_WDT_WDDIS) | |
174 | return 0; | |
175 | dev_err(dev, "watchdog is disabled\n"); | |
176 | return -EINVAL; | |
177 | } | |
178 | ||
179 | value = tmp & AT91_WDT_WDV; | |
180 | delta = (tmp & AT91_WDT_WDD) >> 16; | |
181 | ||
182 | if (delta < value) | |
183 | min_heartbeat = ticks_to_hz_roundup(value - delta); | |
184 | ||
f72fa00f BB |
185 | max_heartbeat = ticks_to_hz_rounddown(value); |
186 | if (!max_heartbeat) { | |
5161b31d BB |
187 | dev_err(dev, |
188 | "heartbeat is too small for the system to handle it correctly\n"); | |
189 | return -EINVAL; | |
190 | } | |
191 | ||
f72fa00f BB |
192 | /* |
193 | * Try to reset the watchdog counter 4 or 2 times more often than | |
194 | * actually requested, to avoid spurious watchdog reset. | |
195 | * If this is not possible because of the min_heartbeat value, reset | |
196 | * it at the min_heartbeat period. | |
197 | */ | |
198 | if ((max_heartbeat / 4) >= min_heartbeat) | |
199 | wdt->heartbeat = max_heartbeat / 4; | |
200 | else if ((max_heartbeat / 2) >= min_heartbeat) | |
201 | wdt->heartbeat = max_heartbeat / 2; | |
202 | else | |
5161b31d | 203 | wdt->heartbeat = min_heartbeat; |
f72fa00f BB |
204 | |
205 | if (max_heartbeat < min_heartbeat + 4) | |
5161b31d BB |
206 | dev_warn(dev, |
207 | "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n"); | |
e6bb42e3 | 208 | |
5161b31d BB |
209 | if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) { |
210 | err = request_irq(wdt->irq, wdt_interrupt, | |
d677772e BB |
211 | IRQF_SHARED | IRQF_IRQPOLL | |
212 | IRQF_NO_SUSPEND, | |
5161b31d BB |
213 | pdev->name, wdt); |
214 | if (err) | |
215 | return err; | |
216 | } | |
217 | ||
218 | if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask)) | |
219 | dev_warn(dev, | |
220 | "watchdog already configured differently (mr = %x expecting %x)\n", | |
221 | tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask); | |
222 | ||
223 | setup_timer(&wdt->timer, at91_ping, (unsigned long)wdt); | |
a04c3f01 BB |
224 | |
225 | /* | |
226 | * Use min_heartbeat the first time to avoid spurious watchdog reset: | |
227 | * we don't know for how long the watchdog counter is running, and | |
228 | * - resetting it right now might trigger a watchdog fault reset | |
229 | * - waiting for heartbeat time might lead to a watchdog timeout | |
230 | * reset | |
231 | */ | |
232 | mod_timer(&wdt->timer, jiffies + min_heartbeat); | |
5161b31d BB |
233 | |
234 | /* Try to set timeout from device tree first */ | |
235 | if (watchdog_init_timeout(&wdt->wdd, 0, dev)) | |
236 | watchdog_init_timeout(&wdt->wdd, heartbeat, dev); | |
237 | watchdog_set_nowayout(&wdt->wdd, wdt->nowayout); | |
238 | err = watchdog_register_device(&wdt->wdd); | |
239 | if (err) | |
240 | goto out_stop_timer; | |
241 | ||
242 | wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ; | |
e6bb42e3 RC |
243 | |
244 | return 0; | |
5161b31d BB |
245 | |
246 | out_stop_timer: | |
247 | del_timer(&wdt->timer); | |
248 | return err; | |
e6bb42e3 RC |
249 | } |
250 | ||
490ac7af WY |
251 | /* ......................................................................... */ |
252 | ||
e6bb42e3 RC |
253 | static const struct watchdog_info at91_wdt_info = { |
254 | .identity = DRV_NAME, | |
e73a7802 WVS |
255 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
256 | WDIOF_MAGICCLOSE, | |
e6bb42e3 RC |
257 | }; |
258 | ||
490ac7af WY |
259 | static const struct watchdog_ops at91_wdt_ops = { |
260 | .owner = THIS_MODULE, | |
261 | .start = at91_wdt_start, | |
262 | .stop = at91_wdt_stop, | |
490ac7af | 263 | .set_timeout = at91_wdt_set_timeout, |
e6bb42e3 RC |
264 | }; |
265 | ||
5161b31d BB |
266 | #if defined(CONFIG_OF) |
267 | static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) | |
268 | { | |
269 | u32 min = 0; | |
270 | u32 max = WDT_COUNTER_MAX_SECS; | |
271 | const char *tmp; | |
272 | ||
273 | /* Get the interrupts property */ | |
274 | wdt->irq = irq_of_parse_and_map(np, 0); | |
275 | if (!wdt->irq) | |
276 | dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n"); | |
277 | ||
278 | if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0, | |
279 | &max)) { | |
280 | if (!max || max > WDT_COUNTER_MAX_SECS) | |
281 | max = WDT_COUNTER_MAX_SECS; | |
282 | ||
283 | if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec", | |
284 | 0, &min)) { | |
285 | if (min >= max) | |
286 | min = max - 1; | |
287 | } | |
288 | } | |
289 | ||
290 | min = secs_to_ticks(min); | |
291 | max = secs_to_ticks(max); | |
292 | ||
293 | wdt->mr_mask = 0x3FFFFFFF; | |
294 | wdt->mr = 0; | |
295 | if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && | |
296 | !strcmp(tmp, "software")) { | |
297 | wdt->mr |= AT91_WDT_WDFIEN; | |
298 | wdt->mr_mask &= ~AT91_WDT_WDRPROC; | |
299 | } else { | |
300 | wdt->mr |= AT91_WDT_WDRSTEN; | |
301 | } | |
302 | ||
303 | if (!of_property_read_string(np, "atmel,reset-type", &tmp) && | |
304 | !strcmp(tmp, "proc")) | |
305 | wdt->mr |= AT91_WDT_WDRPROC; | |
306 | ||
307 | if (of_property_read_bool(np, "atmel,disable")) { | |
308 | wdt->mr |= AT91_WDT_WDDIS; | |
309 | wdt->mr_mask &= AT91_WDT_WDDIS; | |
310 | } | |
311 | ||
312 | if (of_property_read_bool(np, "atmel,idle-halt")) | |
313 | wdt->mr |= AT91_WDT_WDIDLEHLT; | |
314 | ||
315 | if (of_property_read_bool(np, "atmel,dbg-halt")) | |
316 | wdt->mr |= AT91_WDT_WDDBGHLT; | |
317 | ||
318 | wdt->mr |= max | ((max - min) << 16); | |
319 | ||
320 | return 0; | |
321 | } | |
322 | #else | |
323 | static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) | |
324 | { | |
325 | return 0; | |
326 | } | |
327 | #endif | |
e6bb42e3 RC |
328 | |
329 | static int __init at91wdt_probe(struct platform_device *pdev) | |
330 | { | |
c1c30a29 | 331 | struct resource *r; |
5161b31d BB |
332 | int err; |
333 | struct at91wdt *wdt; | |
e6bb42e3 | 334 | |
5161b31d BB |
335 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); |
336 | if (!wdt) | |
c1c30a29 | 337 | return -ENOMEM; |
c1c30a29 | 338 | |
5161b31d BB |
339 | wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD | |
340 | AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT; | |
341 | wdt->mr_mask = 0x3FFFFFFF; | |
342 | wdt->nowayout = nowayout; | |
343 | wdt->wdd.parent = &pdev->dev; | |
344 | wdt->wdd.info = &at91_wdt_info; | |
345 | wdt->wdd.ops = &at91_wdt_ops; | |
346 | wdt->wdd.timeout = WDT_HEARTBEAT; | |
347 | wdt->wdd.min_timeout = 1; | |
348 | wdt->wdd.max_timeout = 0xFFFF; | |
490ac7af | 349 | |
5161b31d BB |
350 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
351 | wdt->base = devm_ioremap_resource(&pdev->dev, r); | |
352 | if (IS_ERR(wdt->base)) | |
353 | return PTR_ERR(wdt->base); | |
354 | ||
355 | if (pdev->dev.of_node) { | |
356 | err = of_at91wdt_init(pdev->dev.of_node, wdt); | |
357 | if (err) | |
358 | return err; | |
359 | } | |
e6bb42e3 | 360 | |
5161b31d BB |
361 | err = at91_wdt_init(pdev, wdt); |
362 | if (err) | |
363 | return err; | |
e6bb42e3 | 364 | |
5161b31d | 365 | platform_set_drvdata(pdev, wdt); |
e6bb42e3 | 366 | |
27c766aa | 367 | pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n", |
5161b31d | 368 | wdt->wdd.timeout, wdt->nowayout); |
e6bb42e3 RC |
369 | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static int __exit at91wdt_remove(struct platform_device *pdev) | |
374 | { | |
5161b31d BB |
375 | struct at91wdt *wdt = platform_get_drvdata(pdev); |
376 | watchdog_unregister_device(&wdt->wdd); | |
e6bb42e3 | 377 | |
490ac7af | 378 | pr_warn("I quit now, hardware will probably reboot!\n"); |
5161b31d | 379 | del_timer(&wdt->timer); |
e6bb42e3 | 380 | |
490ac7af | 381 | return 0; |
e6bb42e3 RC |
382 | } |
383 | ||
be49bbae | 384 | #if defined(CONFIG_OF) |
6c41e474 | 385 | static const struct of_device_id at91_wdt_dt_ids[] = { |
be49bbae FP |
386 | { .compatible = "atmel,at91sam9260-wdt" }, |
387 | { /* sentinel */ } | |
388 | }; | |
389 | ||
390 | MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids); | |
391 | #endif | |
392 | ||
e6bb42e3 RC |
393 | static struct platform_driver at91wdt_driver = { |
394 | .remove = __exit_p(at91wdt_remove), | |
e6bb42e3 RC |
395 | .driver = { |
396 | .name = "at91_wdt", | |
be49bbae | 397 | .of_match_table = of_match_ptr(at91_wdt_dt_ids), |
e6bb42e3 RC |
398 | }, |
399 | }; | |
400 | ||
1cb9204c | 401 | module_platform_driver_probe(at91wdt_driver, at91wdt_probe); |
e6bb42e3 RC |
402 | |
403 | MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>"); | |
404 | MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors"); | |
405 | MODULE_LICENSE("GPL"); |