projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 2e62c498 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| eaa595cb | 2 | /* |
| e7b39145 | 3 | * drivers/watchdog/at91sam9_wdt.h |
| eaa595cb | 4 | * |
| 3d73e893 AV |
5 | * Copyright (C) 2007 Andrew Victor |
| 6 | * Copyright (C) 2007 Atmel Corporation. | |
| d615a6fd | 7 | * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries |
| 3d73e893 | 8 | * |
| eaa595cb AV |
9 | * Watchdog Timer (WDT) - System peripherals regsters. |
| 10 | * Based on AT91SAM9261 datasheet revision D. | |
| d615a6fd | 11 | * Based on SAM9X60 datasheet. |
| eaa595cb | 12 | * |
| eaa595cb AV |
13 | */ |
| 14 | ||
| 15 | #ifndef AT91_WDT_H | |
| 16 | #define AT91_WDT_H | |
| 17 | ||
| d615a6fd EH |
18 | #include <linux/bits.h> |
| 19 | ||
| c1c30a29 | 20 | #define AT91_WDT_CR 0x00 /* Watchdog Control Register */ |
| d615a6fd EH |
21 | #define AT91_WDT_WDRSTT BIT(0) /* Restart */ |
| 22 | #define AT91_WDT_KEY (0xa5UL << 24) /* KEY Password */ | |
| eaa595cb | 23 | |
| c1c30a29 | 24 | #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */ |
| d615a6fd EH |
25 | #define AT91_WDT_WDV (0xfffUL << 0) /* Counter Value */ |
| 26 | #define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV) | |
| bb44aa09 EH |
27 | #define AT91_SAM9X60_PERIODRST BIT(4) /* Period Reset */ |
| 28 | #define AT91_SAM9X60_RPTHRST BIT(5) /* Minimum Restart Period */ | |
| d615a6fd | 29 | #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */ |
| bb44aa09 | 30 | #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */ |
| d615a6fd EH |
31 | #define AT91_WDT_WDRSTEN BIT(13) /* Reset Processor */ |
| 32 | #define AT91_WDT_WDRPROC BIT(14) /* Timer Restart */ | |
| 33 | #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */ | |
| 34 | #define AT91_WDT_WDD (0xfffUL << 16) /* Delta Value */ | |
| 35 | #define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD) | |
| 36 | #define AT91_WDT_WDDBGHLT BIT(28) /* Debug Halt */ | |
| 37 | #define AT91_WDT_WDIDLEHLT BIT(29) /* Idle Halt */ | |
| eaa595cb | 38 | |
| d615a6fd EH |
39 | #define AT91_WDT_SR 0x08 /* Watchdog Status Register */ |
| 40 | #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */ | |
| 41 | #define AT91_WDT_WDERR BIT(1) /* Watchdog Error */ | |
| eaa595cb | 42 | |
| bb44aa09 EH |
43 | /* Watchdog Timer Value Register */ |
| 44 | #define AT91_SAM9X60_VR 0x08 | |
| 45 | ||
| 46 | /* Watchdog Window Level Register */ | |
| 47 | #define AT91_SAM9X60_WLR 0x0c | |
| 48 | /* Watchdog Period Value */ | |
| 49 | #define AT91_SAM9X60_COUNTER (0xfffUL << 0) | |
| 50 | #define AT91_SAM9X60_SET_COUNTER(x) ((x) & AT91_SAM9X60_COUNTER) | |
| 51 | ||
| 52 | /* Interrupt Enable Register */ | |
| 53 | #define AT91_SAM9X60_IER 0x14 | |
| 54 | /* Period Interrupt Enable */ | |
| 55 | #define AT91_SAM9X60_PERINT BIT(0) | |
| 56 | /* Interrupt Disable Register */ | |
| 57 | #define AT91_SAM9X60_IDR 0x18 | |
| 58 | /* Interrupt Status Register */ | |
| 59 | #define AT91_SAM9X60_ISR 0x1c | |
| 60 | ||
| eaa595cb | 61 | #endif |