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f50a7f3d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b466ee89 GZ |
2 | /* |
3 | * Watchdog driver for CSR Atlas7 | |
4 | * | |
5 | * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company. | |
b466ee89 GZ |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/moduleparam.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/watchdog.h> | |
15 | ||
16 | #define ATLAS7_TIMER_WDT_INDEX 5 | |
17 | #define ATLAS7_WDT_DEFAULT_TIMEOUT 20 | |
18 | ||
19 | #define ATLAS7_WDT_CNT_CTRL (0 + 4 * ATLAS7_TIMER_WDT_INDEX) | |
20 | #define ATLAS7_WDT_CNT_MATCH (0x18 + 4 * ATLAS7_TIMER_WDT_INDEX) | |
21 | #define ATLAS7_WDT_CNT (0x48 + 4 * ATLAS7_TIMER_WDT_INDEX) | |
22 | #define ATLAS7_WDT_CNT_EN (BIT(0) | BIT(1)) | |
23 | #define ATLAS7_WDT_EN 0x64 | |
24 | ||
25 | static unsigned int timeout = ATLAS7_WDT_DEFAULT_TIMEOUT; | |
26 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
27 | ||
28 | module_param(timeout, uint, 0); | |
29 | module_param(nowayout, bool, 0); | |
30 | ||
31 | MODULE_PARM_DESC(timeout, "Default watchdog timeout (in seconds)"); | |
32 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
33 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
34 | ||
35 | struct atlas7_wdog { | |
36 | struct device *dev; | |
37 | void __iomem *base; | |
38 | unsigned long tick_rate; | |
39 | struct clk *clk; | |
40 | }; | |
41 | ||
42 | static unsigned int atlas7_wdt_gettimeleft(struct watchdog_device *wdd) | |
43 | { | |
44 | struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); | |
45 | u32 counter, match, delta; | |
46 | ||
47 | counter = readl(wdt->base + ATLAS7_WDT_CNT); | |
48 | match = readl(wdt->base + ATLAS7_WDT_CNT_MATCH); | |
49 | delta = match - counter; | |
50 | ||
51 | return delta / wdt->tick_rate; | |
52 | } | |
53 | ||
54 | static int atlas7_wdt_ping(struct watchdog_device *wdd) | |
55 | { | |
56 | struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); | |
57 | u32 counter, match, delta; | |
58 | ||
59 | counter = readl(wdt->base + ATLAS7_WDT_CNT); | |
60 | delta = wdd->timeout * wdt->tick_rate; | |
61 | match = counter + delta; | |
62 | ||
63 | writel(match, wdt->base + ATLAS7_WDT_CNT_MATCH); | |
64 | ||
65 | return 0; | |
66 | } | |
67 | ||
68 | static int atlas7_wdt_enable(struct watchdog_device *wdd) | |
69 | { | |
70 | struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); | |
71 | ||
72 | atlas7_wdt_ping(wdd); | |
73 | ||
74 | writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) | ATLAS7_WDT_CNT_EN, | |
75 | wdt->base + ATLAS7_WDT_CNT_CTRL); | |
76 | writel(1, wdt->base + ATLAS7_WDT_EN); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int atlas7_wdt_disable(struct watchdog_device *wdd) | |
82 | { | |
83 | struct atlas7_wdog *wdt = watchdog_get_drvdata(wdd); | |
84 | ||
85 | writel(0, wdt->base + ATLAS7_WDT_EN); | |
86 | writel(readl(wdt->base + ATLAS7_WDT_CNT_CTRL) & ~ATLAS7_WDT_CNT_EN, | |
87 | wdt->base + ATLAS7_WDT_CNT_CTRL); | |
88 | ||
89 | return 0; | |
90 | } | |
91 | ||
92 | static int atlas7_wdt_settimeout(struct watchdog_device *wdd, unsigned int to) | |
93 | { | |
94 | wdd->timeout = to; | |
95 | ||
96 | return 0; | |
97 | } | |
98 | ||
99 | #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) | |
100 | ||
101 | static const struct watchdog_info atlas7_wdt_ident = { | |
102 | .options = OPTIONS, | |
103 | .firmware_version = 0, | |
104 | .identity = "atlas7 Watchdog", | |
105 | }; | |
106 | ||
b893e344 | 107 | static const struct watchdog_ops atlas7_wdt_ops = { |
b466ee89 GZ |
108 | .owner = THIS_MODULE, |
109 | .start = atlas7_wdt_enable, | |
110 | .stop = atlas7_wdt_disable, | |
111 | .get_timeleft = atlas7_wdt_gettimeleft, | |
112 | .ping = atlas7_wdt_ping, | |
113 | .set_timeout = atlas7_wdt_settimeout, | |
114 | }; | |
115 | ||
116 | static struct watchdog_device atlas7_wdd = { | |
117 | .info = &atlas7_wdt_ident, | |
118 | .ops = &atlas7_wdt_ops, | |
119 | .timeout = ATLAS7_WDT_DEFAULT_TIMEOUT, | |
120 | }; | |
121 | ||
122 | static const struct of_device_id atlas7_wdt_ids[] = { | |
123 | { .compatible = "sirf,atlas7-tick"}, | |
124 | {} | |
125 | }; | |
126 | ||
f332ce5d GR |
127 | static void atlas7_clk_disable_unprepare(void *data) |
128 | { | |
129 | clk_disable_unprepare(data); | |
130 | } | |
131 | ||
b466ee89 GZ |
132 | static int atlas7_wdt_probe(struct platform_device *pdev) |
133 | { | |
f332ce5d | 134 | struct device *dev = &pdev->dev; |
b466ee89 | 135 | struct atlas7_wdog *wdt; |
b466ee89 GZ |
136 | struct clk *clk; |
137 | int ret; | |
138 | ||
f332ce5d | 139 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
b466ee89 GZ |
140 | if (!wdt) |
141 | return -ENOMEM; | |
0f0a6a28 | 142 | wdt->base = devm_platform_ioremap_resource(pdev, 0); |
b466ee89 GZ |
143 | if (IS_ERR(wdt->base)) |
144 | return PTR_ERR(wdt->base); | |
145 | ||
f332ce5d | 146 | clk = devm_clk_get(dev, NULL); |
b466ee89 GZ |
147 | if (IS_ERR(clk)) |
148 | return PTR_ERR(clk); | |
149 | ret = clk_prepare_enable(clk); | |
150 | if (ret) { | |
f332ce5d GR |
151 | dev_err(dev, "clk enable failed\n"); |
152 | return ret; | |
b466ee89 | 153 | } |
f332ce5d GR |
154 | ret = devm_add_action_or_reset(dev, atlas7_clk_disable_unprepare, clk); |
155 | if (ret) | |
156 | return ret; | |
b466ee89 GZ |
157 | |
158 | /* disable watchdog hardware */ | |
159 | writel(0, wdt->base + ATLAS7_WDT_CNT_CTRL); | |
160 | ||
161 | wdt->tick_rate = clk_get_rate(clk); | |
f332ce5d GR |
162 | if (!wdt->tick_rate) |
163 | return -EINVAL; | |
ccc8208d | 164 | |
b466ee89 GZ |
165 | wdt->clk = clk; |
166 | atlas7_wdd.min_timeout = 1; | |
167 | atlas7_wdd.max_timeout = UINT_MAX / wdt->tick_rate; | |
168 | ||
f332ce5d | 169 | watchdog_init_timeout(&atlas7_wdd, 0, dev); |
b466ee89 GZ |
170 | watchdog_set_nowayout(&atlas7_wdd, nowayout); |
171 | ||
172 | watchdog_set_drvdata(&atlas7_wdd, wdt); | |
173 | platform_set_drvdata(pdev, &atlas7_wdd); | |
174 | ||
f332ce5d GR |
175 | watchdog_stop_on_reboot(&atlas7_wdd); |
176 | watchdog_stop_on_unregister(&atlas7_wdd); | |
177 | return devm_watchdog_register_device(dev, &atlas7_wdd); | |
b466ee89 GZ |
178 | } |
179 | ||
180 | static int __maybe_unused atlas7_wdt_suspend(struct device *dev) | |
181 | { | |
182 | /* | |
183 | * NOTE:timer controller registers settings are saved | |
184 | * and restored back by the timer-atlas7.c | |
185 | */ | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static int __maybe_unused atlas7_wdt_resume(struct device *dev) | |
190 | { | |
191 | struct watchdog_device *wdd = dev_get_drvdata(dev); | |
192 | ||
193 | /* | |
194 | * NOTE: Since timer controller registers settings are saved | |
195 | * and restored back by the timer-atlas7.c, so we need not | |
196 | * update WD settings except refreshing timeout. | |
197 | */ | |
198 | atlas7_wdt_ping(wdd); | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | static SIMPLE_DEV_PM_OPS(atlas7_wdt_pm_ops, | |
204 | atlas7_wdt_suspend, atlas7_wdt_resume); | |
205 | ||
206 | MODULE_DEVICE_TABLE(of, atlas7_wdt_ids); | |
207 | ||
208 | static struct platform_driver atlas7_wdt_driver = { | |
209 | .driver = { | |
210 | .name = "atlas7-wdt", | |
211 | .pm = &atlas7_wdt_pm_ops, | |
212 | .of_match_table = atlas7_wdt_ids, | |
213 | }, | |
214 | .probe = atlas7_wdt_probe, | |
b466ee89 GZ |
215 | }; |
216 | module_platform_driver(atlas7_wdt_driver); | |
217 | ||
218 | MODULE_DESCRIPTION("CSRatlas7 watchdog driver"); | |
219 | MODULE_AUTHOR("Guo Zeng <Guo.Zeng@csr.com>"); | |
220 | MODULE_LICENSE("GPL v2"); | |
221 | MODULE_ALIAS("platform:atlas7-wdt"); |