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938d0a84 LR |
1 | /* |
2 | * Watchdog driver for Broadcom BCM2835 | |
3 | * | |
4 | * "bcm2708_wdog" driver written by Luke Diamand that was obtained from | |
5 | * branch "rpi-3.6.y" of git://github.com/raspberrypi/linux.git was used | |
6 | * as a hardware reference for the Broadcom BCM2835 watchdog timer. | |
7 | * | |
8 | * Copyright (C) 2013 Lubomir Rintel <lkundrak@v3.sk> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
33a9f5bc EA |
16 | #include <linux/delay.h> |
17 | #include <linux/reboot.h> | |
938d0a84 LR |
18 | #include <linux/types.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/watchdog.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/of_address.h> | |
33a9f5bc | 24 | #include <linux/of_platform.h> |
938d0a84 LR |
25 | |
26 | #define PM_RSTC 0x1c | |
33a9f5bc | 27 | #define PM_RSTS 0x20 |
938d0a84 LR |
28 | #define PM_WDOG 0x24 |
29 | ||
30 | #define PM_PASSWORD 0x5a000000 | |
31 | ||
32 | #define PM_WDOG_TIME_SET 0x000fffff | |
33 | #define PM_RSTC_WRCFG_CLR 0xffffffcf | |
33a9f5bc | 34 | #define PM_RSTS_HADWRH_SET 0x00000040 |
938d0a84 LR |
35 | #define PM_RSTC_WRCFG_SET 0x00000030 |
36 | #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 | |
37 | #define PM_RSTC_RESET 0x00000102 | |
38 | ||
898e6861 NT |
39 | /* |
40 | * The Raspberry Pi firmware uses the RSTS register to know which partiton | |
41 | * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10. | |
42 | * Partiton 63 is a special partition used by the firmware to indicate halt. | |
43 | */ | |
44 | #define PM_RSTS_RASPBERRYPI_HALT 0x555 | |
45 | ||
938d0a84 LR |
46 | #define SECS_TO_WDOG_TICKS(x) ((x) << 16) |
47 | #define WDOG_TICKS_TO_SECS(x) ((x) >> 16) | |
48 | ||
49 | struct bcm2835_wdt { | |
50 | void __iomem *base; | |
51 | spinlock_t lock; | |
33a9f5bc | 52 | struct notifier_block restart_handler; |
938d0a84 LR |
53 | }; |
54 | ||
55 | static unsigned int heartbeat; | |
56 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
57 | ||
054ae194 RV |
58 | static bool bcm2835_wdt_is_running(struct bcm2835_wdt *wdt) |
59 | { | |
60 | uint32_t cur; | |
61 | ||
62 | cur = readl(wdt->base + PM_RSTC); | |
63 | ||
64 | return !!(cur & PM_RSTC_WRCFG_FULL_RESET); | |
65 | } | |
66 | ||
938d0a84 LR |
67 | static int bcm2835_wdt_start(struct watchdog_device *wdog) |
68 | { | |
69 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
70 | uint32_t cur; | |
71 | unsigned long flags; | |
72 | ||
73 | spin_lock_irqsave(&wdt->lock, flags); | |
74 | ||
75 | writel_relaxed(PM_PASSWORD | (SECS_TO_WDOG_TICKS(wdog->timeout) & | |
76 | PM_WDOG_TIME_SET), wdt->base + PM_WDOG); | |
77 | cur = readl_relaxed(wdt->base + PM_RSTC); | |
78 | writel_relaxed(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | | |
79 | PM_RSTC_WRCFG_FULL_RESET, wdt->base + PM_RSTC); | |
80 | ||
81 | spin_unlock_irqrestore(&wdt->lock, flags); | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
86 | static int bcm2835_wdt_stop(struct watchdog_device *wdog) | |
87 | { | |
88 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
89 | ||
90 | writel_relaxed(PM_PASSWORD | PM_RSTC_RESET, wdt->base + PM_RSTC); | |
938d0a84 LR |
91 | return 0; |
92 | } | |
93 | ||
938d0a84 LR |
94 | static unsigned int bcm2835_wdt_get_timeleft(struct watchdog_device *wdog) |
95 | { | |
96 | struct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog); | |
97 | ||
98 | uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); | |
99 | return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET); | |
100 | } | |
101 | ||
aea4b477 | 102 | static const struct watchdog_ops bcm2835_wdt_ops = { |
938d0a84 LR |
103 | .owner = THIS_MODULE, |
104 | .start = bcm2835_wdt_start, | |
105 | .stop = bcm2835_wdt_stop, | |
938d0a84 LR |
106 | .get_timeleft = bcm2835_wdt_get_timeleft, |
107 | }; | |
108 | ||
aea4b477 | 109 | static const struct watchdog_info bcm2835_wdt_info = { |
938d0a84 LR |
110 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | |
111 | WDIOF_KEEPALIVEPING, | |
112 | .identity = "Broadcom BCM2835 Watchdog timer", | |
113 | }; | |
114 | ||
115 | static struct watchdog_device bcm2835_wdt_wdd = { | |
116 | .info = &bcm2835_wdt_info, | |
117 | .ops = &bcm2835_wdt_ops, | |
118 | .min_timeout = 1, | |
119 | .max_timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
120 | .timeout = WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), | |
121 | }; | |
122 | ||
33a9f5bc EA |
123 | static int |
124 | bcm2835_restart(struct notifier_block *this, unsigned long mode, void *cmd) | |
125 | { | |
126 | struct bcm2835_wdt *wdt = container_of(this, struct bcm2835_wdt, | |
127 | restart_handler); | |
128 | u32 val; | |
129 | ||
130 | /* use a timeout of 10 ticks (~150us) */ | |
131 | writel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG); | |
132 | val = readl_relaxed(wdt->base + PM_RSTC); | |
133 | val &= PM_RSTC_WRCFG_CLR; | |
134 | val |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET; | |
135 | writel_relaxed(val, wdt->base + PM_RSTC); | |
136 | ||
137 | /* No sleeping, possibly atomic. */ | |
138 | mdelay(1); | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | /* | |
144 | * We can't really power off, but if we do the normal reset scheme, and | |
145 | * indicate to bootcode.bin not to reboot, then most of the chip will be | |
146 | * powered off. | |
147 | */ | |
148 | static void bcm2835_power_off(void) | |
149 | { | |
150 | struct device_node *np = | |
151 | of_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm-wdt"); | |
152 | struct platform_device *pdev = of_find_device_by_node(np); | |
153 | struct bcm2835_wdt *wdt = platform_get_drvdata(pdev); | |
154 | u32 val; | |
155 | ||
156 | /* | |
157 | * We set the watchdog hard reset bit here to distinguish this reset | |
158 | * from the normal (full) reset. bootcode.bin will not reboot after a | |
159 | * hard reset. | |
160 | */ | |
161 | val = readl_relaxed(wdt->base + PM_RSTS); | |
898e6861 | 162 | val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT; |
33a9f5bc EA |
163 | writel_relaxed(val, wdt->base + PM_RSTS); |
164 | ||
165 | /* Continue with normal reset mechanism */ | |
166 | bcm2835_restart(&wdt->restart_handler, REBOOT_HARD, NULL); | |
167 | } | |
168 | ||
938d0a84 LR |
169 | static int bcm2835_wdt_probe(struct platform_device *pdev) |
170 | { | |
171 | struct device *dev = &pdev->dev; | |
172 | struct device_node *np = dev->of_node; | |
173 | struct bcm2835_wdt *wdt; | |
174 | int err; | |
175 | ||
176 | wdt = devm_kzalloc(dev, sizeof(struct bcm2835_wdt), GFP_KERNEL); | |
8deea830 | 177 | if (!wdt) |
938d0a84 | 178 | return -ENOMEM; |
938d0a84 LR |
179 | platform_set_drvdata(pdev, wdt); |
180 | ||
181 | spin_lock_init(&wdt->lock); | |
182 | ||
183 | wdt->base = of_iomap(np, 0); | |
184 | if (!wdt->base) { | |
185 | dev_err(dev, "Failed to remap watchdog regs"); | |
186 | return -ENODEV; | |
187 | } | |
188 | ||
189 | watchdog_set_drvdata(&bcm2835_wdt_wdd, wdt); | |
190 | watchdog_init_timeout(&bcm2835_wdt_wdd, heartbeat, dev); | |
191 | watchdog_set_nowayout(&bcm2835_wdt_wdd, nowayout); | |
6551881c | 192 | bcm2835_wdt_wdd.parent = &pdev->dev; |
054ae194 RV |
193 | if (bcm2835_wdt_is_running(wdt)) { |
194 | /* | |
195 | * The currently active timeout value (set by the | |
196 | * bootloader) may be different from the module | |
197 | * heartbeat parameter or the value in device | |
198 | * tree. But we just need to set WDOG_HW_RUNNING, | |
199 | * because then the framework will "immediately" ping | |
200 | * the device, updating the timeout. | |
201 | */ | |
202 | set_bit(WDOG_HW_RUNNING, &bcm2835_wdt_wdd.status); | |
203 | } | |
938d0a84 LR |
204 | err = watchdog_register_device(&bcm2835_wdt_wdd); |
205 | if (err) { | |
206 | dev_err(dev, "Failed to register watchdog device"); | |
207 | iounmap(wdt->base); | |
208 | return err; | |
209 | } | |
210 | ||
33a9f5bc EA |
211 | wdt->restart_handler.notifier_call = bcm2835_restart; |
212 | wdt->restart_handler.priority = 128; | |
213 | register_restart_handler(&wdt->restart_handler); | |
214 | if (pm_power_off == NULL) | |
215 | pm_power_off = bcm2835_power_off; | |
216 | ||
938d0a84 LR |
217 | dev_info(dev, "Broadcom BCM2835 watchdog timer"); |
218 | return 0; | |
219 | } | |
220 | ||
221 | static int bcm2835_wdt_remove(struct platform_device *pdev) | |
222 | { | |
223 | struct bcm2835_wdt *wdt = platform_get_drvdata(pdev); | |
224 | ||
33a9f5bc EA |
225 | unregister_restart_handler(&wdt->restart_handler); |
226 | if (pm_power_off == bcm2835_power_off) | |
227 | pm_power_off = NULL; | |
938d0a84 LR |
228 | watchdog_unregister_device(&bcm2835_wdt_wdd); |
229 | iounmap(wdt->base); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | static void bcm2835_wdt_shutdown(struct platform_device *pdev) | |
235 | { | |
236 | bcm2835_wdt_stop(&bcm2835_wdt_wdd); | |
237 | } | |
238 | ||
239 | static const struct of_device_id bcm2835_wdt_of_match[] = { | |
240 | { .compatible = "brcm,bcm2835-pm-wdt", }, | |
241 | {}, | |
242 | }; | |
243 | MODULE_DEVICE_TABLE(of, bcm2835_wdt_of_match); | |
244 | ||
245 | static struct platform_driver bcm2835_wdt_driver = { | |
246 | .probe = bcm2835_wdt_probe, | |
247 | .remove = bcm2835_wdt_remove, | |
248 | .shutdown = bcm2835_wdt_shutdown, | |
249 | .driver = { | |
250 | .name = "bcm2835-wdt", | |
938d0a84 LR |
251 | .of_match_table = bcm2835_wdt_of_match, |
252 | }, | |
253 | }; | |
254 | module_platform_driver(bcm2835_wdt_driver); | |
255 | ||
256 | module_param(heartbeat, uint, 0); | |
257 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); | |
258 | ||
259 | module_param(nowayout, bool, 0); | |
260 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
261 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
262 | ||
263 | MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>"); | |
264 | MODULE_DESCRIPTION("Driver for Broadcom BCM2835 watchdog timer"); | |
265 | MODULE_LICENSE("GPL"); |