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2e62c498 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
7a3629fe JC |
2 | /* |
3 | * Copyright (C) 2015 Broadcom Corporation | |
4 | * | |
7a3629fe JC |
5 | */ |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/pm.h> | |
14 | #include <linux/watchdog.h> | |
15 | ||
16 | #define WDT_START_1 0xff00 | |
17 | #define WDT_START_2 0x00ff | |
18 | #define WDT_STOP_1 0xee00 | |
19 | #define WDT_STOP_2 0x00ee | |
20 | ||
21 | #define WDT_TIMEOUT_REG 0x0 | |
22 | #define WDT_CMD_REG 0x4 | |
23 | ||
24 | #define WDT_MIN_TIMEOUT 1 /* seconds */ | |
25 | #define WDT_DEFAULT_TIMEOUT 30 /* seconds */ | |
26 | #define WDT_DEFAULT_RATE 27000000 | |
27 | ||
28 | struct bcm7038_watchdog { | |
29 | void __iomem *base; | |
30 | struct watchdog_device wdd; | |
31 | u32 rate; | |
32 | struct clk *clk; | |
33 | }; | |
34 | ||
35 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
36 | ||
e379c219 ÁFR |
37 | static inline void bcm7038_wdt_write(u32 value, void __iomem *addr) |
38 | { | |
39 | /* MIPS chips strapped for BE will automagically configure the | |
40 | * peripheral registers for CPU-native byte order. | |
41 | */ | |
42 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) | |
43 | __raw_writel(value, addr); | |
44 | else | |
45 | writel_relaxed(value, addr); | |
46 | } | |
47 | ||
48 | static inline u32 bcm7038_wdt_read(void __iomem *addr) | |
49 | { | |
50 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) | |
51 | return __raw_readl(addr); | |
52 | else | |
53 | return readl_relaxed(addr); | |
54 | } | |
55 | ||
7a3629fe JC |
56 | static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog) |
57 | { | |
58 | struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); | |
59 | u32 timeout; | |
60 | ||
61 | timeout = wdt->rate * wdog->timeout; | |
62 | ||
e379c219 | 63 | bcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG); |
7a3629fe JC |
64 | } |
65 | ||
66 | static int bcm7038_wdt_ping(struct watchdog_device *wdog) | |
67 | { | |
68 | struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); | |
69 | ||
e379c219 ÁFR |
70 | bcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG); |
71 | bcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG); | |
7a3629fe JC |
72 | |
73 | return 0; | |
74 | } | |
75 | ||
76 | static int bcm7038_wdt_start(struct watchdog_device *wdog) | |
77 | { | |
78 | bcm7038_wdt_set_timeout_reg(wdog); | |
79 | bcm7038_wdt_ping(wdog); | |
80 | ||
81 | return 0; | |
82 | } | |
83 | ||
84 | static int bcm7038_wdt_stop(struct watchdog_device *wdog) | |
85 | { | |
86 | struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); | |
87 | ||
e379c219 ÁFR |
88 | bcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG); |
89 | bcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG); | |
7a3629fe JC |
90 | |
91 | return 0; | |
92 | } | |
93 | ||
94 | static int bcm7038_wdt_set_timeout(struct watchdog_device *wdog, | |
95 | unsigned int t) | |
96 | { | |
97 | /* Can't modify timeout value if watchdog timer is running */ | |
98 | bcm7038_wdt_stop(wdog); | |
99 | wdog->timeout = t; | |
100 | bcm7038_wdt_start(wdog); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static unsigned int bcm7038_wdt_get_timeleft(struct watchdog_device *wdog) | |
106 | { | |
107 | struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); | |
108 | u32 time_left; | |
109 | ||
e379c219 | 110 | time_left = bcm7038_wdt_read(wdt->base + WDT_CMD_REG); |
7a3629fe JC |
111 | |
112 | return time_left / wdt->rate; | |
113 | } | |
114 | ||
6c368932 | 115 | static const struct watchdog_info bcm7038_wdt_info = { |
7a3629fe JC |
116 | .identity = "Broadcom BCM7038 Watchdog Timer", |
117 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | | |
118 | WDIOF_MAGICCLOSE | |
119 | }; | |
120 | ||
85f15cfc | 121 | static const struct watchdog_ops bcm7038_wdt_ops = { |
7a3629fe JC |
122 | .owner = THIS_MODULE, |
123 | .start = bcm7038_wdt_start, | |
124 | .stop = bcm7038_wdt_stop, | |
125 | .set_timeout = bcm7038_wdt_set_timeout, | |
126 | .get_timeleft = bcm7038_wdt_get_timeleft, | |
127 | }; | |
128 | ||
69656dcd GR |
129 | static void bcm7038_clk_disable_unprepare(void *data) |
130 | { | |
131 | clk_disable_unprepare(data); | |
132 | } | |
133 | ||
7a3629fe JC |
134 | static int bcm7038_wdt_probe(struct platform_device *pdev) |
135 | { | |
136 | struct device *dev = &pdev->dev; | |
137 | struct bcm7038_watchdog *wdt; | |
7a3629fe JC |
138 | int err; |
139 | ||
140 | wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); | |
141 | if (!wdt) | |
142 | return -ENOMEM; | |
143 | ||
144 | platform_set_drvdata(pdev, wdt); | |
145 | ||
0f0a6a28 | 146 | wdt->base = devm_platform_ioremap_resource(pdev, 0); |
7a3629fe JC |
147 | if (IS_ERR(wdt->base)) |
148 | return PTR_ERR(wdt->base); | |
149 | ||
150 | wdt->clk = devm_clk_get(dev, NULL); | |
151 | /* If unable to get clock, use default frequency */ | |
152 | if (!IS_ERR(wdt->clk)) { | |
dd0a18ca | 153 | err = clk_prepare_enable(wdt->clk); |
69656dcd GR |
154 | if (err) |
155 | return err; | |
156 | err = devm_add_action_or_reset(dev, | |
157 | bcm7038_clk_disable_unprepare, | |
158 | wdt->clk); | |
dd0a18ca FE |
159 | if (err) |
160 | return err; | |
7a3629fe JC |
161 | wdt->rate = clk_get_rate(wdt->clk); |
162 | /* Prevent divide-by-zero exception */ | |
163 | if (!wdt->rate) | |
164 | wdt->rate = WDT_DEFAULT_RATE; | |
165 | } else { | |
166 | wdt->rate = WDT_DEFAULT_RATE; | |
167 | wdt->clk = NULL; | |
168 | } | |
169 | ||
170 | wdt->wdd.info = &bcm7038_wdt_info; | |
171 | wdt->wdd.ops = &bcm7038_wdt_ops; | |
172 | wdt->wdd.min_timeout = WDT_MIN_TIMEOUT; | |
173 | wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT; | |
174 | wdt->wdd.max_timeout = 0xffffffff / wdt->rate; | |
175 | wdt->wdd.parent = dev; | |
176 | watchdog_set_drvdata(&wdt->wdd, wdt); | |
177 | ||
69656dcd GR |
178 | watchdog_stop_on_reboot(&wdt->wdd); |
179 | watchdog_stop_on_unregister(&wdt->wdd); | |
180 | err = devm_watchdog_register_device(dev, &wdt->wdd); | |
f5429895 | 181 | if (err) |
7a3629fe | 182 | return err; |
7a3629fe JC |
183 | |
184 | dev_info(dev, "Registered BCM7038 Watchdog\n"); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
7a3629fe JC |
189 | #ifdef CONFIG_PM_SLEEP |
190 | static int bcm7038_wdt_suspend(struct device *dev) | |
191 | { | |
192 | struct bcm7038_watchdog *wdt = dev_get_drvdata(dev); | |
193 | ||
194 | if (watchdog_active(&wdt->wdd)) | |
195 | return bcm7038_wdt_stop(&wdt->wdd); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static int bcm7038_wdt_resume(struct device *dev) | |
201 | { | |
202 | struct bcm7038_watchdog *wdt = dev_get_drvdata(dev); | |
203 | ||
204 | if (watchdog_active(&wdt->wdd)) | |
205 | return bcm7038_wdt_start(&wdt->wdd); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | #endif | |
210 | ||
211 | static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_ops, bcm7038_wdt_suspend, | |
212 | bcm7038_wdt_resume); | |
213 | ||
7a3629fe JC |
214 | static const struct of_device_id bcm7038_wdt_match[] = { |
215 | { .compatible = "brcm,bcm7038-wdt" }, | |
216 | {}, | |
217 | }; | |
57d77c62 | 218 | MODULE_DEVICE_TABLE(of, bcm7038_wdt_match); |
7a3629fe JC |
219 | |
220 | static struct platform_driver bcm7038_wdt_driver = { | |
221 | .probe = bcm7038_wdt_probe, | |
7a3629fe JC |
222 | .driver = { |
223 | .name = "bcm7038-wdt", | |
224 | .of_match_table = bcm7038_wdt_match, | |
225 | .pm = &bcm7038_wdt_pm_ops, | |
226 | } | |
227 | }; | |
228 | module_platform_driver(bcm7038_wdt_driver); | |
229 | ||
230 | module_param(nowayout, bool, 0); | |
231 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
232 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
2e62c498 | 233 | MODULE_LICENSE("GPL"); |
7a3629fe JC |
234 | MODULE_DESCRIPTION("Driver for Broadcom 7038 SoCs Watchdog"); |
235 | MODULE_AUTHOR("Justin Chen"); |