[mirror_ubuntu-jammy-kernel.git] / drivers / watchdog / cpu5wdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * sma cpu5 watchdog driver
 *
 * Copyright (C) 2003 Heiko Ronsdorf <hero@ihg.uni-duisburg.de>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/miscdevice.h>
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/timer.h>
#include <linux/completion.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/watchdog.h>

/* adjustable parameters */

static int verbose;
static int port = 0x91;
static int ticks = 10000;
static DEFINE_SPINLOCK(cpu5wdt_lock);

#define PFX			"cpu5wdt: "

#define CPU5WDT_EXTENT          0x0A

#define CPU5WDT_STATUS_REG      0x00
#define CPU5WDT_TIME_A_REG      0x02
#define CPU5WDT_TIME_B_REG      0x03
#define CPU5WDT_MODE_REG        0x04
#define CPU5WDT_TRIGGER_REG     0x07
#define CPU5WDT_ENABLE_REG      0x08
#define CPU5WDT_RESET_REG       0x09

#define CPU5WDT_INTERVAL	(HZ/10+1)

/* some device data */

static struct {
	struct completion stop;
	int running;
	struct timer_list timer;
	int queue;
	int default_ticks;
	unsigned long inuse;
} cpu5wdt_device;

/* generic helper functions */

static void cpu5wdt_trigger(struct timer_list *unused)
{
	if (verbose > 2)
		pr_debug("trigger at %i ticks\n", ticks);

	if (cpu5wdt_device.running)
		ticks--;

	spin_lock(&cpu5wdt_lock);
	/* keep watchdog alive */
	outb(1, port + CPU5WDT_TRIGGER_REG);

	/* requeue?? */
	if (cpu5wdt_device.queue && ticks)
		mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
	else {
		/* ticks doesn't matter anyway */
		complete(&cpu5wdt_device.stop);
	}
	spin_unlock(&cpu5wdt_lock);

}

static void cpu5wdt_reset(void)
{
	ticks = cpu5wdt_device.default_ticks;

	if (verbose)
		pr_debug("reset (%i ticks)\n", (int) ticks);

}

static void cpu5wdt_start(void)
{
	unsigned long flags;

	spin_lock_irqsave(&cpu5wdt_lock, flags);
	if (!cpu5wdt_device.queue) {
		cpu5wdt_device.queue = 1;
		outb(0, port + CPU5WDT_TIME_A_REG);
		outb(0, port + CPU5WDT_TIME_B_REG);
		outb(1, port + CPU5WDT_MODE_REG);
		outb(0, port + CPU5WDT_RESET_REG);
		outb(0, port + CPU5WDT_ENABLE_REG);
		mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
	}
	/* if process dies, counter is not decremented */
	cpu5wdt_device.running++;
	spin_unlock_irqrestore(&cpu5wdt_lock, flags);
}

static int cpu5wdt_stop(void)
{
	unsigned long flags;

	spin_lock_irqsave(&cpu5wdt_lock, flags);
	if (cpu5wdt_device.running)
		cpu5wdt_device.running = 0;
	ticks = cpu5wdt_device.default_ticks;
	spin_unlock_irqrestore(&cpu5wdt_lock, flags);
	if (verbose)
		pr_crit("stop not possible\n");
	return -EIO;
}

/* filesystem operations */

static int cpu5wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(0, &cpu5wdt_device.inuse))
		return -EBUSY;
	return stream_open(inode, file);
}

static int cpu5wdt_release(struct inode *inode, struct file *file)
{
	clear_bit(0, &cpu5wdt_device.inuse);
	return 0;
}

static long cpu5wdt_ioctl(struct file *file, unsigned int cmd,
						unsigned long arg)
{
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	unsigned int value;
	static const struct watchdog_info ident = {
		.options = WDIOF_CARDRESET,
		.identity = "CPU5 WDT",
	};

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		if (copy_to_user(argp, &ident, sizeof(ident)))
			return -EFAULT;
		break;
	case WDIOC_GETSTATUS:
		value = inb(port + CPU5WDT_STATUS_REG);
		value = (value >> 2) & 1;
		return put_user(value, p);
	case WDIOC_GETBOOTSTATUS:
		return put_user(0, p);
	case WDIOC_SETOPTIONS:
		if (get_user(value, p))
			return -EFAULT;
		if (value & WDIOS_ENABLECARD)
			cpu5wdt_start();
		if (value & WDIOS_DISABLECARD)
			cpu5wdt_stop();
		break;
	case WDIOC_KEEPALIVE:
		cpu5wdt_reset();
		break;
	default:
		return -ENOTTY;
	}
	return 0;
}

static ssize_t cpu5wdt_write(struct file *file, const char __user *buf,
						size_t count, loff_t *ppos)
{
	if (!count)
		return -EIO;
	cpu5wdt_reset();
	return count;
}

static const struct file_operations cpu5wdt_fops = {
	.owner		= THIS_MODULE,
	.llseek		= no_llseek,
	.unlocked_ioctl	= cpu5wdt_ioctl,
	.compat_ioctl	= compat_ptr_ioctl,
	.open		= cpu5wdt_open,
	.write		= cpu5wdt_write,
	.release	= cpu5wdt_release,
};

static struct miscdevice cpu5wdt_misc = {
	.minor	= WATCHDOG_MINOR,
	.name	= "watchdog",
	.fops	= &cpu5wdt_fops,
};

/* init/exit function */

static int cpu5wdt_init(void)
{
	unsigned int val;
	int err;

	if (verbose)
		pr_debug("port=0x%x, verbose=%i\n", port, verbose);

	init_completion(&cpu5wdt_device.stop);
	cpu5wdt_device.queue = 0;
	timer_setup(&cpu5wdt_device.timer, cpu5wdt_trigger, 0);
	cpu5wdt_device.default_ticks = ticks;

	if (!request_region(port, CPU5WDT_EXTENT, PFX)) {
		pr_err("request_region failed\n");
		err = -EBUSY;
		goto no_port;
	}

	/* watchdog reboot? */
	val = inb(port + CPU5WDT_STATUS_REG);
	val = (val >> 2) & 1;
	if (!val)
		pr_info("sorry, was my fault\n");

	err = misc_register(&cpu5wdt_misc);
	if (err < 0) {
		pr_err("misc_register failed\n");
		goto no_misc;
	}


	pr_info("init success\n");
	return 0;

no_misc:
	release_region(port, CPU5WDT_EXTENT);
no_port:
	return err;
}

static int cpu5wdt_init_module(void)
{
	return cpu5wdt_init();
}

static void cpu5wdt_exit(void)
{
	if (cpu5wdt_device.queue) {
		cpu5wdt_device.queue = 0;
		wait_for_completion(&cpu5wdt_device.stop);
		del_timer(&cpu5wdt_device.timer);
	}

	misc_deregister(&cpu5wdt_misc);

	release_region(port, CPU5WDT_EXTENT);

}

static void cpu5wdt_exit_module(void)
{
	cpu5wdt_exit();
}

/* module entry points */

module_init(cpu5wdt_init_module);
module_exit(cpu5wdt_exit_module);

MODULE_AUTHOR("Heiko Ronsdorf <hero@ihg.uni-duisburg.de>");
MODULE_DESCRIPTION("sma cpu5 watchdog driver");
MODULE_LICENSE("GPL");

module_param_hw(port, int, ioport, 0);
MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");

module_param(verbose, int, 0);
MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");

module_param(ticks, int, 0);
MODULE_PARM_DESC(ticks, "count down ticks, default is 10000");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* sma cpu5 watchdog driver
	4	*
	5	* Copyright (C) 2003 Heiko Ronsdorf <hero@ihg.uni-duisburg.de>
1da177e4 LT	6	*/
1da177e4 LT	7
27c766aa JP	8	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/moduleparam.h>
	12	#include <linux/types.h>
	13	#include <linux/errno.h>
	14	#include <linux/miscdevice.h>
	15	#include <linux/fs.h>
1da177e4 LT	16	#include <linux/ioport.h>
1da177e4 LT	17	#include <linux/timer.h>
3fe0c277	18	#include <linux/completion.h>
4e57b681	19	#include <linux/jiffies.h>
6f932f18 AC	20	#include <linux/io.h>
6f932f18 AC	21	#include <linux/uaccess.h>
1da177e4 LT	22	#include <linux/watchdog.h>
	23
	24	/* adjustable parameters */
	25
6f932f18	26	static int verbose;
1da177e4 LT	27	static int port = 0x91;
1da177e4 LT	28	static int ticks = 10000;
1334f329	29	static DEFINE_SPINLOCK(cpu5wdt_lock);
1da177e4 LT	30
	31	#define PFX "cpu5wdt: "
	32
	33	#define CPU5WDT_EXTENT 0x0A
	34
	35	#define CPU5WDT_STATUS_REG 0x00
	36	#define CPU5WDT_TIME_A_REG 0x02
	37	#define CPU5WDT_TIME_B_REG 0x03
	38	#define CPU5WDT_MODE_REG 0x04
	39	#define CPU5WDT_TRIGGER_REG 0x07
	40	#define CPU5WDT_ENABLE_REG 0x08
	41	#define CPU5WDT_RESET_REG 0x09
	42
	43	#define CPU5WDT_INTERVAL (HZ/10+1)
	44
	45	/* some device data */
	46
	47	static struct {
3fe0c277	48	struct completion stop;
996d62d4	49	int running;
1da177e4	50	struct timer_list timer;
996d62d4	51	int queue;
1da177e4 LT	52	int default_ticks;
	53	unsigned long inuse;
	54	} cpu5wdt_device;
	55
	56	/* generic helper functions */
	57
e99e88a9	58	static void cpu5wdt_trigger(struct timer_list *unused)
1da177e4	59	{
6f932f18	60	if (verbose > 2)
27c766aa	61	pr_debug("trigger at %i ticks\n", ticks);
1da177e4	62
6f932f18	63	if (cpu5wdt_device.running)
1da177e4 LT	64	ticks--;
1da177e4 LT	65
6f932f18	66	spin_lock(&cpu5wdt_lock);
1da177e4 LT	67	/* keep watchdog alive */
	68	outb(1, port + CPU5WDT_TRIGGER_REG);
	69
	70	/* requeue?? */
82eb7c50 JS	71	if (cpu5wdt_device.queue && ticks)
82eb7c50 JS	72	mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
1da177e4 LT	73	else {
1da177e4 LT	74	/* ticks doesn't matter anyway */
3fe0c277	75	complete(&cpu5wdt_device.stop);
1da177e4	76	}
6f932f18	77	spin_unlock(&cpu5wdt_lock);
1da177e4 LT	78
	79	}
	80
	81	static void cpu5wdt_reset(void)
	82	{
	83	ticks = cpu5wdt_device.default_ticks;
	84
6f932f18	85	if (verbose)
27c766aa	86	pr_debug("reset (%i ticks)\n", (int) ticks);
1da177e4 LT	87
	88	}
	89
	90	static void cpu5wdt_start(void)
	91	{
6f932f18 AC	92	unsigned long flags;
	93
	94	spin_lock_irqsave(&cpu5wdt_lock, flags);
	95	if (!cpu5wdt_device.queue) {
1da177e4 LT	96	cpu5wdt_device.queue = 1;
	97	outb(0, port + CPU5WDT_TIME_A_REG);
	98	outb(0, port + CPU5WDT_TIME_B_REG);
	99	outb(1, port + CPU5WDT_MODE_REG);
	100	outb(0, port + CPU5WDT_RESET_REG);
	101	outb(0, port + CPU5WDT_ENABLE_REG);
82eb7c50	102	mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
1da177e4 LT	103	}
	104	/* if process dies, counter is not decremented */
	105	cpu5wdt_device.running++;
6f932f18	106	spin_unlock_irqrestore(&cpu5wdt_lock, flags);
1da177e4 LT	107	}
	108
	109	static int cpu5wdt_stop(void)
	110	{
6f932f18	111	unsigned long flags;
1da177e4	112
6f932f18 AC	113	spin_lock_irqsave(&cpu5wdt_lock, flags);
	114	if (cpu5wdt_device.running)
	115	cpu5wdt_device.running = 0;
1da177e4	116	ticks = cpu5wdt_device.default_ticks;
6f932f18 AC	117	spin_unlock_irqrestore(&cpu5wdt_lock, flags);
6f932f18 AC	118	if (verbose)
27c766aa	119	pr_crit("stop not possible\n");
1da177e4 LT	120	return -EIO;
	121	}
	122
	123	/* filesystem operations */
	124
	125	static int cpu5wdt_open(struct inode inode, struct file file)
	126	{
6f932f18	127	if (test_and_set_bit(0, &cpu5wdt_device.inuse))
1da177e4	128	return -EBUSY;
c5bf68fe	129	return stream_open(inode, file);
1da177e4 LT	130	}
	131
	132	static int cpu5wdt_release(struct inode inode, struct file file)
	133	{
	134	clear_bit(0, &cpu5wdt_device.inuse);
	135	return 0;
	136	}
	137
6f932f18 AC	138	static long cpu5wdt_ioctl(struct file *file, unsigned int cmd,
6f932f18 AC	139	unsigned long arg)
1da177e4 LT	140	{
1da177e4 LT	141	void __user argp = (void __user )arg;
6f932f18	142	int __user *p = argp;
1da177e4	143	unsigned int value;
42747d71	144	static const struct watchdog_info ident = {
1da177e4 LT	145	.options = WDIOF_CARDRESET,
	146	.identity = "CPU5 WDT",
	147	};
	148
6f932f18	149	switch (cmd) {
0c06090c WVS	150	case WDIOC_GETSUPPORT:
	151	if (copy_to_user(argp, &ident, sizeof(ident)))
	152	return -EFAULT;
6f932f18 AC	153	break;
	154	case WDIOC_GETSTATUS:
	155	value = inb(port + CPU5WDT_STATUS_REG);
	156	value = (value >> 2) & 1;
	157	return put_user(value, p);
	158	case WDIOC_GETBOOTSTATUS:
	159	return put_user(0, p);
6f932f18 AC	160	case WDIOC_SETOPTIONS:
	161	if (get_user(value, p))
	162	return -EFAULT;
	163	if (value & WDIOS_ENABLECARD)
	164	cpu5wdt_start();
	165	if (value & WDIOS_DISABLECARD)
	166	cpu5wdt_stop();
	167	break;
0c06090c WVS	168	case WDIOC_KEEPALIVE:
	169	cpu5wdt_reset();
	170	break;
6f932f18 AC	171	default:
6f932f18 AC	172	return -ENOTTY;
1da177e4 LT	173	}
	174	return 0;
	175	}
	176
6f932f18 AC	177	static ssize_t cpu5wdt_write(struct file file, const char __user buf,
6f932f18 AC	178	size_t count, loff_t *ppos)
1da177e4	179	{
6f932f18	180	if (!count)
1da177e4	181	return -EIO;
1da177e4	182	cpu5wdt_reset();
1da177e4 LT	183	return count;
	184	}
	185
62322d25	186	static const struct file_operations cpu5wdt_fops = {
1da177e4 LT	187	.owner = THIS_MODULE,
1da177e4 LT	188	.llseek = no_llseek,
6f932f18	189	.unlocked_ioctl = cpu5wdt_ioctl,
b6dfb247	190	.compat_ioctl = compat_ptr_ioctl,
1da177e4 LT	191	.open = cpu5wdt_open,
	192	.write = cpu5wdt_write,
	193	.release = cpu5wdt_release,
	194	};
	195
	196	static struct miscdevice cpu5wdt_misc = {
	197	.minor = WATCHDOG_MINOR,
	198	.name = "watchdog",
	199	.fops = &cpu5wdt_fops,
	200	};
	201
	202	/* init/exit function */
	203
2d991a16	204	static int cpu5wdt_init(void)
1da177e4 LT	205	{
	206	unsigned int val;
	207	int err;
	208
6f932f18	209	if (verbose)
27c766aa	210	pr_debug("port=0x%x, verbose=%i\n", port, verbose);
1da177e4	211
6f932f18	212	init_completion(&cpu5wdt_device.stop);
6f932f18	213	cpu5wdt_device.queue = 0;
e99e88a9	214	timer_setup(&cpu5wdt_device.timer, cpu5wdt_trigger, 0);
6f932f18 AC	215	cpu5wdt_device.default_ticks = ticks;
	216
	217	if (!request_region(port, CPU5WDT_EXTENT, PFX)) {
27c766aa	218	pr_err("request_region failed\n");
1da177e4 LT	219	err = -EBUSY;
	220	goto no_port;
	221	}
	222
	223	/* watchdog reboot? */
	224	val = inb(port + CPU5WDT_STATUS_REG);
	225	val = (val >> 2) & 1;
6f932f18	226	if (!val)
27c766aa	227	pr_info("sorry, was my fault\n");
1da177e4	228
6f932f18 AC	229	err = misc_register(&cpu5wdt_misc);
6f932f18 AC	230	if (err < 0) {
27c766aa	231	pr_err("misc_register failed\n");
6f932f18 AC	232	goto no_misc;
6f932f18 AC	233	}
1da177e4	234
1da177e4	235
27c766aa	236	pr_info("init success\n");
1da177e4 LT	237	return 0;
1da177e4 LT	238
1da177e4	239	no_misc:
fb8f7ba0 AD	240	release_region(port, CPU5WDT_EXTENT);
fb8f7ba0 AD	241	no_port:
1da177e4 LT	242	return err;
	243	}
	244
2d991a16	245	static int cpu5wdt_init_module(void)
1da177e4 LT	246	{
	247	return cpu5wdt_init();
	248	}
	249
4b12b896	250	static void cpu5wdt_exit(void)
1da177e4	251	{
6f932f18	252	if (cpu5wdt_device.queue) {
1da177e4	253	cpu5wdt_device.queue = 0;
3fe0c277	254	wait_for_completion(&cpu5wdt_device.stop);
e09d9c3e	255	del_timer(&cpu5wdt_device.timer);
1da177e4 LT	256	}
	257
	258	misc_deregister(&cpu5wdt_misc);
	259
	260	release_region(port, CPU5WDT_EXTENT);
	261
	262	}
	263
4b12b896	264	static void cpu5wdt_exit_module(void)
1da177e4 LT	265	{
	266	cpu5wdt_exit();
	267	}
	268
	269	/* module entry points */
	270
	271	module_init(cpu5wdt_init_module);
	272	module_exit(cpu5wdt_exit_module);
	273
	274	MODULE_AUTHOR("Heiko Ronsdorf <hero@ihg.uni-duisburg.de>");
	275	MODULE_DESCRIPTION("sma cpu5 watchdog driver");
1da177e4	276	MODULE_LICENSE("GPL");
1da177e4	277
5d1c93ce	278	module_param_hw(port, int, ioport, 0);
1da177e4 LT	279	MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");
	280
	281	module_param(verbose, int, 0);
	282	MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");
	283
	284	module_param(ticks, int, 0);
	285	MODULE_PARM_DESC(ticks, "count down ticks, default is 10000");