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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8ab0dc33 | 2 | /* cpwd.c - driver implementation for hardware watchdog |
1da177e4 LT |
3 | * timers found on Sun Microsystems CP1400 and CP1500 boards. |
4 | * | |
927d6961 | 5 | * This device supports both the generic Linux watchdog |
1da177e4 LT |
6 | * interface and Solaris-compatible ioctls as best it is |
7 | * able. | |
8 | * | |
5f3b2756 WVS |
9 | * NOTE: CP1400 systems appear to have a defective intr_mask |
10 | * register on the PLD, preventing the disabling of | |
11 | * timer interrupts. We use a timer to periodically | |
12 | * reset 'stopped' watchdogs on affected platforms. | |
1da177e4 | 13 | * |
1da177e4 | 14 | * Copyright (c) 2000 Eric Brower (ebrower@usa.net) |
c5f8556c | 15 | * Copyright (C) 2008 David S. Miller <davem@davemloft.net> |
1da177e4 LT |
16 | */ |
17 | ||
27c766aa JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/fs.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/major.h> | |
1da177e4 | 25 | #include <linux/miscdevice.h> |
1da177e4 LT |
26 | #include <linux/interrupt.h> |
27 | #include <linux/ioport.h> | |
28 | #include <linux/timer.h> | |
c58e8134 | 29 | #include <linux/compat.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
613655fa | 31 | #include <linux/mutex.h> |
347e03df | 32 | #include <linux/io.h> |
c5f8556c DM |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
278aefc5 | 35 | #include <linux/uaccess.h> |
c5f8556c | 36 | |
1da177e4 | 37 | #include <asm/irq.h> |
1da177e4 LT |
38 | #include <asm/watchdog.h> |
39 | ||
c5f8556c | 40 | #define DRIVER_NAME "cpwd" |
c5f8556c | 41 | |
1da177e4 | 42 | #define WD_OBPNAME "watchdog" |
c5f8556c | 43 | #define WD_BADMODEL "SUNW,501-5336" |
1da177e4 LT |
44 | #define WD_BTIMEOUT (jiffies + (HZ * 1000)) |
45 | #define WD_BLIMIT 0xFFFF | |
46 | ||
1da177e4 | 47 | #define WD0_MINOR 212 |
927d6961 WVS |
48 | #define WD1_MINOR 213 |
49 | #define WD2_MINOR 214 | |
1da177e4 | 50 | |
c5f8556c DM |
51 | /* Internal driver definitions. */ |
52 | #define WD0_ID 0 | |
53 | #define WD1_ID 1 | |
54 | #define WD2_ID 2 | |
55 | #define WD_NUMDEVS 3 | |
1da177e4 | 56 | |
c5f8556c DM |
57 | #define WD_INTR_OFF 0 |
58 | #define WD_INTR_ON 1 | |
1da177e4 LT |
59 | |
60 | #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */ | |
61 | #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */ | |
62 | #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */ | |
63 | ||
64 | /* Register value definitions | |
65 | */ | |
66 | #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */ | |
67 | #define WD1_INTR_MASK 0x02 | |
68 | #define WD2_INTR_MASK 0x04 | |
69 | ||
70 | #define WD_S_RUNNING 0x01 /* Watchdog device status running */ | |
71 | #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */ | |
72 | ||
c5f8556c DM |
73 | struct cpwd { |
74 | void __iomem *regs; | |
75 | spinlock_t lock; | |
76 | ||
77 | unsigned int irq; | |
78 | ||
79 | unsigned long timeout; | |
80 | bool enabled; | |
81 | bool reboot; | |
82 | bool broken; | |
83 | bool initialized; | |
84 | ||
85 | struct { | |
86 | struct miscdevice misc; | |
87 | void __iomem *regs; | |
88 | u8 intr_mask; | |
89 | u8 runstatus; | |
90 | u16 timeout; | |
91 | } devs[WD_NUMDEVS]; | |
92 | }; | |
93 | ||
613655fa | 94 | static DEFINE_MUTEX(cpwd_mutex); |
c5f8556c DM |
95 | static struct cpwd *cpwd_device; |
96 | ||
927d6961 | 97 | /* Sun uses Altera PLD EPF8820ATC144-4 |
1da177e4 LT |
98 | * providing three hardware watchdogs: |
99 | * | |
927d6961 WVS |
100 | * 1) RIC - sends an interrupt when triggered |
101 | * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU | |
102 | * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board | |
1da177e4 LT |
103 | * |
104 | *** Timer register block definition (struct wd_timer_regblk) | |
105 | * | |
927d6961 | 106 | * dcntr and limit registers (halfword access): |
1da177e4 LT |
107 | * ------------------- |
108 | * | 15 | ...| 1 | 0 | | |
109 | * ------------------- | |
110 | * |- counter val -| | |
111 | * ------------------- | |
5f3b2756 WVS |
112 | * dcntr - Current 16-bit downcounter value. |
113 | * When downcounter reaches '0' watchdog expires. | |
114 | * Reading this register resets downcounter with | |
115 | * 'limit' value. | |
116 | * limit - 16-bit countdown value in 1/10th second increments. | |
117 | * Writing this register begins countdown with input value. | |
118 | * Reading from this register does not affect counter. | |
1da177e4 LT |
119 | * NOTES: After watchdog reset, dcntr and limit contain '1' |
120 | * | |
121 | * status register (byte access): | |
122 | * --------------------------- | |
123 | * | 7 | ... | 2 | 1 | 0 | | |
124 | * --------------+------------ | |
125 | * |- UNUSED -| EXP | RUN | | |
126 | * --------------------------- | |
127 | * status- Bit 0 - Watchdog is running | |
5f3b2756 | 128 | * Bit 1 - Watchdog has expired |
1da177e4 LT |
129 | * |
130 | *** PLD register block definition (struct wd_pld_regblk) | |
131 | * | |
132 | * intr_mask register (byte access): | |
133 | * --------------------------------- | |
134 | * | 7 | ... | 3 | 2 | 1 | 0 | | |
135 | * +-------------+------------------ | |
136 | * |- UNUSED -| WD3 | WD2 | WD1 | | |
137 | * --------------------------------- | |
138 | * WD3 - 1 == Interrupt disabled for watchdog 3 | |
139 | * WD2 - 1 == Interrupt disabled for watchdog 2 | |
140 | * WD1 - 1 == Interrupt disabled for watchdog 1 | |
141 | * | |
142 | * pld_status register (byte access): | |
143 | * UNKNOWN, MAGICAL MYSTERY REGISTER | |
144 | * | |
145 | */ | |
146 | #define WD_TIMER_REGSZ 16 | |
147 | #define WD0_OFF 0 | |
148 | #define WD1_OFF (WD_TIMER_REGSZ * 1) | |
149 | #define WD2_OFF (WD_TIMER_REGSZ * 2) | |
150 | #define PLD_OFF (WD_TIMER_REGSZ * 3) | |
151 | ||
152 | #define WD_DCNTR 0x00 | |
153 | #define WD_LIMIT 0x04 | |
154 | #define WD_STATUS 0x08 | |
155 | ||
156 | #define PLD_IMASK (PLD_OFF + 0x00) | |
157 | #define PLD_STATUS (PLD_OFF + 0x04) | |
158 | ||
c5f8556c | 159 | static struct timer_list cpwd_timer; |
1da177e4 | 160 | |
a77dba7e WVS |
161 | static int wd0_timeout; |
162 | static int wd1_timeout; | |
163 | static int wd2_timeout; | |
1da177e4 | 164 | |
927d6961 | 165 | module_param(wd0_timeout, int, 0); |
1da177e4 | 166 | MODULE_PARM_DESC(wd0_timeout, "Default watchdog0 timeout in 1/10secs"); |
927d6961 | 167 | module_param(wd1_timeout, int, 0); |
1da177e4 | 168 | MODULE_PARM_DESC(wd1_timeout, "Default watchdog1 timeout in 1/10secs"); |
927d6961 | 169 | module_param(wd2_timeout, int, 0); |
1da177e4 LT |
170 | MODULE_PARM_DESC(wd2_timeout, "Default watchdog2 timeout in 1/10secs"); |
171 | ||
c5f8556c DM |
172 | MODULE_AUTHOR("Eric Brower <ebrower@usa.net>"); |
173 | MODULE_DESCRIPTION("Hardware watchdog driver for Sun Microsystems CP1400/1500"); | |
1da177e4 | 174 | MODULE_LICENSE("GPL"); |
c5f8556c DM |
175 | MODULE_SUPPORTED_DEVICE("watchdog"); |
176 | ||
177 | static void cpwd_writew(u16 val, void __iomem *addr) | |
178 | { | |
179 | writew(cpu_to_le16(val), addr); | |
180 | } | |
181 | static u16 cpwd_readw(void __iomem *addr) | |
182 | { | |
183 | u16 val = readw(addr); | |
184 | ||
185 | return le16_to_cpu(val); | |
186 | } | |
187 | ||
188 | static void cpwd_writeb(u8 val, void __iomem *addr) | |
189 | { | |
190 | writeb(val, addr); | |
191 | } | |
192 | ||
193 | static u8 cpwd_readb(void __iomem *addr) | |
194 | { | |
195 | return readb(addr); | |
196 | } | |
1da177e4 | 197 | |
c5f8556c DM |
198 | /* Enable or disable watchdog interrupts |
199 | * Because of the CP1400 defect this should only be | |
200 | * called during initialzation or by wd_[start|stop]timer() | |
201 | * | |
5f3b2756 | 202 | * index - sub-device index, or -1 for 'all' |
c5f8556c | 203 | * enable - non-zero to enable interrupts, zero to disable |
1da177e4 | 204 | */ |
c5f8556c DM |
205 | static void cpwd_toggleintr(struct cpwd *p, int index, int enable) |
206 | { | |
207 | unsigned char curregs = cpwd_readb(p->regs + PLD_IMASK); | |
927d6961 WVS |
208 | unsigned char setregs = |
209 | (index == -1) ? | |
210 | (WD0_INTR_MASK | WD1_INTR_MASK | WD2_INTR_MASK) : | |
c5f8556c DM |
211 | (p->devs[index].intr_mask); |
212 | ||
213 | if (enable == WD_INTR_ON) | |
214 | curregs &= ~setregs; | |
215 | else | |
216 | curregs |= setregs; | |
217 | ||
218 | cpwd_writeb(curregs, p->regs + PLD_IMASK); | |
219 | } | |
220 | ||
221 | /* Restarts timer with maximum limit value and | |
222 | * does not unset 'brokenstop' value. | |
1da177e4 | 223 | */ |
c5f8556c | 224 | static void cpwd_resetbrokentimer(struct cpwd *p, int index) |
1da177e4 | 225 | { |
c5f8556c DM |
226 | cpwd_toggleintr(p, index, WD_INTR_ON); |
227 | cpwd_writew(WD_BLIMIT, p->devs[index].regs + WD_LIMIT); | |
1da177e4 LT |
228 | } |
229 | ||
c5f8556c DM |
230 | /* Timer method called to reset stopped watchdogs-- |
231 | * because of the PLD bug on CP1400, we cannot mask | |
232 | * interrupts within the PLD so me must continually | |
233 | * reset the timers ad infinitum. | |
234 | */ | |
4fa42b4e | 235 | static void cpwd_brokentimer(struct timer_list *unused) |
c5f8556c | 236 | { |
4fa42b4e | 237 | struct cpwd *p = cpwd_device; |
c5f8556c DM |
238 | int id, tripped = 0; |
239 | ||
240 | /* kill a running timer instance, in case we | |
241 | * were called directly instead of by kernel timer | |
242 | */ | |
243 | if (timer_pending(&cpwd_timer)) | |
244 | del_timer(&cpwd_timer); | |
1da177e4 | 245 | |
c5f8556c DM |
246 | for (id = 0; id < WD_NUMDEVS; id++) { |
247 | if (p->devs[id].runstatus & WD_STAT_BSTOP) { | |
248 | ++tripped; | |
249 | cpwd_resetbrokentimer(p, id); | |
250 | } | |
251 | } | |
1da177e4 | 252 | |
c5f8556c DM |
253 | if (tripped) { |
254 | /* there is at least one timer brokenstopped-- reschedule */ | |
255 | cpwd_timer.expires = WD_BTIMEOUT; | |
256 | add_timer(&cpwd_timer); | |
257 | } | |
258 | } | |
259 | ||
260 | /* Reset countdown timer with 'limit' value and continue countdown. | |
261 | * This will not start a stopped timer. | |
1da177e4 | 262 | */ |
c5f8556c | 263 | static void cpwd_pingtimer(struct cpwd *p, int index) |
1da177e4 | 264 | { |
c5f8556c DM |
265 | if (cpwd_readb(p->devs[index].regs + WD_STATUS) & WD_S_RUNNING) |
266 | cpwd_readw(p->devs[index].regs + WD_DCNTR); | |
1da177e4 | 267 | } |
c5f8556c DM |
268 | |
269 | /* Stop a running watchdog timer-- the timer actually keeps | |
270 | * running, but the interrupt is masked so that no action is | |
271 | * taken upon expiration. | |
1da177e4 | 272 | */ |
c5f8556c | 273 | static void cpwd_stoptimer(struct cpwd *p, int index) |
1da177e4 | 274 | { |
c5f8556c DM |
275 | if (cpwd_readb(p->devs[index].regs + WD_STATUS) & WD_S_RUNNING) { |
276 | cpwd_toggleintr(p, index, WD_INTR_OFF); | |
1da177e4 | 277 | |
c5f8556c DM |
278 | if (p->broken) { |
279 | p->devs[index].runstatus |= WD_STAT_BSTOP; | |
4fa42b4e | 280 | cpwd_brokentimer(NULL); |
c5f8556c DM |
281 | } |
282 | } | |
1da177e4 LT |
283 | } |
284 | ||
c5f8556c DM |
285 | /* Start a watchdog timer with the specified limit value |
286 | * If the watchdog is running, it will be restarted with | |
287 | * the provided limit value. | |
288 | * | |
289 | * This function will enable interrupts on the specified | |
290 | * watchdog. | |
1da177e4 | 291 | */ |
c5f8556c | 292 | static void cpwd_starttimer(struct cpwd *p, int index) |
1da177e4 | 293 | { |
c5f8556c DM |
294 | if (p->broken) |
295 | p->devs[index].runstatus &= ~WD_STAT_BSTOP; | |
296 | ||
297 | p->devs[index].runstatus &= ~WD_STAT_SVCD; | |
1da177e4 | 298 | |
c5f8556c DM |
299 | cpwd_writew(p->devs[index].timeout, p->devs[index].regs + WD_LIMIT); |
300 | cpwd_toggleintr(p, index, WD_INTR_ON); | |
1da177e4 LT |
301 | } |
302 | ||
c5f8556c | 303 | static int cpwd_getstatus(struct cpwd *p, int index) |
1da177e4 | 304 | { |
c5f8556c DM |
305 | unsigned char stat = cpwd_readb(p->devs[index].regs + WD_STATUS); |
306 | unsigned char intr = cpwd_readb(p->devs[index].regs + PLD_IMASK); | |
307 | unsigned char ret = WD_STOPPED; | |
308 | ||
309 | /* determine STOPPED */ | |
927d6961 | 310 | if (!stat) |
c5f8556c DM |
311 | return ret; |
312 | ||
313 | /* determine EXPIRED vs FREERUN vs RUNNING */ | |
314 | else if (WD_S_EXPIRED & stat) { | |
315 | ret = WD_EXPIRED; | |
927d6961 | 316 | } else if (WD_S_RUNNING & stat) { |
c5f8556c DM |
317 | if (intr & p->devs[index].intr_mask) { |
318 | ret = WD_FREERUN; | |
319 | } else { | |
320 | /* Fudge WD_EXPIRED status for defective CP1400-- | |
927d6961 | 321 | * IF timer is running |
5f3b2756 WVS |
322 | * AND brokenstop is set |
323 | * AND an interrupt has been serviced | |
c5f8556c DM |
324 | * we are WD_EXPIRED. |
325 | * | |
927d6961 | 326 | * IF timer is running |
5f3b2756 WVS |
327 | * AND brokenstop is set |
328 | * AND no interrupt has been serviced | |
c5f8556c DM |
329 | * we are WD_FREERUN. |
330 | */ | |
331 | if (p->broken && | |
332 | (p->devs[index].runstatus & WD_STAT_BSTOP)) { | |
333 | if (p->devs[index].runstatus & WD_STAT_SVCD) { | |
334 | ret = WD_EXPIRED; | |
335 | } else { | |
927d6961 WVS |
336 | /* we could as well pretend |
337 | * we are expired */ | |
c5f8556c DM |
338 | ret = WD_FREERUN; |
339 | } | |
340 | } else { | |
341 | ret = WD_RUNNING; | |
1da177e4 LT |
342 | } |
343 | } | |
344 | } | |
c5f8556c DM |
345 | |
346 | /* determine SERVICED */ | |
347 | if (p->devs[index].runstatus & WD_STAT_SVCD) | |
348 | ret |= WD_SERVICED; | |
349 | ||
927d6961 | 350 | return ret; |
c5f8556c DM |
351 | } |
352 | ||
353 | static irqreturn_t cpwd_interrupt(int irq, void *dev_id) | |
354 | { | |
355 | struct cpwd *p = dev_id; | |
356 | ||
357 | /* Only WD0 will interrupt-- others are NMI and we won't | |
358 | * see them here.... | |
359 | */ | |
360 | spin_lock_irq(&p->lock); | |
361 | ||
362 | cpwd_stoptimer(p, WD0_ID); | |
363 | p->devs[WD0_ID].runstatus |= WD_STAT_SVCD; | |
364 | ||
365 | spin_unlock_irq(&p->lock); | |
366 | ||
367 | return IRQ_HANDLED; | |
1da177e4 LT |
368 | } |
369 | ||
c5f8556c | 370 | static int cpwd_open(struct inode *inode, struct file *f) |
1da177e4 | 371 | { |
c5f8556c DM |
372 | struct cpwd *p = cpwd_device; |
373 | ||
613655fa | 374 | mutex_lock(&cpwd_mutex); |
927d6961 WVS |
375 | switch (iminor(inode)) { |
376 | case WD0_MINOR: | |
377 | case WD1_MINOR: | |
378 | case WD2_MINOR: | |
379 | break; | |
c5f8556c | 380 | |
927d6961 | 381 | default: |
613655fa | 382 | mutex_unlock(&cpwd_mutex); |
927d6961 | 383 | return -ENODEV; |
1da177e4 LT |
384 | } |
385 | ||
386 | /* Register IRQ on first open of device */ | |
c5f8556c | 387 | if (!p->initialized) { |
927d6961 | 388 | if (request_irq(p->irq, &cpwd_interrupt, |
c5f8556c | 389 | IRQF_SHARED, DRIVER_NAME, p)) { |
27c766aa | 390 | pr_err("Cannot register IRQ %d\n", p->irq); |
613655fa | 391 | mutex_unlock(&cpwd_mutex); |
c5f8556c | 392 | return -EBUSY; |
1da177e4 | 393 | } |
c5f8556c | 394 | p->initialized = true; |
1da177e4 LT |
395 | } |
396 | ||
613655fa | 397 | mutex_unlock(&cpwd_mutex); |
c5f8556c | 398 | |
c5bf68fe | 399 | return stream_open(inode, f); |
1da177e4 LT |
400 | } |
401 | ||
c5f8556c | 402 | static int cpwd_release(struct inode *inode, struct file *file) |
1da177e4 LT |
403 | { |
404 | return 0; | |
405 | } | |
406 | ||
9626dd75 | 407 | static long cpwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
1da177e4 | 408 | { |
42747d71 | 409 | static const struct watchdog_info info = { |
c5f8556c DM |
410 | .options = WDIOF_SETTIMEOUT, |
411 | .firmware_version = 1, | |
412 | .identity = DRIVER_NAME, | |
1da177e4 | 413 | }; |
c5f8556c | 414 | void __user *argp = (void __user *)arg; |
496ad9aa | 415 | struct inode *inode = file_inode(file); |
c5f8556c DM |
416 | int index = iminor(inode) - WD0_MINOR; |
417 | struct cpwd *p = cpwd_device; | |
418 | int setopt = 0; | |
1da177e4 | 419 | |
c5f8556c DM |
420 | switch (cmd) { |
421 | /* Generic Linux IOCTLs */ | |
422 | case WDIOC_GETSUPPORT: | |
423 | if (copy_to_user(argp, &info, sizeof(struct watchdog_info))) | |
424 | return -EFAULT; | |
425 | break; | |
1da177e4 | 426 | |
c5f8556c DM |
427 | case WDIOC_GETSTATUS: |
428 | case WDIOC_GETBOOTSTATUS: | |
429 | if (put_user(0, (int __user *)argp)) | |
430 | return -EFAULT; | |
431 | break; | |
432 | ||
433 | case WDIOC_KEEPALIVE: | |
434 | cpwd_pingtimer(p, index); | |
435 | break; | |
436 | ||
437 | case WDIOC_SETOPTIONS: | |
438 | if (copy_from_user(&setopt, argp, sizeof(unsigned int))) | |
439 | return -EFAULT; | |
440 | ||
441 | if (setopt & WDIOS_DISABLECARD) { | |
442 | if (p->enabled) | |
443 | return -EINVAL; | |
444 | cpwd_stoptimer(p, index); | |
445 | } else if (setopt & WDIOS_ENABLECARD) { | |
446 | cpwd_starttimer(p, index); | |
447 | } else { | |
448 | return -EINVAL; | |
927d6961 | 449 | } |
c5f8556c DM |
450 | break; |
451 | ||
452 | /* Solaris-compatible IOCTLs */ | |
453 | case WIOCGSTAT: | |
454 | setopt = cpwd_getstatus(p, index); | |
455 | if (copy_to_user(argp, &setopt, sizeof(unsigned int))) | |
456 | return -EFAULT; | |
457 | break; | |
458 | ||
459 | case WIOCSTART: | |
460 | cpwd_starttimer(p, index); | |
461 | break; | |
462 | ||
463 | case WIOCSTOP: | |
464 | if (p->enabled) | |
927d6961 | 465 | return -EINVAL; |
c5f8556c DM |
466 | |
467 | cpwd_stoptimer(p, index); | |
468 | break; | |
469 | ||
470 | default: | |
471 | return -EINVAL; | |
1da177e4 | 472 | } |
c5f8556c DM |
473 | |
474 | return 0; | |
1da177e4 LT |
475 | } |
476 | ||
c58e8134 AB |
477 | static long cpwd_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
478 | { | |
479 | return cpwd_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); | |
480 | } | |
481 | ||
927d6961 | 482 | static ssize_t cpwd_write(struct file *file, const char __user *buf, |
c5f8556c | 483 | size_t count, loff_t *ppos) |
1da177e4 | 484 | { |
496ad9aa | 485 | struct inode *inode = file_inode(file); |
c5f8556c DM |
486 | struct cpwd *p = cpwd_device; |
487 | int index = iminor(inode); | |
1da177e4 LT |
488 | |
489 | if (count) { | |
c5f8556c | 490 | cpwd_pingtimer(p, index); |
1da177e4 LT |
491 | return 1; |
492 | } | |
1da177e4 | 493 | |
c5f8556c | 494 | return 0; |
1da177e4 LT |
495 | } |
496 | ||
927d6961 | 497 | static ssize_t cpwd_read(struct file *file, char __user *buffer, |
c5f8556c | 498 | size_t count, loff_t *ppos) |
1da177e4 | 499 | { |
c5f8556c | 500 | return -EINVAL; |
1da177e4 LT |
501 | } |
502 | ||
c5f8556c | 503 | static const struct file_operations cpwd_fops = { |
9626dd75 WVS |
504 | .owner = THIS_MODULE, |
505 | .unlocked_ioctl = cpwd_ioctl, | |
c58e8134 | 506 | .compat_ioctl = cpwd_compat_ioctl, |
9626dd75 WVS |
507 | .open = cpwd_open, |
508 | .write = cpwd_write, | |
509 | .read = cpwd_read, | |
510 | .release = cpwd_release, | |
6038f373 | 511 | .llseek = no_llseek, |
1da177e4 LT |
512 | }; |
513 | ||
2d991a16 | 514 | static int cpwd_probe(struct platform_device *op) |
1da177e4 | 515 | { |
c5f8556c DM |
516 | struct device_node *options; |
517 | const char *str_prop; | |
518 | const void *prop_val; | |
519 | int i, err = -EINVAL; | |
520 | struct cpwd *p; | |
1da177e4 | 521 | |
c5f8556c DM |
522 | if (cpwd_device) |
523 | return -EINVAL; | |
1da177e4 | 524 | |
b6621df5 AK |
525 | p = devm_kzalloc(&op->dev, sizeof(*p), GFP_KERNEL); |
526 | if (!p) | |
527 | return -ENOMEM; | |
1da177e4 | 528 | |
1636f8ac | 529 | p->irq = op->archdata.irqs[0]; |
1da177e4 | 530 | |
c5f8556c | 531 | spin_lock_init(&p->lock); |
1da177e4 | 532 | |
c5f8556c DM |
533 | p->regs = of_ioremap(&op->resource[0], 0, |
534 | 4 * WD_TIMER_REGSZ, DRIVER_NAME); | |
535 | if (!p->regs) { | |
27c766aa | 536 | pr_err("Unable to map registers\n"); |
b6621df5 | 537 | return -ENOMEM; |
1da177e4 | 538 | } |
1da177e4 | 539 | |
c5f8556c | 540 | options = of_find_node_by_path("/options"); |
c5f8556c | 541 | if (!options) { |
b6621df5 | 542 | err = -ENODEV; |
27c766aa | 543 | pr_err("Unable to find /options node\n"); |
c5f8556c DM |
544 | goto out_iounmap; |
545 | } | |
1da177e4 | 546 | |
c5f8556c DM |
547 | prop_val = of_get_property(options, "watchdog-enable?", NULL); |
548 | p->enabled = (prop_val ? true : false); | |
1da177e4 | 549 | |
c5f8556c DM |
550 | prop_val = of_get_property(options, "watchdog-reboot?", NULL); |
551 | p->reboot = (prop_val ? true : false); | |
1da177e4 | 552 | |
c5f8556c DM |
553 | str_prop = of_get_property(options, "watchdog-timeout", NULL); |
554 | if (str_prop) | |
555 | p->timeout = simple_strtoul(str_prop, NULL, 10); | |
1da177e4 | 556 | |
06f8f2ca YL |
557 | of_node_put(options); |
558 | ||
c5f8556c DM |
559 | /* CP1400s seem to have broken PLD implementations-- the |
560 | * interrupt_mask register cannot be written, so no timer | |
561 | * interrupts can be masked within the PLD. | |
1da177e4 | 562 | */ |
61c7a080 | 563 | str_prop = of_get_property(op->dev.of_node, "model", NULL); |
c5f8556c DM |
564 | p->broken = (str_prop && !strcmp(str_prop, WD_BADMODEL)); |
565 | ||
566 | if (!p->enabled) | |
567 | cpwd_toggleintr(p, -1, WD_INTR_OFF); | |
568 | ||
569 | for (i = 0; i < WD_NUMDEVS; i++) { | |
570 | static const char *cpwd_names[] = { "RIC", "XIR", "POR" }; | |
571 | static int *parms[] = { &wd0_timeout, | |
572 | &wd1_timeout, | |
573 | &wd2_timeout }; | |
574 | struct miscdevice *mp = &p->devs[i].misc; | |
575 | ||
576 | mp->minor = WD0_MINOR + i; | |
577 | mp->name = cpwd_names[i]; | |
578 | mp->fops = &cpwd_fops; | |
579 | ||
580 | p->devs[i].regs = p->regs + (i * WD_TIMER_REGSZ); | |
581 | p->devs[i].intr_mask = (WD0_INTR_MASK << i); | |
582 | p->devs[i].runstatus &= ~WD_STAT_BSTOP; | |
583 | p->devs[i].runstatus |= WD_STAT_INIT; | |
584 | p->devs[i].timeout = p->timeout; | |
585 | if (*parms[i]) | |
586 | p->devs[i].timeout = *parms[i]; | |
587 | ||
588 | err = misc_register(&p->devs[i].misc); | |
589 | if (err) { | |
27c766aa JP |
590 | pr_err("Could not register misc device for dev %d\n", |
591 | i); | |
c5f8556c | 592 | goto out_unregister; |
1da177e4 LT |
593 | } |
594 | } | |
595 | ||
c5f8556c | 596 | if (p->broken) { |
4fa42b4e | 597 | timer_setup(&cpwd_timer, cpwd_brokentimer, 0); |
c5f8556c DM |
598 | cpwd_timer.expires = WD_BTIMEOUT; |
599 | ||
27c766aa JP |
600 | pr_info("PLD defect workaround enabled for model %s\n", |
601 | WD_BADMODEL); | |
1da177e4 | 602 | } |
1da177e4 | 603 | |
26556b6e | 604 | platform_set_drvdata(op, p); |
c5f8556c | 605 | cpwd_device = p; |
b6621df5 | 606 | return 0; |
1da177e4 | 607 | |
c5f8556c DM |
608 | out_unregister: |
609 | for (i--; i >= 0; i--) | |
610 | misc_deregister(&p->devs[i].misc); | |
1da177e4 | 611 | |
c5f8556c DM |
612 | out_iounmap: |
613 | of_iounmap(&op->resource[0], p->regs, 4 * WD_TIMER_REGSZ); | |
614 | ||
b6621df5 | 615 | return err; |
1da177e4 LT |
616 | } |
617 | ||
4b12b896 | 618 | static int cpwd_remove(struct platform_device *op) |
1da177e4 | 619 | { |
26556b6e | 620 | struct cpwd *p = platform_get_drvdata(op); |
c5f8556c DM |
621 | int i; |
622 | ||
bbd562d7 | 623 | for (i = 0; i < WD_NUMDEVS; i++) { |
c5f8556c DM |
624 | misc_deregister(&p->devs[i].misc); |
625 | ||
626 | if (!p->enabled) { | |
627 | cpwd_stoptimer(p, i); | |
628 | if (p->devs[i].runstatus & WD_STAT_BSTOP) | |
629 | cpwd_resetbrokentimer(p, i); | |
1da177e4 LT |
630 | } |
631 | } | |
632 | ||
c5f8556c DM |
633 | if (p->broken) |
634 | del_timer_sync(&cpwd_timer); | |
1da177e4 | 635 | |
c5f8556c DM |
636 | if (p->initialized) |
637 | free_irq(p->irq, p); | |
1da177e4 | 638 | |
c5f8556c | 639 | of_iounmap(&op->resource[0], p->regs, 4 * WD_TIMER_REGSZ); |
1da177e4 | 640 | |
c5f8556c | 641 | cpwd_device = NULL; |
1da177e4 | 642 | |
c5f8556c DM |
643 | return 0; |
644 | } | |
1da177e4 | 645 | |
fd098316 | 646 | static const struct of_device_id cpwd_match[] = { |
c5f8556c DM |
647 | { |
648 | .name = "watchdog", | |
649 | }, | |
650 | {}, | |
651 | }; | |
652 | MODULE_DEVICE_TABLE(of, cpwd_match); | |
1da177e4 | 653 | |
1c48a5c9 | 654 | static struct platform_driver cpwd_driver = { |
4018294b GL |
655 | .driver = { |
656 | .name = DRIVER_NAME, | |
4018294b GL |
657 | .of_match_table = cpwd_match, |
658 | }, | |
c5f8556c | 659 | .probe = cpwd_probe, |
82268714 | 660 | .remove = cpwd_remove, |
c5f8556c | 661 | }; |
1da177e4 | 662 | |
b8ec6118 | 663 | module_platform_driver(cpwd_driver); |