[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / davinci_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * drivers/char/watchdog/davinci_wdt.c
 *
 * Watchdog driver for DaVinci DM644x/DM646x processors
 *
 * Copyright (C) 2006-2013 Texas Instruments.
 *
 * 2007 (c) MontaVista Software, Inc.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>

#define MODULE_NAME "DAVINCI-WDT: "

#define DEFAULT_HEARTBEAT 60
#define MAX_HEARTBEAT     600	/* really the max margin is 264/27MHz*/

/* Timer register set definition */
#define PID12	(0x0)
#define EMUMGT	(0x4)
#define TIM12	(0x10)
#define TIM34	(0x14)
#define PRD12	(0x18)
#define PRD34	(0x1C)
#define TCR	(0x20)
#define TGCR	(0x24)
#define WDTCR	(0x28)

/* TCR bit definitions */
#define ENAMODE12_DISABLED	(0 << 6)
#define ENAMODE12_ONESHOT	(1 << 6)
#define ENAMODE12_PERIODIC	(2 << 6)

/* TGCR bit definitions */
#define TIM12RS_UNRESET		(1 << 0)
#define TIM34RS_UNRESET		(1 << 1)
#define TIMMODE_64BIT_WDOG      (2 << 2)

/* WDTCR bit definitions */
#define WDEN			(1 << 14)
#define WDFLAG			(1 << 15)
#define WDKEY_SEQ0		(0xa5c6 << 16)
#define WDKEY_SEQ1		(0xda7e << 16)

static int heartbeat;

/*
 * struct to hold data for each WDT device
 * @base - base io address of WD device
 * @clk - source clock of WDT
 * @wdd - hold watchdog device as is in WDT core
 */
struct davinci_wdt_device {
	void __iomem		*base;
	struct clk		*clk;
	struct watchdog_device	wdd;
};

static int davinci_wdt_start(struct watchdog_device *wdd)
{
	u32 tgcr;
	u32 timer_margin;
	unsigned long wdt_freq;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	wdt_freq = clk_get_rate(davinci_wdt->clk);

	/* disable, internal clock source */
	iowrite32(0, davinci_wdt->base + TCR);
	/* reset timer, set mode to 64-bit watchdog, and unreset */
	iowrite32(0, davinci_wdt->base + TGCR);
	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
	iowrite32(tgcr, davinci_wdt->base + TGCR);
	/* clear counter regs */
	iowrite32(0, davinci_wdt->base + TIM12);
	iowrite32(0, davinci_wdt->base + TIM34);
	/* set timeout period */
	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
	iowrite32(timer_margin, davinci_wdt->base + PRD12);
	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
	iowrite32(timer_margin, davinci_wdt->base + PRD34);
	/* enable run continuously */
	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
	/* Once the WDT is in pre-active state write to
	 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	 * write protected (except for the WDKEY field)
	 */
	/* put watchdog in pre-active state */
	iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
	return 0;
}

static int davinci_wdt_ping(struct watchdog_device *wdd)
{
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* put watchdog in service state */
	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
	return 0;
}

static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
{
	u64 timer_counter;
	unsigned long freq;
	u32 val;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* if timeout has occured then return 0 */
	val = ioread32(davinci_wdt->base + WDTCR);
	if (val & WDFLAG)
		return 0;

	freq = clk_get_rate(davinci_wdt->clk);

	if (!freq)
		return 0;

	timer_counter = ioread32(davinci_wdt->base + TIM12);
	timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);

	do_div(timer_counter, freq);

	return wdd->timeout - timer_counter;
}

static int davinci_wdt_restart(struct watchdog_device *wdd,
			       unsigned long action, void *data)
{
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	u32 tgcr, wdtcr;

	/* disable, internal clock source */
	iowrite32(0, davinci_wdt->base + TCR);

	/* reset timer, set mode to 64-bit watchdog, and unreset */
	tgcr = 0;
	iowrite32(tgcr, davinci_wdt->base + TGCR);
	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
	iowrite32(tgcr, davinci_wdt->base + TGCR);

	/* clear counter and period regs */
	iowrite32(0, davinci_wdt->base + TIM12);
	iowrite32(0, davinci_wdt->base + TIM34);
	iowrite32(0, davinci_wdt->base + PRD12);
	iowrite32(0, davinci_wdt->base + PRD34);

	/* put watchdog in pre-active state */
	wdtcr = WDKEY_SEQ0 | WDEN;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	/* put watchdog in active state */
	wdtcr = WDKEY_SEQ1 | WDEN;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	/* write an invalid value to the WDKEY field to trigger a restart */
	wdtcr = 0x00004000;
	iowrite32(wdtcr, davinci_wdt->base + WDTCR);

	return 0;
}

static const struct watchdog_info davinci_wdt_info = {
	.options = WDIOF_KEEPALIVEPING,
	.identity = "DaVinci/Keystone Watchdog",
};

static const struct watchdog_ops davinci_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= davinci_wdt_start,
	.stop		= davinci_wdt_ping,
	.ping		= davinci_wdt_ping,
	.get_timeleft	= davinci_wdt_get_timeleft,
	.restart	= davinci_wdt_restart,
};

static void davinci_clk_disable_unprepare(void *data)
{
	clk_disable_unprepare(data);
}

static int davinci_wdt_probe(struct platform_device *pdev)
{
	int ret = 0;
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdd;
	struct davinci_wdt_device *davinci_wdt;

	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	if (!davinci_wdt)
		return -ENOMEM;

	davinci_wdt->clk = devm_clk_get(dev, NULL);

	if (IS_ERR(davinci_wdt->clk)) {
		if (PTR_ERR(davinci_wdt->clk) != -EPROBE_DEFER)
			dev_err(dev, "failed to get clock node\n");
		return PTR_ERR(davinci_wdt->clk);
	}

	ret = clk_prepare_enable(davinci_wdt->clk);
	if (ret) {
		dev_err(dev, "failed to prepare clock\n");
		return ret;
	}
	ret = devm_add_action_or_reset(dev, davinci_clk_disable_unprepare,
				       davinci_wdt->clk);
	if (ret)
		return ret;

	platform_set_drvdata(pdev, davinci_wdt);

	wdd			= &davinci_wdt->wdd;
	wdd->info		= &davinci_wdt_info;
	wdd->ops		= &davinci_wdt_ops;
	wdd->min_timeout	= 1;
	wdd->max_timeout	= MAX_HEARTBEAT;
	wdd->timeout		= DEFAULT_HEARTBEAT;
	wdd->parent		= dev;

	watchdog_init_timeout(wdd, heartbeat, dev);

	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);

	watchdog_set_drvdata(wdd, davinci_wdt);
	watchdog_set_nowayout(wdd, 1);
	watchdog_set_restart_priority(wdd, 128);

	davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(davinci_wdt->base))
		return PTR_ERR(davinci_wdt->base);

	return devm_watchdog_register_device(dev, wdd);
}

static const struct of_device_id davinci_wdt_of_match[] = {
	{ .compatible = "ti,davinci-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "davinci-wdt",
		.of_match_table = davinci_wdt_of_match,
	},
	.probe = davinci_wdt_probe,
};

module_platform_driver(platform_wdt_driver);

MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("DaVinci Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:davinci-wdt");
Commit	Line	Data
d0173278	1	// SPDX-License-Identifier: GPL-2.0
7d831bf5 VB	2	/*
	3	* drivers/char/watchdog/davinci_wdt.c
	4	*
	5	* Watchdog driver for DaVinci DM644x/DM646x processors
	6	*
f48f3cea	7	* Copyright (C) 2006-2013 Texas Instruments.
7d831bf5	8	*
d0173278	9	* 2007 (c) MontaVista Software, Inc.
7d831bf5 VB	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/moduleparam.h>
ac316725	14	#include <linux/mod_devicetable.h>
7d831bf5 VB	15	#include <linux/types.h>
7d831bf5 VB	16	#include <linux/kernel.h>
7d831bf5	17	#include <linux/watchdog.h>
7d831bf5	18	#include <linux/platform_device.h>
f78b0a8f	19	#include <linux/io.h>
371d3525	20	#include <linux/device.h>
9fd868f4	21	#include <linux/clk.h>
6330c707	22	#include <linux/err.h>
7d831bf5 VB	23
	24	#define MODULE_NAME "DAVINCI-WDT: "
	25
	26	#define DEFAULT_HEARTBEAT 60
	27	#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
	28
	29	/* Timer register set definition */
	30	#define PID12 (0x0)
	31	#define EMUMGT (0x4)
	32	#define TIM12 (0x10)
	33	#define TIM34 (0x14)
	34	#define PRD12 (0x18)
	35	#define PRD34 (0x1C)
	36	#define TCR (0x20)
	37	#define TGCR (0x24)
	38	#define WDTCR (0x28)
	39
	40	/* TCR bit definitions */
	41	#define ENAMODE12_DISABLED (0 << 6)
	42	#define ENAMODE12_ONESHOT (1 << 6)
	43	#define ENAMODE12_PERIODIC (2 << 6)
	44
	45	/* TGCR bit definitions */
	46	#define TIM12RS_UNRESET (1 << 0)
	47	#define TIM34RS_UNRESET (1 << 1)
	48	#define TIMMODE_64BIT_WDOG (2 << 2)
	49
	50	/* WDTCR bit definitions */
	51	#define WDEN (1 << 14)
	52	#define WDFLAG (1 << 15)
	53	#define WDKEY_SEQ0 (0xa5c6 << 16)
	54	#define WDKEY_SEQ1 (0xda7e << 16)
	55
f48f3cea	56	static int heartbeat;
6d9a6cf5 IK	57
	58	/*
	59	* struct to hold data for each WDT device
	60	* @base - base io address of WD device
	61	* @clk - source clock of WDT
	62	* @wdd - hold watchdog device as is in WDT core
	63	*/
	64	struct davinci_wdt_device {
	65	void __iomem *base;
	66	struct clk *clk;
	67	struct watchdog_device wdd;
	68	};
7d831bf5	69
f48f3cea	70	static int davinci_wdt_start(struct watchdog_device *wdd)
7d831bf5 VB	71	{
	72	u32 tgcr;
	73	u32 timer_margin;
9fd868f4	74	unsigned long wdt_freq;
6d9a6cf5	75	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
9fd868f4	76
6d9a6cf5	77	wdt_freq = clk_get_rate(davinci_wdt->clk);
7d831bf5	78
7d831bf5	79	/* disable, internal clock source */
6d9a6cf5	80	iowrite32(0, davinci_wdt->base + TCR);
7d831bf5	81	/* reset timer, set mode to 64-bit watchdog, and unreset */
6d9a6cf5	82	iowrite32(0, davinci_wdt->base + TGCR);
7d831bf5	83	tgcr = TIMMODE_64BIT_WDOG \| TIM12RS_UNRESET \| TIM34RS_UNRESET;
6d9a6cf5	84	iowrite32(tgcr, davinci_wdt->base + TGCR);
7d831bf5	85	/* clear counter regs */
6d9a6cf5 IK	86	iowrite32(0, davinci_wdt->base + TIM12);
6d9a6cf5 IK	87	iowrite32(0, davinci_wdt->base + TIM34);
7d831bf5	88	/* set timeout period */
f48f3cea	89	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
6d9a6cf5	90	iowrite32(timer_margin, davinci_wdt->base + PRD12);
f48f3cea	91	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
6d9a6cf5	92	iowrite32(timer_margin, davinci_wdt->base + PRD34);
7d831bf5	93	/* enable run continuously */
6d9a6cf5	94	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
7d831bf5 VB	95	/* Once the WDT is in pre-active state write to
	96	* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	97	* write protected (except for the WDKEY field)
	98	*/
	99	/* put watchdog in pre-active state */
6d9a6cf5	100	iowrite32(WDKEY_SEQ0 \| WDEN, davinci_wdt->base + WDTCR);
7d831bf5	101	/* put watchdog in active state */
6d9a6cf5	102	iowrite32(WDKEY_SEQ1 \| WDEN, davinci_wdt->base + WDTCR);
f48f3cea	103	return 0;
7d831bf5 VB	104	}
7d831bf5 VB	105
f48f3cea	106	static int davinci_wdt_ping(struct watchdog_device *wdd)
7d831bf5	107	{
6d9a6cf5 IK	108	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
6d9a6cf5 IK	109
f48f3cea	110	/* put watchdog in service state */
6d9a6cf5	111	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
f48f3cea	112	/* put watchdog in active state */
6d9a6cf5	113	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
f48f3cea	114	return 0;
7d831bf5 VB	115	}
7d831bf5 VB	116
a7719949 IK	117	static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
	118	{
	119	u64 timer_counter;
	120	unsigned long freq;
	121	u32 val;
	122	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	123
	124	/* if timeout has occured then return 0 */
	125	val = ioread32(davinci_wdt->base + WDTCR);
	126	if (val & WDFLAG)
	127	return 0;
	128
	129	freq = clk_get_rate(davinci_wdt->clk);
	130
	131	if (!freq)
	132	return 0;
	133
	134	timer_counter = ioread32(davinci_wdt->base + TIM12);
	135	timer_counter \|= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
	136
	137	do_div(timer_counter, freq);
	138
	139	return wdd->timeout - timer_counter;
	140	}
	141
71d1f058 DL	142	static int davinci_wdt_restart(struct watchdog_device *wdd,
	143	unsigned long action, void *data)
	144	{
	145	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	146	u32 tgcr, wdtcr;
	147
	148	/* disable, internal clock source */
	149	iowrite32(0, davinci_wdt->base + TCR);
	150
	151	/* reset timer, set mode to 64-bit watchdog, and unreset */
	152	tgcr = 0;
	153	iowrite32(tgcr, davinci_wdt->base + TGCR);
	154	tgcr = TIMMODE_64BIT_WDOG \| TIM12RS_UNRESET \| TIM34RS_UNRESET;
	155	iowrite32(tgcr, davinci_wdt->base + TGCR);
	156
	157	/* clear counter and period regs */
	158	iowrite32(0, davinci_wdt->base + TIM12);
	159	iowrite32(0, davinci_wdt->base + TIM34);
	160	iowrite32(0, davinci_wdt->base + PRD12);
	161	iowrite32(0, davinci_wdt->base + PRD34);
	162
	163	/* put watchdog in pre-active state */
	164	wdtcr = WDKEY_SEQ0 \| WDEN;
	165	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	166
	167	/* put watchdog in active state */
	168	wdtcr = WDKEY_SEQ1 \| WDEN;
	169	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	170
	171	/* write an invalid value to the WDKEY field to trigger a restart */
	172	wdtcr = 0x00004000;
	173	iowrite32(wdtcr, davinci_wdt->base + WDTCR);
	174
	175	return 0;
	176	}
	177
f48f3cea	178	static const struct watchdog_info davinci_wdt_info = {
f1a08cc9	179	.options = WDIOF_KEEPALIVEPING,
8832b200	180	.identity = "DaVinci/Keystone Watchdog",
7d831bf5 VB	181	};
7d831bf5 VB	182
f48f3cea IK	183	static const struct watchdog_ops davinci_wdt_ops = {
	184	.owner = THIS_MODULE,
	185	.start = davinci_wdt_start,
	186	.stop = davinci_wdt_ping,
	187	.ping = davinci_wdt_ping,
a7719949	188	.get_timeleft = davinci_wdt_get_timeleft,
71d1f058	189	.restart = davinci_wdt_restart,
7d831bf5 VB	190	};
7d831bf5 VB	191
cecda010 GR	192	static void davinci_clk_disable_unprepare(void *data)
	193	{
	194	clk_disable_unprepare(data);
	195	}
	196
2d991a16	197	static int davinci_wdt_probe(struct platform_device *pdev)
7d831bf5	198	{
e20880e6	199	int ret = 0;
371d3525	200	struct device *dev = &pdev->dev;
f48f3cea	201	struct watchdog_device *wdd;
6d9a6cf5 IK	202	struct davinci_wdt_device *davinci_wdt;
	203
	204	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	205	if (!davinci_wdt)
	206	return -ENOMEM;
7d831bf5	207
6d9a6cf5	208	davinci_wdt->clk = devm_clk_get(dev, NULL);
9b386574 TK	209
	210	if (IS_ERR(davinci_wdt->clk)) {
	211	if (PTR_ERR(davinci_wdt->clk) != -EPROBE_DEFER)
cecda010	212	dev_err(dev, "failed to get clock node\n");
6d9a6cf5	213	return PTR_ERR(davinci_wdt->clk);
9b386574	214	}
9fd868f4	215
8f11eb58 AY	216	ret = clk_prepare_enable(davinci_wdt->clk);
8f11eb58 AY	217	if (ret) {
cecda010	218	dev_err(dev, "failed to prepare clock\n");
8f11eb58 AY	219	return ret;
8f11eb58 AY	220	}
cecda010 GR	221	ret = devm_add_action_or_reset(dev, davinci_clk_disable_unprepare,
	222	davinci_wdt->clk);
	223	if (ret)
	224	return ret;
9fd868f4	225
6d9a6cf5 IK	226	platform_set_drvdata(pdev, davinci_wdt);
	227
	228	wdd = &davinci_wdt->wdd;
f48f3cea IK	229	wdd->info = &davinci_wdt_info;
	230	wdd->ops = &davinci_wdt_ops;
	231	wdd->min_timeout = 1;
	232	wdd->max_timeout = MAX_HEARTBEAT;
	233	wdd->timeout = DEFAULT_HEARTBEAT;
cecda010	234	wdd->parent = dev;
f48f3cea IK	235
	236	watchdog_init_timeout(wdd, heartbeat, dev);
	237
	238	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
7d831bf5	239
6d9a6cf5	240	watchdog_set_drvdata(wdd, davinci_wdt);
f48f3cea	241	watchdog_set_nowayout(wdd, 1);
71d1f058	242	watchdog_set_restart_priority(wdd, 128);
7d831bf5	243
0f0a6a28	244	davinci_wdt->base = devm_platform_ioremap_resource(pdev, 0);
cecda010 GR	245	if (IS_ERR(davinci_wdt->base))
cecda010 GR	246	return PTR_ERR(davinci_wdt->base);
7d831bf5	247
6ab6d33e	248	return devm_watchdog_register_device(dev, wdd);
7d831bf5 VB	249	}
7d831bf5 VB	250
902e2e7d MK	251	static const struct of_device_id davinci_wdt_of_match[] = {
	252	{ .compatible = "ti,davinci-wdt", },
	253	{},
	254	};
	255	MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
	256
7d831bf5 VB	257	static struct platform_driver platform_wdt_driver = {
7d831bf5 VB	258	.driver = {
84374812	259	.name = "davinci-wdt",
902e2e7d	260	.of_match_table = davinci_wdt_of_match,
7d831bf5 VB	261	},
7d831bf5 VB	262	.probe = davinci_wdt_probe,
7d831bf5 VB	263	};
7d831bf5 VB	264
b8ec6118	265	module_platform_driver(platform_wdt_driver);
7d831bf5 VB	266
	267	MODULE_AUTHOR("Texas Instruments");
	268	MODULE_DESCRIPTION("DaVinci Watchdog Driver");
	269
	270	module_param(heartbeat, int, 0);
	271	MODULE_PARM_DESC(heartbeat,
	272	"Watchdog heartbeat period in seconds from 1 to "
	273	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	274	__MODULE_STRING(DEFAULT_HEARTBEAT));
	275
	276	MODULE_LICENSE("GPL");
84374812	277	MODULE_ALIAS("platform:davinci-wdt");