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7d831bf5 VB |
1 | /* |
2 | * drivers/char/watchdog/davinci_wdt.c | |
3 | * | |
4 | * Watchdog driver for DaVinci DM644x/DM646x processors | |
5 | * | |
f48f3cea | 6 | * Copyright (C) 2006-2013 Texas Instruments. |
7d831bf5 VB |
7 | * |
8 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
7d831bf5 | 18 | #include <linux/watchdog.h> |
7d831bf5 | 19 | #include <linux/platform_device.h> |
f78b0a8f | 20 | #include <linux/io.h> |
371d3525 | 21 | #include <linux/device.h> |
9fd868f4 | 22 | #include <linux/clk.h> |
6330c707 | 23 | #include <linux/err.h> |
7d831bf5 VB |
24 | |
25 | #define MODULE_NAME "DAVINCI-WDT: " | |
26 | ||
27 | #define DEFAULT_HEARTBEAT 60 | |
28 | #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/ | |
29 | ||
30 | /* Timer register set definition */ | |
31 | #define PID12 (0x0) | |
32 | #define EMUMGT (0x4) | |
33 | #define TIM12 (0x10) | |
34 | #define TIM34 (0x14) | |
35 | #define PRD12 (0x18) | |
36 | #define PRD34 (0x1C) | |
37 | #define TCR (0x20) | |
38 | #define TGCR (0x24) | |
39 | #define WDTCR (0x28) | |
40 | ||
41 | /* TCR bit definitions */ | |
42 | #define ENAMODE12_DISABLED (0 << 6) | |
43 | #define ENAMODE12_ONESHOT (1 << 6) | |
44 | #define ENAMODE12_PERIODIC (2 << 6) | |
45 | ||
46 | /* TGCR bit definitions */ | |
47 | #define TIM12RS_UNRESET (1 << 0) | |
48 | #define TIM34RS_UNRESET (1 << 1) | |
49 | #define TIMMODE_64BIT_WDOG (2 << 2) | |
50 | ||
51 | /* WDTCR bit definitions */ | |
52 | #define WDEN (1 << 14) | |
53 | #define WDFLAG (1 << 15) | |
54 | #define WDKEY_SEQ0 (0xa5c6 << 16) | |
55 | #define WDKEY_SEQ1 (0xda7e << 16) | |
56 | ||
f48f3cea | 57 | static int heartbeat; |
6d9a6cf5 IK |
58 | |
59 | /* | |
60 | * struct to hold data for each WDT device | |
61 | * @base - base io address of WD device | |
62 | * @clk - source clock of WDT | |
63 | * @wdd - hold watchdog device as is in WDT core | |
64 | */ | |
65 | struct davinci_wdt_device { | |
66 | void __iomem *base; | |
67 | struct clk *clk; | |
68 | struct watchdog_device wdd; | |
69 | }; | |
7d831bf5 | 70 | |
f48f3cea | 71 | static int davinci_wdt_start(struct watchdog_device *wdd) |
7d831bf5 VB |
72 | { |
73 | u32 tgcr; | |
74 | u32 timer_margin; | |
9fd868f4 | 75 | unsigned long wdt_freq; |
6d9a6cf5 | 76 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
9fd868f4 | 77 | |
6d9a6cf5 | 78 | wdt_freq = clk_get_rate(davinci_wdt->clk); |
7d831bf5 | 79 | |
7d831bf5 | 80 | /* disable, internal clock source */ |
6d9a6cf5 | 81 | iowrite32(0, davinci_wdt->base + TCR); |
7d831bf5 | 82 | /* reset timer, set mode to 64-bit watchdog, and unreset */ |
6d9a6cf5 | 83 | iowrite32(0, davinci_wdt->base + TGCR); |
7d831bf5 | 84 | tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET; |
6d9a6cf5 | 85 | iowrite32(tgcr, davinci_wdt->base + TGCR); |
7d831bf5 | 86 | /* clear counter regs */ |
6d9a6cf5 IK |
87 | iowrite32(0, davinci_wdt->base + TIM12); |
88 | iowrite32(0, davinci_wdt->base + TIM34); | |
7d831bf5 | 89 | /* set timeout period */ |
f48f3cea | 90 | timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff); |
6d9a6cf5 | 91 | iowrite32(timer_margin, davinci_wdt->base + PRD12); |
f48f3cea | 92 | timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32); |
6d9a6cf5 | 93 | iowrite32(timer_margin, davinci_wdt->base + PRD34); |
7d831bf5 | 94 | /* enable run continuously */ |
6d9a6cf5 | 95 | iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); |
7d831bf5 VB |
96 | /* Once the WDT is in pre-active state write to |
97 | * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are | |
98 | * write protected (except for the WDKEY field) | |
99 | */ | |
100 | /* put watchdog in pre-active state */ | |
6d9a6cf5 | 101 | iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR); |
7d831bf5 | 102 | /* put watchdog in active state */ |
6d9a6cf5 | 103 | iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR); |
f48f3cea | 104 | return 0; |
7d831bf5 VB |
105 | } |
106 | ||
f48f3cea | 107 | static int davinci_wdt_ping(struct watchdog_device *wdd) |
7d831bf5 | 108 | { |
6d9a6cf5 IK |
109 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); |
110 | ||
f48f3cea | 111 | /* put watchdog in service state */ |
6d9a6cf5 | 112 | iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR); |
f48f3cea | 113 | /* put watchdog in active state */ |
6d9a6cf5 | 114 | iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR); |
f48f3cea | 115 | return 0; |
7d831bf5 VB |
116 | } |
117 | ||
a7719949 IK |
118 | static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd) |
119 | { | |
120 | u64 timer_counter; | |
121 | unsigned long freq; | |
122 | u32 val; | |
123 | struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd); | |
124 | ||
125 | /* if timeout has occured then return 0 */ | |
126 | val = ioread32(davinci_wdt->base + WDTCR); | |
127 | if (val & WDFLAG) | |
128 | return 0; | |
129 | ||
130 | freq = clk_get_rate(davinci_wdt->clk); | |
131 | ||
132 | if (!freq) | |
133 | return 0; | |
134 | ||
135 | timer_counter = ioread32(davinci_wdt->base + TIM12); | |
136 | timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32); | |
137 | ||
138 | do_div(timer_counter, freq); | |
139 | ||
140 | return wdd->timeout - timer_counter; | |
141 | } | |
142 | ||
f48f3cea | 143 | static const struct watchdog_info davinci_wdt_info = { |
f1a08cc9 | 144 | .options = WDIOF_KEEPALIVEPING, |
8832b200 | 145 | .identity = "DaVinci/Keystone Watchdog", |
7d831bf5 VB |
146 | }; |
147 | ||
f48f3cea IK |
148 | static const struct watchdog_ops davinci_wdt_ops = { |
149 | .owner = THIS_MODULE, | |
150 | .start = davinci_wdt_start, | |
151 | .stop = davinci_wdt_ping, | |
152 | .ping = davinci_wdt_ping, | |
a7719949 | 153 | .get_timeleft = davinci_wdt_get_timeleft, |
7d831bf5 VB |
154 | }; |
155 | ||
2d991a16 | 156 | static int davinci_wdt_probe(struct platform_device *pdev) |
7d831bf5 | 157 | { |
e20880e6 | 158 | int ret = 0; |
371d3525 | 159 | struct device *dev = &pdev->dev; |
e20880e6 | 160 | struct resource *wdt_mem; |
f48f3cea | 161 | struct watchdog_device *wdd; |
6d9a6cf5 IK |
162 | struct davinci_wdt_device *davinci_wdt; |
163 | ||
164 | davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL); | |
165 | if (!davinci_wdt) | |
166 | return -ENOMEM; | |
7d831bf5 | 167 | |
6d9a6cf5 IK |
168 | davinci_wdt->clk = devm_clk_get(dev, NULL); |
169 | if (WARN_ON(IS_ERR(davinci_wdt->clk))) | |
170 | return PTR_ERR(davinci_wdt->clk); | |
9fd868f4 | 171 | |
6d9a6cf5 | 172 | clk_prepare_enable(davinci_wdt->clk); |
9fd868f4 | 173 | |
6d9a6cf5 IK |
174 | platform_set_drvdata(pdev, davinci_wdt); |
175 | ||
176 | wdd = &davinci_wdt->wdd; | |
f48f3cea IK |
177 | wdd->info = &davinci_wdt_info; |
178 | wdd->ops = &davinci_wdt_ops; | |
179 | wdd->min_timeout = 1; | |
180 | wdd->max_timeout = MAX_HEARTBEAT; | |
181 | wdd->timeout = DEFAULT_HEARTBEAT; | |
6551881c | 182 | wdd->parent = &pdev->dev; |
f48f3cea IK |
183 | |
184 | watchdog_init_timeout(wdd, heartbeat, dev); | |
185 | ||
186 | dev_info(dev, "heartbeat %d sec\n", wdd->timeout); | |
7d831bf5 | 187 | |
6d9a6cf5 | 188 | watchdog_set_drvdata(wdd, davinci_wdt); |
f48f3cea | 189 | watchdog_set_nowayout(wdd, 1); |
7d831bf5 | 190 | |
f712eacf | 191 | wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6d9a6cf5 IK |
192 | davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem); |
193 | if (IS_ERR(davinci_wdt->base)) | |
194 | return PTR_ERR(davinci_wdt->base); | |
7d831bf5 | 195 | |
f48f3cea IK |
196 | ret = watchdog_register_device(wdd); |
197 | if (ret < 0) | |
198 | dev_err(dev, "cannot register watchdog device\n"); | |
7d831bf5 VB |
199 | |
200 | return ret; | |
201 | } | |
202 | ||
4b12b896 | 203 | static int davinci_wdt_remove(struct platform_device *pdev) |
7d831bf5 | 204 | { |
6d9a6cf5 IK |
205 | struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev); |
206 | ||
207 | watchdog_unregister_device(&davinci_wdt->wdd); | |
208 | clk_disable_unprepare(davinci_wdt->clk); | |
9fd868f4 | 209 | |
7d831bf5 VB |
210 | return 0; |
211 | } | |
212 | ||
902e2e7d MK |
213 | static const struct of_device_id davinci_wdt_of_match[] = { |
214 | { .compatible = "ti,davinci-wdt", }, | |
215 | {}, | |
216 | }; | |
217 | MODULE_DEVICE_TABLE(of, davinci_wdt_of_match); | |
218 | ||
7d831bf5 VB |
219 | static struct platform_driver platform_wdt_driver = { |
220 | .driver = { | |
84374812 | 221 | .name = "davinci-wdt", |
902e2e7d | 222 | .of_match_table = davinci_wdt_of_match, |
7d831bf5 VB |
223 | }, |
224 | .probe = davinci_wdt_probe, | |
82268714 | 225 | .remove = davinci_wdt_remove, |
7d831bf5 VB |
226 | }; |
227 | ||
b8ec6118 | 228 | module_platform_driver(platform_wdt_driver); |
7d831bf5 VB |
229 | |
230 | MODULE_AUTHOR("Texas Instruments"); | |
231 | MODULE_DESCRIPTION("DaVinci Watchdog Driver"); | |
232 | ||
233 | module_param(heartbeat, int, 0); | |
234 | MODULE_PARM_DESC(heartbeat, | |
235 | "Watchdog heartbeat period in seconds from 1 to " | |
236 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
237 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
238 | ||
239 | MODULE_LICENSE("GPL"); | |
84374812 | 240 | MODULE_ALIAS("platform:davinci-wdt"); |