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c9353ae1 JI |
1 | /* |
2 | * Copyright 2010-2011 Picochip Ltd., Jamie Iles | |
3 | * http://www.picochip.com | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * This file implements a driver for the Synopsys DesignWare watchdog device | |
58a251f2 | 11 | * in the many subsystems. The watchdog has 16 different timeout periods |
c9353ae1 JI |
12 | * and these are a function of the input clock frequency. |
13 | * | |
14 | * The DesignWare watchdog cannot be stopped once it has been started so we | |
f29a72c2 GR |
15 | * do not implement a stop function. The watchdog core will continue to send |
16 | * heartbeat requests after the watchdog device has been closed. | |
c9353ae1 | 17 | */ |
27c766aa JP |
18 | |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
c9353ae1 JI |
20 | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/clk.h> | |
31228f43 | 23 | #include <linux/delay.h> |
c9353ae1 | 24 | #include <linux/err.h> |
c9353ae1 JI |
25 | #include <linux/io.h> |
26 | #include <linux/kernel.h> | |
c9353ae1 JI |
27 | #include <linux/module.h> |
28 | #include <linux/moduleparam.h> | |
58e56373 | 29 | #include <linux/of.h> |
c9353ae1 JI |
30 | #include <linux/pm.h> |
31 | #include <linux/platform_device.h> | |
65a3b693 | 32 | #include <linux/reset.h> |
c9353ae1 JI |
33 | #include <linux/watchdog.h> |
34 | ||
35 | #define WDOG_CONTROL_REG_OFFSET 0x00 | |
36 | #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 | |
d4ef6f3c | 37 | #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 |
c9353ae1 | 38 | #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 |
dfa07141 | 39 | #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 |
c9353ae1 JI |
40 | #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 |
41 | #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c | |
42 | #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 | |
43 | ||
44 | /* The maximum TOP (timeout period) value that can be set in the watchdog. */ | |
45 | #define DW_WDT_MAX_TOP 15 | |
46 | ||
b5ade9bc DA |
47 | #define DW_WDT_DEFAULT_SECONDS 30 |
48 | ||
86a1e189 WVS |
49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
50 | module_param(nowayout, bool, 0); | |
c9353ae1 JI |
51 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
52 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
53 | ||
f29a72c2 | 54 | struct dw_wdt { |
c9353ae1 JI |
55 | void __iomem *regs; |
56 | struct clk *clk; | |
c97344f7 | 57 | unsigned long rate; |
f29a72c2 | 58 | struct watchdog_device wdd; |
65a3b693 | 59 | struct reset_control *rst; |
f29a72c2 GR |
60 | }; |
61 | ||
62 | #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) | |
c9353ae1 | 63 | |
f29a72c2 | 64 | static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) |
c9353ae1 | 65 | { |
f29a72c2 | 66 | return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & |
c9353ae1 JI |
67 | WDOG_CONTROL_REG_WDT_EN_MASK; |
68 | } | |
69 | ||
f29a72c2 | 70 | static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top) |
c9353ae1 JI |
71 | { |
72 | /* | |
73 | * There are 16 possible timeout values in 0..15 where the number of | |
74 | * cycles is 2 ^ (16 + i) and the watchdog counts down. | |
75 | */ | |
c97344f7 | 76 | return (1U << (16 + top)) / dw_wdt->rate; |
c9353ae1 JI |
77 | } |
78 | ||
f29a72c2 | 79 | static int dw_wdt_get_top(struct dw_wdt *dw_wdt) |
c9353ae1 | 80 | { |
f29a72c2 | 81 | int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; |
c9353ae1 | 82 | |
f29a72c2 | 83 | return dw_wdt_top_in_seconds(dw_wdt, top); |
c9353ae1 JI |
84 | } |
85 | ||
f29a72c2 | 86 | static int dw_wdt_ping(struct watchdog_device *wdd) |
c9353ae1 | 87 | { |
f29a72c2 | 88 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 89 | |
f29a72c2 | 90 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + |
a0085010 | 91 | WDOG_COUNTER_RESTART_REG_OFFSET); |
f29a72c2 GR |
92 | |
93 | return 0; | |
a0085010 DA |
94 | } |
95 | ||
f29a72c2 | 96 | static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) |
c9353ae1 | 97 | { |
f29a72c2 | 98 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 JI |
99 | int i, top_val = DW_WDT_MAX_TOP; |
100 | ||
101 | /* | |
102 | * Iterate over the timeout values until we find the closest match. We | |
103 | * always look for >=. | |
104 | */ | |
105 | for (i = 0; i <= DW_WDT_MAX_TOP; ++i) | |
f29a72c2 | 106 | if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) { |
c9353ae1 JI |
107 | top_val = i; |
108 | break; | |
109 | } | |
110 | ||
a0085010 DA |
111 | /* |
112 | * Set the new value in the watchdog. Some versions of dw_wdt | |
113 | * have have TOPINIT in the TIMEOUT_RANGE register (as per | |
114 | * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we | |
115 | * effectively get a pat of the watchdog right here. | |
116 | */ | |
dfa07141 | 117 | writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, |
f29a72c2 | 118 | dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
c9353ae1 | 119 | |
f29a72c2 | 120 | wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val); |
a0085010 | 121 | |
f29a72c2 GR |
122 | return 0; |
123 | } | |
124 | ||
d4ef6f3c BN |
125 | static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) |
126 | { | |
127 | u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
128 | ||
129 | /* Disable interrupt mode; always perform system reset. */ | |
130 | val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; | |
131 | /* Enable watchdog. */ | |
132 | val |= WDOG_CONTROL_REG_WDT_EN_MASK; | |
133 | writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
134 | } | |
135 | ||
f29a72c2 GR |
136 | static int dw_wdt_start(struct watchdog_device *wdd) |
137 | { | |
138 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
139 | ||
140 | dw_wdt_set_timeout(wdd, wdd->timeout); | |
d4ef6f3c | 141 | dw_wdt_arm_system_reset(dw_wdt); |
f29a72c2 GR |
142 | |
143 | return 0; | |
c9353ae1 JI |
144 | } |
145 | ||
f6375d39 OR |
146 | static int dw_wdt_stop(struct watchdog_device *wdd) |
147 | { | |
148 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
149 | ||
150 | if (!dw_wdt->rst) { | |
151 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | reset_control_assert(dw_wdt->rst); | |
156 | reset_control_deassert(dw_wdt->rst); | |
157 | ||
158 | return 0; | |
159 | } | |
160 | ||
a70dcc01 GR |
161 | static int dw_wdt_restart(struct watchdog_device *wdd, |
162 | unsigned long action, void *data) | |
31228f43 | 163 | { |
a70dcc01 | 164 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
31228f43 | 165 | |
f29a72c2 | 166 | writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
d4ef6f3c | 167 | if (dw_wdt_is_enabled(dw_wdt)) |
f29a72c2 GR |
168 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, |
169 | dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); | |
31228f43 | 170 | else |
d4ef6f3c | 171 | dw_wdt_arm_system_reset(dw_wdt); |
31228f43 JZ |
172 | |
173 | /* wait for reset to assert... */ | |
174 | mdelay(500); | |
175 | ||
a70dcc01 | 176 | return 0; |
31228f43 JZ |
177 | } |
178 | ||
f29a72c2 | 179 | static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) |
c9353ae1 | 180 | { |
f29a72c2 | 181 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 182 | |
f29a72c2 | 183 | return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) / |
c97344f7 | 184 | dw_wdt->rate; |
c9353ae1 JI |
185 | } |
186 | ||
187 | static const struct watchdog_info dw_wdt_ident = { | |
188 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | | |
189 | WDIOF_MAGICCLOSE, | |
190 | .identity = "Synopsys DesignWare Watchdog", | |
191 | }; | |
192 | ||
f29a72c2 GR |
193 | static const struct watchdog_ops dw_wdt_ops = { |
194 | .owner = THIS_MODULE, | |
195 | .start = dw_wdt_start, | |
f6375d39 | 196 | .stop = dw_wdt_stop, |
f29a72c2 GR |
197 | .ping = dw_wdt_ping, |
198 | .set_timeout = dw_wdt_set_timeout, | |
199 | .get_timeleft = dw_wdt_get_timeleft, | |
a70dcc01 | 200 | .restart = dw_wdt_restart, |
f29a72c2 | 201 | }; |
c9353ae1 | 202 | |
ad83c6cb | 203 | #ifdef CONFIG_PM_SLEEP |
c9353ae1 JI |
204 | static int dw_wdt_suspend(struct device *dev) |
205 | { | |
f29a72c2 GR |
206 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
207 | ||
208 | clk_disable_unprepare(dw_wdt->clk); | |
c9353ae1 JI |
209 | |
210 | return 0; | |
211 | } | |
212 | ||
213 | static int dw_wdt_resume(struct device *dev) | |
214 | { | |
f29a72c2 GR |
215 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
216 | int err = clk_prepare_enable(dw_wdt->clk); | |
c9353ae1 JI |
217 | |
218 | if (err) | |
219 | return err; | |
220 | ||
f29a72c2 | 221 | dw_wdt_ping(&dw_wdt->wdd); |
c9353ae1 JI |
222 | |
223 | return 0; | |
224 | } | |
ad83c6cb | 225 | #endif /* CONFIG_PM_SLEEP */ |
c9353ae1 | 226 | |
ad83c6cb | 227 | static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); |
c9353ae1 | 228 | |
2d991a16 | 229 | static int dw_wdt_drv_probe(struct platform_device *pdev) |
c9353ae1 | 230 | { |
f29a72c2 GR |
231 | struct device *dev = &pdev->dev; |
232 | struct watchdog_device *wdd; | |
233 | struct dw_wdt *dw_wdt; | |
234 | struct resource *mem; | |
c9353ae1 | 235 | int ret; |
c9353ae1 | 236 | |
f29a72c2 GR |
237 | dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); |
238 | if (!dw_wdt) | |
239 | return -ENOMEM; | |
240 | ||
241 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
242 | dw_wdt->regs = devm_ioremap_resource(dev, mem); | |
243 | if (IS_ERR(dw_wdt->regs)) | |
244 | return PTR_ERR(dw_wdt->regs); | |
c9353ae1 | 245 | |
f29a72c2 GR |
246 | dw_wdt->clk = devm_clk_get(dev, NULL); |
247 | if (IS_ERR(dw_wdt->clk)) | |
248 | return PTR_ERR(dw_wdt->clk); | |
c9353ae1 | 249 | |
f29a72c2 | 250 | ret = clk_prepare_enable(dw_wdt->clk); |
c9353ae1 | 251 | if (ret) |
cf3cc8c2 | 252 | return ret; |
c9353ae1 | 253 | |
c97344f7 GR |
254 | dw_wdt->rate = clk_get_rate(dw_wdt->clk); |
255 | if (dw_wdt->rate == 0) { | |
256 | ret = -EINVAL; | |
257 | goto out_disable_clk; | |
258 | } | |
259 | ||
65a3b693 ST |
260 | dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); |
261 | if (IS_ERR(dw_wdt->rst)) { | |
262 | ret = PTR_ERR(dw_wdt->rst); | |
263 | goto out_disable_clk; | |
264 | } | |
265 | ||
266 | reset_control_deassert(dw_wdt->rst); | |
267 | ||
f29a72c2 GR |
268 | wdd = &dw_wdt->wdd; |
269 | wdd->info = &dw_wdt_ident; | |
270 | wdd->ops = &dw_wdt_ops; | |
271 | wdd->min_timeout = 1; | |
272 | wdd->max_hw_heartbeat_ms = | |
273 | dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000; | |
274 | wdd->parent = dev; | |
275 | ||
276 | watchdog_set_drvdata(wdd, dw_wdt); | |
277 | watchdog_set_nowayout(wdd, nowayout); | |
278 | watchdog_init_timeout(wdd, 0, dev); | |
279 | ||
280 | /* | |
281 | * If the watchdog is already running, use its already configured | |
282 | * timeout. Otherwise use the default or the value provided through | |
283 | * devicetree. | |
284 | */ | |
285 | if (dw_wdt_is_enabled(dw_wdt)) { | |
286 | wdd->timeout = dw_wdt_get_top(dw_wdt); | |
287 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
288 | } else { | |
289 | wdd->timeout = DW_WDT_DEFAULT_SECONDS; | |
290 | watchdog_init_timeout(wdd, 0, dev); | |
291 | } | |
292 | ||
293 | platform_set_drvdata(pdev, dw_wdt); | |
294 | ||
a70dcc01 GR |
295 | watchdog_set_restart_priority(wdd, 128); |
296 | ||
f29a72c2 | 297 | ret = watchdog_register_device(wdd); |
c9353ae1 JI |
298 | if (ret) |
299 | goto out_disable_clk; | |
300 | ||
c9353ae1 JI |
301 | return 0; |
302 | ||
303 | out_disable_clk: | |
f29a72c2 | 304 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
305 | return ret; |
306 | } | |
307 | ||
4b12b896 | 308 | static int dw_wdt_drv_remove(struct platform_device *pdev) |
c9353ae1 | 309 | { |
f29a72c2 | 310 | struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); |
c9353ae1 | 311 | |
f29a72c2 | 312 | watchdog_unregister_device(&dw_wdt->wdd); |
65a3b693 | 313 | reset_control_assert(dw_wdt->rst); |
f29a72c2 | 314 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
58e56373 DN |
319 | #ifdef CONFIG_OF |
320 | static const struct of_device_id dw_wdt_of_match[] = { | |
321 | { .compatible = "snps,dw-wdt", }, | |
322 | { /* sentinel */ } | |
323 | }; | |
324 | MODULE_DEVICE_TABLE(of, dw_wdt_of_match); | |
325 | #endif | |
326 | ||
c9353ae1 JI |
327 | static struct platform_driver dw_wdt_driver = { |
328 | .probe = dw_wdt_drv_probe, | |
82268714 | 329 | .remove = dw_wdt_drv_remove, |
c9353ae1 JI |
330 | .driver = { |
331 | .name = "dw_wdt", | |
58e56373 | 332 | .of_match_table = of_match_ptr(dw_wdt_of_match), |
c9353ae1 | 333 | .pm = &dw_wdt_pm_ops, |
c9353ae1 JI |
334 | }, |
335 | }; | |
336 | ||
b8ec6118 | 337 | module_platform_driver(dw_wdt_driver); |
c9353ae1 JI |
338 | |
339 | MODULE_AUTHOR("Jamie Iles"); | |
340 | MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); | |
341 | MODULE_LICENSE("GPL"); |