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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c9353ae1 JI |
2 | /* |
3 | * Copyright 2010-2011 Picochip Ltd., Jamie Iles | |
4 | * http://www.picochip.com | |
5 | * | |
c9353ae1 | 6 | * This file implements a driver for the Synopsys DesignWare watchdog device |
58a251f2 | 7 | * in the many subsystems. The watchdog has 16 different timeout periods |
c9353ae1 JI |
8 | * and these are a function of the input clock frequency. |
9 | * | |
10 | * The DesignWare watchdog cannot be stopped once it has been started so we | |
f29a72c2 GR |
11 | * do not implement a stop function. The watchdog core will continue to send |
12 | * heartbeat requests after the watchdog device has been closed. | |
c9353ae1 | 13 | */ |
27c766aa | 14 | |
c9353ae1 JI |
15 | #include <linux/bitops.h> |
16 | #include <linux/clk.h> | |
31228f43 | 17 | #include <linux/delay.h> |
c9353ae1 | 18 | #include <linux/err.h> |
c9353ae1 JI |
19 | #include <linux/io.h> |
20 | #include <linux/kernel.h> | |
c9353ae1 JI |
21 | #include <linux/module.h> |
22 | #include <linux/moduleparam.h> | |
58e56373 | 23 | #include <linux/of.h> |
c9353ae1 JI |
24 | #include <linux/pm.h> |
25 | #include <linux/platform_device.h> | |
65a3b693 | 26 | #include <linux/reset.h> |
c9353ae1 JI |
27 | #include <linux/watchdog.h> |
28 | ||
29 | #define WDOG_CONTROL_REG_OFFSET 0x00 | |
30 | #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 | |
a81abbb4 | 31 | #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 |
c9353ae1 | 32 | #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 |
dfa07141 | 33 | #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 |
c9353ae1 JI |
34 | #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 |
35 | #define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c | |
36 | #define WDOG_COUNTER_RESTART_KICK_VALUE 0x76 | |
37 | ||
38 | /* The maximum TOP (timeout period) value that can be set in the watchdog. */ | |
39 | #define DW_WDT_MAX_TOP 15 | |
40 | ||
b5ade9bc DA |
41 | #define DW_WDT_DEFAULT_SECONDS 30 |
42 | ||
86a1e189 WVS |
43 | static bool nowayout = WATCHDOG_NOWAYOUT; |
44 | module_param(nowayout, bool, 0); | |
c9353ae1 JI |
45 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
46 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
47 | ||
f29a72c2 | 48 | struct dw_wdt { |
c9353ae1 JI |
49 | void __iomem *regs; |
50 | struct clk *clk; | |
c97344f7 | 51 | unsigned long rate; |
f29a72c2 | 52 | struct watchdog_device wdd; |
65a3b693 | 53 | struct reset_control *rst; |
8c088370 BN |
54 | /* Save/restore */ |
55 | u32 control; | |
56 | u32 timeout; | |
f29a72c2 GR |
57 | }; |
58 | ||
59 | #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) | |
c9353ae1 | 60 | |
f29a72c2 | 61 | static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt) |
c9353ae1 | 62 | { |
f29a72c2 | 63 | return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) & |
c9353ae1 JI |
64 | WDOG_CONTROL_REG_WDT_EN_MASK; |
65 | } | |
66 | ||
f29a72c2 | 67 | static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top) |
c9353ae1 JI |
68 | { |
69 | /* | |
70 | * There are 16 possible timeout values in 0..15 where the number of | |
71 | * cycles is 2 ^ (16 + i) and the watchdog counts down. | |
72 | */ | |
c97344f7 | 73 | return (1U << (16 + top)) / dw_wdt->rate; |
c9353ae1 JI |
74 | } |
75 | ||
f29a72c2 | 76 | static int dw_wdt_get_top(struct dw_wdt *dw_wdt) |
c9353ae1 | 77 | { |
f29a72c2 | 78 | int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF; |
c9353ae1 | 79 | |
f29a72c2 | 80 | return dw_wdt_top_in_seconds(dw_wdt, top); |
c9353ae1 JI |
81 | } |
82 | ||
f29a72c2 | 83 | static int dw_wdt_ping(struct watchdog_device *wdd) |
c9353ae1 | 84 | { |
f29a72c2 | 85 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 86 | |
f29a72c2 | 87 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + |
a0085010 | 88 | WDOG_COUNTER_RESTART_REG_OFFSET); |
f29a72c2 GR |
89 | |
90 | return 0; | |
a0085010 DA |
91 | } |
92 | ||
f29a72c2 | 93 | static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) |
c9353ae1 | 94 | { |
f29a72c2 | 95 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 JI |
96 | int i, top_val = DW_WDT_MAX_TOP; |
97 | ||
98 | /* | |
99 | * Iterate over the timeout values until we find the closest match. We | |
100 | * always look for >=. | |
101 | */ | |
102 | for (i = 0; i <= DW_WDT_MAX_TOP; ++i) | |
f29a72c2 | 103 | if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) { |
c9353ae1 JI |
104 | top_val = i; |
105 | break; | |
106 | } | |
107 | ||
a0085010 DA |
108 | /* |
109 | * Set the new value in the watchdog. Some versions of dw_wdt | |
110 | * have have TOPINIT in the TIMEOUT_RANGE register (as per | |
111 | * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we | |
112 | * effectively get a pat of the watchdog right here. | |
113 | */ | |
dfa07141 | 114 | writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT, |
f29a72c2 | 115 | dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
c9353ae1 | 116 | |
f29a72c2 | 117 | wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val); |
a0085010 | 118 | |
f29a72c2 GR |
119 | return 0; |
120 | } | |
121 | ||
a81abbb4 BN |
122 | static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) |
123 | { | |
124 | u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
125 | ||
126 | /* Disable interrupt mode; always perform system reset. */ | |
127 | val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; | |
128 | /* Enable watchdog. */ | |
129 | val |= WDOG_CONTROL_REG_WDT_EN_MASK; | |
130 | writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
131 | } | |
132 | ||
f29a72c2 GR |
133 | static int dw_wdt_start(struct watchdog_device *wdd) |
134 | { | |
135 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
136 | ||
137 | dw_wdt_set_timeout(wdd, wdd->timeout); | |
a81abbb4 | 138 | dw_wdt_arm_system_reset(dw_wdt); |
f29a72c2 GR |
139 | |
140 | return 0; | |
c9353ae1 JI |
141 | } |
142 | ||
1bfe8889 OR |
143 | static int dw_wdt_stop(struct watchdog_device *wdd) |
144 | { | |
145 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); | |
146 | ||
147 | if (!dw_wdt->rst) { | |
148 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
149 | return 0; | |
150 | } | |
151 | ||
152 | reset_control_assert(dw_wdt->rst); | |
153 | reset_control_deassert(dw_wdt->rst); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
a70dcc01 GR |
158 | static int dw_wdt_restart(struct watchdog_device *wdd, |
159 | unsigned long action, void *data) | |
31228f43 | 160 | { |
a70dcc01 | 161 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
31228f43 | 162 | |
f29a72c2 | 163 | writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
a81abbb4 | 164 | if (dw_wdt_is_enabled(dw_wdt)) |
f29a72c2 GR |
165 | writel(WDOG_COUNTER_RESTART_KICK_VALUE, |
166 | dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); | |
31228f43 | 167 | else |
a81abbb4 | 168 | dw_wdt_arm_system_reset(dw_wdt); |
31228f43 JZ |
169 | |
170 | /* wait for reset to assert... */ | |
171 | mdelay(500); | |
172 | ||
a70dcc01 | 173 | return 0; |
31228f43 JZ |
174 | } |
175 | ||
f29a72c2 | 176 | static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd) |
c9353ae1 | 177 | { |
f29a72c2 | 178 | struct dw_wdt *dw_wdt = to_dw_wdt(wdd); |
c9353ae1 | 179 | |
f29a72c2 | 180 | return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) / |
c97344f7 | 181 | dw_wdt->rate; |
c9353ae1 JI |
182 | } |
183 | ||
184 | static const struct watchdog_info dw_wdt_ident = { | |
185 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | | |
186 | WDIOF_MAGICCLOSE, | |
187 | .identity = "Synopsys DesignWare Watchdog", | |
188 | }; | |
189 | ||
f29a72c2 GR |
190 | static const struct watchdog_ops dw_wdt_ops = { |
191 | .owner = THIS_MODULE, | |
192 | .start = dw_wdt_start, | |
1bfe8889 | 193 | .stop = dw_wdt_stop, |
f29a72c2 GR |
194 | .ping = dw_wdt_ping, |
195 | .set_timeout = dw_wdt_set_timeout, | |
196 | .get_timeleft = dw_wdt_get_timeleft, | |
a70dcc01 | 197 | .restart = dw_wdt_restart, |
f29a72c2 | 198 | }; |
c9353ae1 | 199 | |
ad83c6cb | 200 | #ifdef CONFIG_PM_SLEEP |
c9353ae1 JI |
201 | static int dw_wdt_suspend(struct device *dev) |
202 | { | |
f29a72c2 GR |
203 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
204 | ||
8c088370 BN |
205 | dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); |
206 | dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); | |
207 | ||
f29a72c2 | 208 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
209 | |
210 | return 0; | |
211 | } | |
212 | ||
213 | static int dw_wdt_resume(struct device *dev) | |
214 | { | |
f29a72c2 GR |
215 | struct dw_wdt *dw_wdt = dev_get_drvdata(dev); |
216 | int err = clk_prepare_enable(dw_wdt->clk); | |
c9353ae1 JI |
217 | |
218 | if (err) | |
219 | return err; | |
220 | ||
8c088370 BN |
221 | writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); |
222 | writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); | |
223 | ||
f29a72c2 | 224 | dw_wdt_ping(&dw_wdt->wdd); |
c9353ae1 JI |
225 | |
226 | return 0; | |
227 | } | |
ad83c6cb | 228 | #endif /* CONFIG_PM_SLEEP */ |
c9353ae1 | 229 | |
ad83c6cb | 230 | static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); |
c9353ae1 | 231 | |
2d991a16 | 232 | static int dw_wdt_drv_probe(struct platform_device *pdev) |
c9353ae1 | 233 | { |
f29a72c2 GR |
234 | struct device *dev = &pdev->dev; |
235 | struct watchdog_device *wdd; | |
236 | struct dw_wdt *dw_wdt; | |
c9353ae1 | 237 | int ret; |
c9353ae1 | 238 | |
f29a72c2 GR |
239 | dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL); |
240 | if (!dw_wdt) | |
241 | return -ENOMEM; | |
242 | ||
0f0a6a28 | 243 | dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0); |
f29a72c2 GR |
244 | if (IS_ERR(dw_wdt->regs)) |
245 | return PTR_ERR(dw_wdt->regs); | |
c9353ae1 | 246 | |
f29a72c2 GR |
247 | dw_wdt->clk = devm_clk_get(dev, NULL); |
248 | if (IS_ERR(dw_wdt->clk)) | |
249 | return PTR_ERR(dw_wdt->clk); | |
c9353ae1 | 250 | |
f29a72c2 | 251 | ret = clk_prepare_enable(dw_wdt->clk); |
c9353ae1 | 252 | if (ret) |
cf3cc8c2 | 253 | return ret; |
c9353ae1 | 254 | |
c97344f7 GR |
255 | dw_wdt->rate = clk_get_rate(dw_wdt->clk); |
256 | if (dw_wdt->rate == 0) { | |
257 | ret = -EINVAL; | |
258 | goto out_disable_clk; | |
259 | } | |
260 | ||
65a3b693 ST |
261 | dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); |
262 | if (IS_ERR(dw_wdt->rst)) { | |
263 | ret = PTR_ERR(dw_wdt->rst); | |
264 | goto out_disable_clk; | |
265 | } | |
266 | ||
267 | reset_control_deassert(dw_wdt->rst); | |
268 | ||
f29a72c2 GR |
269 | wdd = &dw_wdt->wdd; |
270 | wdd->info = &dw_wdt_ident; | |
271 | wdd->ops = &dw_wdt_ops; | |
272 | wdd->min_timeout = 1; | |
273 | wdd->max_hw_heartbeat_ms = | |
274 | dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000; | |
275 | wdd->parent = dev; | |
276 | ||
277 | watchdog_set_drvdata(wdd, dw_wdt); | |
278 | watchdog_set_nowayout(wdd, nowayout); | |
279 | watchdog_init_timeout(wdd, 0, dev); | |
280 | ||
281 | /* | |
282 | * If the watchdog is already running, use its already configured | |
283 | * timeout. Otherwise use the default or the value provided through | |
284 | * devicetree. | |
285 | */ | |
286 | if (dw_wdt_is_enabled(dw_wdt)) { | |
287 | wdd->timeout = dw_wdt_get_top(dw_wdt); | |
288 | set_bit(WDOG_HW_RUNNING, &wdd->status); | |
289 | } else { | |
290 | wdd->timeout = DW_WDT_DEFAULT_SECONDS; | |
291 | watchdog_init_timeout(wdd, 0, dev); | |
292 | } | |
293 | ||
294 | platform_set_drvdata(pdev, dw_wdt); | |
295 | ||
a70dcc01 GR |
296 | watchdog_set_restart_priority(wdd, 128); |
297 | ||
f29a72c2 | 298 | ret = watchdog_register_device(wdd); |
c9353ae1 JI |
299 | if (ret) |
300 | goto out_disable_clk; | |
301 | ||
c9353ae1 JI |
302 | return 0; |
303 | ||
304 | out_disable_clk: | |
f29a72c2 | 305 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
306 | return ret; |
307 | } | |
308 | ||
4b12b896 | 309 | static int dw_wdt_drv_remove(struct platform_device *pdev) |
c9353ae1 | 310 | { |
f29a72c2 | 311 | struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); |
c9353ae1 | 312 | |
f29a72c2 | 313 | watchdog_unregister_device(&dw_wdt->wdd); |
65a3b693 | 314 | reset_control_assert(dw_wdt->rst); |
f29a72c2 | 315 | clk_disable_unprepare(dw_wdt->clk); |
c9353ae1 JI |
316 | |
317 | return 0; | |
318 | } | |
319 | ||
58e56373 DN |
320 | #ifdef CONFIG_OF |
321 | static const struct of_device_id dw_wdt_of_match[] = { | |
322 | { .compatible = "snps,dw-wdt", }, | |
323 | { /* sentinel */ } | |
324 | }; | |
325 | MODULE_DEVICE_TABLE(of, dw_wdt_of_match); | |
326 | #endif | |
327 | ||
c9353ae1 JI |
328 | static struct platform_driver dw_wdt_driver = { |
329 | .probe = dw_wdt_drv_probe, | |
82268714 | 330 | .remove = dw_wdt_drv_remove, |
c9353ae1 JI |
331 | .driver = { |
332 | .name = "dw_wdt", | |
58e56373 | 333 | .of_match_table = of_match_ptr(dw_wdt_of_match), |
c9353ae1 | 334 | .pm = &dw_wdt_pm_ops, |
c9353ae1 JI |
335 | }, |
336 | }; | |
337 | ||
b8ec6118 | 338 | module_platform_driver(dw_wdt_driver); |
c9353ae1 JI |
339 | |
340 | MODULE_AUTHOR("Jamie Iles"); | |
341 | MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver"); | |
342 | MODULE_LICENSE("GPL"); |