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cc90ef0f 1/*
abda5c8b 2 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
cc90ef0f
DH
3 *
4 * (c) Copyright 2004 Google Inc.
96de0e25 5 * (c) Copyright 2005 David Härdeman <david@2gen.com>
cc90ef0f
DH
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
7944d3a5 12 * based on i810-tco.c which is in turn based on softdog.c
cc90ef0f 13 *
7944d3a5
WVS
14 * The timer is implemented in the following I/O controller hubs:
15 * (See the intel documentation on http://developer.intel.com.)
0426fd0d 16 * 6300ESB chip : document number 300641-004
cc90ef0f
DH
17 *
18 * 2004YYZZ Ross Biro
19 * Initial version 0.01
20 * 2004YYZZ Ross Biro
7944d3a5 21 * Version 0.02
96de0e25 22 * 20050210 David Härdeman <david@2gen.com>
7944d3a5 23 * Ported driver to kernel 2.6
cc90ef0f
DH
24 */
25
26/*
27 * Includes, defines, variables, module parameters, ...
28 */
29
27c766aa
JP
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
cc90ef0f
DH
32#include <linux/module.h>
33#include <linux/types.h>
34#include <linux/kernel.h>
35#include <linux/fs.h>
36#include <linux/mm.h>
37#include <linux/miscdevice.h>
38#include <linux/watchdog.h>
cc90ef0f
DH
39#include <linux/pci.h>
40#include <linux/ioport.h>
0829291e
AC
41#include <linux/uaccess.h>
42#include <linux/io.h>
cc90ef0f 43
cc90ef0f 44/* Module and version information */
2786095a 45#define ESB_VERSION "0.05"
cc90ef0f
DH
46#define ESB_MODULE_NAME "i6300ESB timer"
47#define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
cc90ef0f 48
abda5c8b
DH
49/* PCI configuration registers */
50#define ESB_CONFIG_REG 0x60 /* Config register */
51#define ESB_LOCK_REG 0x68 /* WDT lock register */
52
53/* Memory mapped registers */
bd4e6c18
WVS
54#define ESB_TIMER1_REG (BASEADDR + 0x00)/* Timer1 value after each reset */
55#define ESB_TIMER2_REG (BASEADDR + 0x04)/* Timer2 value after each reset */
56#define ESB_GINTSR_REG (BASEADDR + 0x08)/* General Interrupt Status Register */
57#define ESB_RELOAD_REG (BASEADDR + 0x0c)/* Reload register */
abda5c8b
DH
58
59/* Lock register bits */
0829291e
AC
60#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
61#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
62#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
abda5c8b
DH
63
64/* Config register bits */
0829291e
AC
65#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
66#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
39f3be72 67#define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
abda5c8b
DH
68
69/* Reload register bits */
31838d9d 70#define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
0829291e 71#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
abda5c8b
DH
72
73/* Magic constants */
74#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
75#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
76
cc90ef0f
DH
77/* internal variables */
78static void __iomem *BASEADDR;
c7dfd0cc 79static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */
cc90ef0f
DH
80static unsigned long timer_alive;
81static struct pci_dev *esb_pci;
82static unsigned short triggered; /* The status of the watchdog upon boot */
83static char esb_expect_close;
2786095a
WVS
84
85/* We can only use 1 card due to the /dev/watchdog restriction */
86static int cards_found;
0426fd0d 87
cc90ef0f 88/* module parameters */
0829291e
AC
89/* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
90#define WATCHDOG_HEARTBEAT 30
cc90ef0f
DH
91static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
92module_param(heartbeat, int, 0);
0829291e
AC
93MODULE_PARM_DESC(heartbeat,
94 "Watchdog heartbeat in seconds. (1<heartbeat<2046, default="
95 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
cc90ef0f 96
86a1e189
WVS
97static bool nowayout = WATCHDOG_NOWAYOUT;
98module_param(nowayout, bool, 0);
0829291e
AC
99MODULE_PARM_DESC(nowayout,
100 "Watchdog cannot be stopped once started (default="
101 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
cc90ef0f
DH
102
103/*
104 * Some i6300ESB specific functions
105 */
106
107/*
108 * Prepare for reloading the timer by unlocking the proper registers.
109 * This is performed by first writing 0x80 followed by 0x86 to the
110 * reload register. After this the appropriate registers can be written
111 * to once before they need to be unlocked again.
112 */
7944d3a5
WVS
113static inline void esb_unlock_registers(void)
114{
39f3be72
WVS
115 writew(ESB_UNLOCK1, ESB_RELOAD_REG);
116 writew(ESB_UNLOCK2, ESB_RELOAD_REG);
cc90ef0f
DH
117}
118
3b9d49ee 119static int esb_timer_start(void)
cc90ef0f
DH
120{
121 u8 val;
122
3b9d49ee
WVS
123 spin_lock(&esb_lock);
124 esb_unlock_registers();
125 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
cc90ef0f 126 /* Enable or Enable + Lock? */
fc8a9d83 127 val = ESB_WDT_ENABLE | (nowayout ? ESB_WDT_LOCK : 0x00);
0829291e 128 pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
3b9d49ee
WVS
129 spin_unlock(&esb_lock);
130 return 0;
cc90ef0f
DH
131}
132
133static int esb_timer_stop(void)
134{
135 u8 val;
136
137 spin_lock(&esb_lock);
138 /* First, reset timers as suggested by the docs */
139 esb_unlock_registers();
ce2f50b4 140 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
cc90ef0f
DH
141 /* Then disable the WDT */
142 pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
143 pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
144 spin_unlock(&esb_lock);
145
146 /* Returns 0 if the timer was disabled, non-zero otherwise */
fc8a9d83 147 return val & ESB_WDT_ENABLE;
cc90ef0f
DH
148}
149
150static void esb_timer_keepalive(void)
151{
152 spin_lock(&esb_lock);
153 esb_unlock_registers();
ce2f50b4 154 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
0829291e 155 /* FIXME: Do we need to flush anything here? */
cc90ef0f
DH
156 spin_unlock(&esb_lock);
157}
158
159static int esb_timer_set_heartbeat(int time)
160{
161 u32 val;
162
163 if (time < 0x1 || time > (2 * 0x03ff))
164 return -EINVAL;
165
166 spin_lock(&esb_lock);
167
168 /* We shift by 9, so if we are passed a value of 1 sec,
169 * val will be 1 << 9 = 512, then write that to two
170 * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
171 */
172 val = time << 9;
173
174 /* Write timer 1 */
175 esb_unlock_registers();
176 writel(val, ESB_TIMER1_REG);
177
178 /* Write timer 2 */
179 esb_unlock_registers();
7944d3a5 180 writel(val, ESB_TIMER2_REG);
cc90ef0f 181
0829291e 182 /* Reload */
cc90ef0f 183 esb_unlock_registers();
ce2f50b4 184 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
cc90ef0f
DH
185
186 /* FIXME: Do we need to flush everything out? */
187
188 /* Done */
189 heartbeat = time;
190 spin_unlock(&esb_lock);
191 return 0;
192}
193
cc90ef0f 194/*
7944d3a5 195 * /dev/watchdog handling
cc90ef0f
DH
196 */
197
0829291e 198static int esb_open(struct inode *inode, struct file *file)
cc90ef0f 199{
0829291e
AC
200 /* /dev/watchdog can only be opened once */
201 if (test_and_set_bit(0, &timer_alive))
202 return -EBUSY;
cc90ef0f 203
0829291e 204 /* Reload and activate timer */
0829291e 205 esb_timer_start();
cc90ef0f
DH
206
207 return nonseekable_open(inode, file);
208}
209
0829291e 210static int esb_release(struct inode *inode, struct file *file)
cc90ef0f 211{
0829291e
AC
212 /* Shut off the timer. */
213 if (esb_expect_close == 42)
214 esb_timer_stop();
215 else {
27c766aa 216 pr_crit("Unexpected close, not stopping watchdog!\n");
0829291e
AC
217 esb_timer_keepalive();
218 }
219 clear_bit(0, &timer_alive);
220 esb_expect_close = 0;
221 return 0;
cc90ef0f
DH
222}
223
0829291e
AC
224static ssize_t esb_write(struct file *file, const char __user *data,
225 size_t len, loff_t *ppos)
cc90ef0f
DH
226{
227 /* See if we got the magic character 'V' and reload the timer */
0829291e 228 if (len) {
cc90ef0f
DH
229 if (!nowayout) {
230 size_t i;
231
232 /* note: just in case someone wrote the magic character
233 * five months ago... */
234 esb_expect_close = 0;
235
143a2e54
WVS
236 /* scan to see whether or not we got the
237 * magic character */
cc90ef0f
DH
238 for (i = 0; i != len; i++) {
239 char c;
7944d3a5 240 if (get_user(c, data + i))
cc90ef0f
DH
241 return -EFAULT;
242 if (c == 'V')
243 esb_expect_close = 42;
244 }
245 }
246
247 /* someone wrote to us, we should reload the timer */
0829291e 248 esb_timer_keepalive();
cc90ef0f
DH
249 }
250 return len;
251}
252
0829291e 253static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
cc90ef0f
DH
254{
255 int new_options, retval = -EINVAL;
256 int new_heartbeat;
257 void __user *argp = (void __user *)arg;
258 int __user *p = argp;
42747d71 259 static const struct watchdog_info ident = {
7944d3a5 260 .options = WDIOF_SETTIMEOUT |
cc90ef0f
DH
261 WDIOF_KEEPALIVEPING |
262 WDIOF_MAGICCLOSE,
7944d3a5
WVS
263 .firmware_version = 0,
264 .identity = ESB_MODULE_NAME,
cc90ef0f
DH
265 };
266
267 switch (cmd) {
0829291e
AC
268 case WDIOC_GETSUPPORT:
269 return copy_to_user(argp, &ident,
270 sizeof(ident)) ? -EFAULT : 0;
cc90ef0f 271
0829291e 272 case WDIOC_GETSTATUS:
31838d9d 273 return put_user(0, p);
cc90ef0f 274
0829291e
AC
275 case WDIOC_GETBOOTSTATUS:
276 return put_user(triggered, p);
cc90ef0f 277
0829291e
AC
278 case WDIOC_SETOPTIONS:
279 {
280 if (get_user(new_options, p))
281 return -EFAULT;
cc90ef0f 282
0829291e
AC
283 if (new_options & WDIOS_DISABLECARD) {
284 esb_timer_stop();
285 retval = 0;
286 }
cc90ef0f 287
0829291e 288 if (new_options & WDIOS_ENABLECARD) {
0829291e
AC
289 esb_timer_start();
290 retval = 0;
291 }
292 return retval;
293 }
0c06090c
WVS
294 case WDIOC_KEEPALIVE:
295 esb_timer_keepalive();
296 return 0;
297
0829291e
AC
298 case WDIOC_SETTIMEOUT:
299 {
300 if (get_user(new_heartbeat, p))
301 return -EFAULT;
302 if (esb_timer_set_heartbeat(new_heartbeat))
303 return -EINVAL;
304 esb_timer_keepalive();
305 /* Fall */
306 }
307 case WDIOC_GETTIMEOUT:
308 return put_user(heartbeat, p);
309 default:
310 return -ENOTTY;
311 }
cc90ef0f
DH
312}
313
cc90ef0f
DH
314/*
315 * Kernel Interfaces
316 */
317
62322d25 318static const struct file_operations esb_fops = {
0829291e
AC
319 .owner = THIS_MODULE,
320 .llseek = no_llseek,
321 .write = esb_write,
322 .unlocked_ioctl = esb_ioctl,
323 .open = esb_open,
324 .release = esb_release,
cc90ef0f
DH
325};
326
327static struct miscdevice esb_miscdev = {
0829291e
AC
328 .minor = WATCHDOG_MINOR,
329 .name = "watchdog",
330 .fops = &esb_fops,
cc90ef0f
DH
331};
332
cc90ef0f
DH
333/*
334 * Data for PCI driver interface
cc90ef0f 335 */
bc17f9dc 336static const struct pci_device_id esb_pci_tbl[] = {
0829291e
AC
337 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
338 { 0, }, /* End of list */
cc90ef0f 339};
0829291e 340MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
cc90ef0f
DH
341
342/*
343 * Init & exit routines
344 */
345
2d991a16 346static unsigned char esb_getdevice(struct pci_dev *pdev)
cc90ef0f 347{
2786095a 348 if (pci_enable_device(pdev)) {
27c766aa 349 pr_err("failed to enable device\n");
fc8a9d83
WVS
350 goto err_devput;
351 }
cc90ef0f 352
2786095a 353 if (pci_request_region(pdev, 0, ESB_MODULE_NAME)) {
27c766aa 354 pr_err("failed to request region\n");
fc8a9d83
WVS
355 goto err_disable;
356 }
cc90ef0f 357
2786095a 358 BASEADDR = pci_ioremap_bar(pdev, 0);
fc8a9d83
WVS
359 if (BASEADDR == NULL) {
360 /* Something's wrong here, BASEADDR has to be set */
27c766aa 361 pr_err("failed to get BASEADDR\n");
fc8a9d83
WVS
362 goto err_release;
363 }
364
365 /* Done */
2786095a 366 esb_pci = pdev;
fc8a9d83 367 return 1;
cc90ef0f
DH
368
369err_release:
2786095a 370 pci_release_region(pdev, 0);
cc90ef0f 371err_disable:
2786095a 372 pci_disable_device(pdev);
811f9991 373err_devput:
cc90ef0f
DH
374 return 0;
375}
376
2d991a16 377static void esb_initdevice(void)
fc8a9d83
WVS
378{
379 u8 val1;
380 u16 val2;
381
382 /*
383 * Config register:
384 * Bit 5 : 0 = Enable WDT_OUTPUT
385 * Bit 2 : 0 = set the timer frequency to the PCI clock
386 * divided by 2^15 (approx 1KHz).
387 * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
388 * The watchdog has two timers, it can be setup so that the
389 * expiry of timer1 results in an interrupt and the expiry of
390 * timer2 results in a reboot. We set it to not generate
391 * any interrupts as there is not much we can do with it
392 * right now.
393 */
394 pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);
395
396 /* Check that the WDT isn't already locked */
397 pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
398 if (val1 & ESB_WDT_LOCK)
27c766aa 399 pr_warn("nowayout already set\n");
fc8a9d83
WVS
400
401 /* Set the timer to watchdog mode and disable it for now */
402 pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);
403
404 /* Check if the watchdog was previously triggered */
405 esb_unlock_registers();
406 val2 = readw(ESB_RELOAD_REG);
407 if (val2 & ESB_WDT_TIMEOUT)
408 triggered = WDIOF_CARDRESET;
409
410 /* Reset WDT_TIMEOUT flag and timers */
411 esb_unlock_registers();
412 writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG);
413
414 /* And set the correct timeout value */
415 esb_timer_set_heartbeat(heartbeat);
416}
417
2d991a16 418static int esb_probe(struct pci_dev *pdev,
2786095a 419 const struct pci_device_id *ent)
cc90ef0f 420{
0829291e
AC
421 int ret;
422
2786095a
WVS
423 cards_found++;
424 if (cards_found == 1)
27c766aa 425 pr_info("Intel 6300ESB WatchDog Timer Driver v%s\n",
2786095a
WVS
426 ESB_VERSION);
427
428 if (cards_found > 1) {
27c766aa 429 pr_err("This driver only supports 1 device\n");
2786095a
WVS
430 return -ENODEV;
431 }
432
0829291e 433 /* Check whether or not the hardware watchdog is there */
2786095a 434 if (!esb_getdevice(pdev) || esb_pci == NULL)
0829291e
AC
435 return -ENODEV;
436
437 /* Check that the heartbeat value is within it's range;
438 if not reset to the default */
fc8a9d83
WVS
439 if (heartbeat < 0x1 || heartbeat > 2 * 0x03ff) {
440 heartbeat = WATCHDOG_HEARTBEAT;
27c766aa
JP
441 pr_info("heartbeat value must be 1<heartbeat<2046, using %d\n",
442 heartbeat);
0829291e 443 }
cc90ef0f 444
fc8a9d83
WVS
445 /* Initialize the watchdog and make sure it does not run */
446 esb_initdevice();
447
448 /* Register the watchdog so that userspace has access to it */
0829291e
AC
449 ret = misc_register(&esb_miscdev);
450 if (ret != 0) {
27c766aa
JP
451 pr_err("cannot register miscdev on minor=%d (err=%d)\n",
452 WATCHDOG_MINOR, ret);
0426fd0d 453 goto err_unmap;
0829291e 454 }
27c766aa
JP
455 pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
456 BASEADDR, heartbeat, nowayout);
0829291e 457 return 0;
cc90ef0f 458
cc90ef0f
DH
459err_unmap:
460 iounmap(BASEADDR);
cc90ef0f 461 pci_release_region(esb_pci, 0);
cc90ef0f 462 pci_disable_device(esb_pci);
2786095a 463 esb_pci = NULL;
0829291e 464 return ret;
cc90ef0f
DH
465}
466
4b12b896 467static void esb_remove(struct pci_dev *pdev)
cc90ef0f
DH
468{
469 /* Stop the timer before we leave */
470 if (!nowayout)
0829291e 471 esb_timer_stop();
cc90ef0f
DH
472
473 /* Deregister */
474 misc_deregister(&esb_miscdev);
cc90ef0f
DH
475 iounmap(BASEADDR);
476 pci_release_region(esb_pci, 0);
477 pci_disable_device(esb_pci);
2786095a 478 esb_pci = NULL;
0426fd0d
WVS
479}
480
2786095a 481static void esb_shutdown(struct pci_dev *pdev)
0426fd0d
WVS
482{
483 esb_timer_stop();
484}
485
2786095a
WVS
486static struct pci_driver esb_driver = {
487 .name = ESB_MODULE_NAME,
488 .id_table = esb_pci_tbl,
0426fd0d 489 .probe = esb_probe,
82268714 490 .remove = esb_remove,
0426fd0d 491 .shutdown = esb_shutdown,
0426fd0d
WVS
492};
493
5ce9c371 494module_pci_driver(esb_driver);
cc90ef0f 495
96de0e25 496MODULE_AUTHOR("Ross Biro and David Härdeman");
cc90ef0f
DH
497MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
498MODULE_LICENSE("GPL");