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9e0ea345 1/*
cb711a19 2 * intel TCO Watchdog Driver
9e0ea345 3 *
deb9197b 4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
9e0ea345
WVS
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
cb711a19
WVS
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
d38bd479 29 * document number 322896-001, 322897-001: NM10
cb711a19
WVS
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
3c9d8ecc 33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
4946f835 34 * document number 320066-003, 320257-008: EP80597 (IICH)
203f8d89 35 * document number 324645-001, 324646-001: Cougar Point (CPT)
c54fb811 36 * document number TBD : Patsburg (PBG)
203f8d89 37 * document number TBD : DH89xxCC
aa1f4652 38 * document number TBD : Panther Point
84e83c28 39 * document number TBD : Lynx Point
7fb9c1a4 40 * document number TBD : Lynx Point-LP
9e0ea345
WVS
41 */
42
43/*
44 * Includes, defines, variables, module parameters, ...
45 */
46
27c766aa
JP
47#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
9e0ea345 49/* Module and version information */
7944d3a5 50#define DRV_NAME "iTCO_wdt"
24b3a167 51#define DRV_VERSION "1.11"
9e0ea345
WVS
52
53/* Includes */
f321c9cb 54#include <linux/acpi.h> /* For ACPI support */
3836cc0f
WVS
55#include <linux/module.h> /* For module specific items */
56#include <linux/moduleparam.h> /* For new moduleparam's */
57#include <linux/types.h> /* For standard types (like size_t) */
58#include <linux/errno.h> /* For the -ENODEV/... values */
59#include <linux/kernel.h> /* For printk/panic/... */
3836cc0f 60#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f
WVS
61#include <linux/init.h> /* For __init/__exit/... */
62#include <linux/fs.h> /* For file operations */
63#include <linux/platform_device.h> /* For platform_driver framework */
64#include <linux/pci.h> /* For pci functions */
65#include <linux/ioport.h> /* For io-port access */
66#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
0e6fa3fb
AC
67#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
68#include <linux/io.h> /* For inb/outb/... */
420b54de 69#include <linux/platform_data/itco_wdt.h>
3836cc0f 70
0e6fa3fb 71#include "iTCO_vendor.h"
9e0ea345 72
9e0ea345 73/* Address definitions for the TCO */
0e6fa3fb 74/* TCO base address */
ce1b95ca 75#define TCOBASE(p) ((p)->tco_res->start)
0e6fa3fb 76/* SMI Control and Enable Register */
ce1b95ca
GR
77#define SMI_EN(p) ((p)->smi_res->start)
78
79#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
80#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
81#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
82#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
83#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
84#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
85#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
86#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
87#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
9e0ea345
WVS
88
89/* internal variables */
ce1b95ca
GR
90struct iTCO_wdt_private {
91 struct watchdog_device wddev;
92
0e6fa3fb
AC
93 /* TCO version/generation */
94 unsigned int iTCO_version;
887c8ec7
AS
95 struct resource *tco_res;
96 struct resource *smi_res;
24b3a167
PT
97 /*
98 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
99 * or memory-mapped PMC register bit 4 (TCO version 3).
100 */
101 struct resource *gcs_pmc_res;
102 unsigned long __iomem *gcs_pmc;
0e6fa3fb
AC
103 /* the lock for io operations */
104 spinlock_t io_lock;
105 /* the PCI-device */
78e45696 106 struct pci_dev *pci_dev;
f321c9cb
RW
107 /* whether or not the watchdog has been suspended */
108 bool suspended;
140c91b2
KS
109 /* no reboot API private data */
110 void *no_reboot_priv;
f583a884
KS
111 /* no reboot update function pointer */
112 int (*update_no_reboot_bit)(void *p, bool set);
ce1b95ca 113};
9e0ea345
WVS
114
115/* module parameters */
bff23431
WVS
116#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
117static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
9e0ea345 118module_param(heartbeat, int, 0);
7e6811da
PB
119MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
120 "5..76 (TCO v1) or 3..614 (TCO v2), default="
bff23431 121 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
9e0ea345 122
86a1e189
WVS
123static bool nowayout = WATCHDOG_NOWAYOUT;
124module_param(nowayout, bool, 0);
0e6fa3fb
AC
125MODULE_PARM_DESC(nowayout,
126 "Watchdog cannot be stopped once started (default="
127 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
e033351d 128
0d098587 129static int turn_SMI_watchdog_clear_off = 1;
deb9197b
WVS
130module_param(turn_SMI_watchdog_clear_off, int, 0);
131MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
0d098587 132 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
deb9197b 133
9e0ea345
WVS
134/*
135 * Some TCO specific functions
136 */
137
24b3a167
PT
138/*
139 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
140 * every 0.6 seconds. v3's internal timer is stored as seconds (some
141 * datasheets incorrectly state 0.6 seconds).
142 */
ce1b95ca
GR
143static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
144 int secs)
9e0ea345 145{
ce1b95ca 146 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
24b3a167
PT
147}
148
ce1b95ca
GR
149static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
150 int ticks)
24b3a167 151{
ce1b95ca 152 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
9e0ea345
WVS
153}
154
ce1b95ca 155static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
2a7a0e9b
MF
156{
157 u32 enable_bit;
158
ce1b95ca 159 switch (p->iTCO_version) {
3b3a1c8f 160 case 5:
2a7a0e9b
MF
161 case 3:
162 enable_bit = 0x00000010;
163 break;
164 case 2:
165 enable_bit = 0x00000020;
166 break;
167 case 4:
168 case 1:
169 default:
170 enable_bit = 0x00000002;
171 break;
172 }
173
174 return enable_bit;
175}
176
f583a884 177static int update_no_reboot_bit_def(void *priv, bool set)
9e0ea345 178{
f583a884 179 return 0;
9e0ea345
WVS
180}
181
f583a884 182static int update_no_reboot_bit_pci(void *priv, bool set)
9e0ea345 183{
f583a884
KS
184 struct iTCO_wdt_private *p = priv;
185 u32 val32 = 0, newval32 = 0;
9e0ea345 186
f583a884
KS
187 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
188 if (set)
189 val32 |= no_reboot_bit(p);
190 else
191 val32 &= ~no_reboot_bit(p);
192 pci_write_config_dword(p->pci_dev, 0xd4, val32);
193 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
9e0ea345 194
f583a884
KS
195 /* make sure the update is successful */
196 if (val32 != newval32)
197 return -EIO;
9e0ea345 198
f583a884
KS
199 return 0;
200}
201
202static int update_no_reboot_bit_mem(void *priv, bool set)
203{
204 struct iTCO_wdt_private *p = priv;
205 u32 val32 = 0, newval32 = 0;
206
207 val32 = readl(p->gcs_pmc);
208 if (set)
209 val32 |= no_reboot_bit(p);
210 else
211 val32 &= ~no_reboot_bit(p);
212 writel(val32, p->gcs_pmc);
213 newval32 = readl(p->gcs_pmc);
9e0ea345 214
f583a884
KS
215 /* make sure the update is successful */
216 if (val32 != newval32)
2a7a0e9b
MF
217 return -EIO;
218
219 return 0;
9e0ea345
WVS
220}
221
140c91b2
KS
222static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
223 struct itco_wdt_platform_data *pdata)
f583a884 224{
140c91b2
KS
225 if (pdata->update_no_reboot_bit) {
226 p->update_no_reboot_bit = pdata->update_no_reboot_bit;
227 p->no_reboot_priv = pdata->no_reboot_priv;
228 return;
229 }
230
f583a884
KS
231 if (p->iTCO_version >= 2)
232 p->update_no_reboot_bit = update_no_reboot_bit_mem;
233 else if (p->iTCO_version == 1)
234 p->update_no_reboot_bit = update_no_reboot_bit_pci;
235 else
236 p->update_no_reboot_bit = update_no_reboot_bit_def;
140c91b2
KS
237
238 p->no_reboot_priv = p;
f583a884
KS
239}
240
bff23431 241static int iTCO_wdt_start(struct watchdog_device *wd_dev)
9e0ea345 242{
ce1b95ca 243 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
9e0ea345
WVS
244 unsigned int val;
245
ce1b95ca 246 spin_lock(&p->io_lock);
9e0ea345 247
ce1b95ca 248 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
e033351d 249
9e0ea345 250 /* disable chipset's NO_REBOOT bit */
140c91b2 251 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
ce1b95ca 252 spin_unlock(&p->io_lock);
27c766aa 253 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
9e0ea345
WVS
254 return -EIO;
255 }
256
7cd5b08b
WVS
257 /* Force the timer to its reload value by writing to the TCO_RLD
258 register */
ce1b95ca
GR
259 if (p->iTCO_version >= 2)
260 outw(0x01, TCO_RLD(p));
261 else if (p->iTCO_version == 1)
262 outb(0x01, TCO_RLD(p));
7cd5b08b 263
9e0ea345 264 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
ce1b95ca 265 val = inw(TCO1_CNT(p));
9e0ea345 266 val &= 0xf7ff;
ce1b95ca
GR
267 outw(val, TCO1_CNT(p));
268 val = inw(TCO1_CNT(p));
269 spin_unlock(&p->io_lock);
9e0ea345
WVS
270
271 if (val & 0x0800)
272 return -1;
273 return 0;
274}
275
bff23431 276static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
9e0ea345 277{
ce1b95ca 278 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
9e0ea345
WVS
279 unsigned int val;
280
ce1b95ca 281 spin_lock(&p->io_lock);
9e0ea345 282
ce1b95ca 283 iTCO_vendor_pre_stop(p->smi_res);
e033351d 284
9e0ea345 285 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
ce1b95ca 286 val = inw(TCO1_CNT(p));
9e0ea345 287 val |= 0x0800;
ce1b95ca
GR
288 outw(val, TCO1_CNT(p));
289 val = inw(TCO1_CNT(p));
9e0ea345
WVS
290
291 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
140c91b2 292 p->update_no_reboot_bit(p->no_reboot_priv, true);
9e0ea345 293
ce1b95ca 294 spin_unlock(&p->io_lock);
9e0ea345
WVS
295
296 if ((val & 0x0800) == 0)
297 return -1;
298 return 0;
299}
300
bff23431 301static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
9e0ea345 302{
ce1b95ca 303 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
9e0ea345 304
ce1b95ca
GR
305 spin_lock(&p->io_lock);
306
307 iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
e033351d 308
9e0ea345 309 /* Reload the timer by writing to the TCO Timer Counter register */
fc61e83a 310 if (p->iTCO_version >= 2) {
ce1b95ca 311 outw(0x01, TCO_RLD(p));
fc61e83a
WVS
312 } else if (p->iTCO_version == 1) {
313 /* Reset the timeout status bit so that the timer
314 * needs to count down twice again before rebooting */
315 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
316
ce1b95ca 317 outb(0x01, TCO_RLD(p));
fc61e83a 318 }
9e0ea345 319
ce1b95ca 320 spin_unlock(&p->io_lock);
9e0ea345
WVS
321 return 0;
322}
323
bff23431 324static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
9e0ea345 325{
ce1b95ca 326 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
9e0ea345
WVS
327 unsigned int val16;
328 unsigned char val8;
329 unsigned int tmrval;
330
fc61e83a
WVS
331 tmrval = seconds_to_ticks(p, t);
332
333 /* For TCO v1 the timer counts down twice before rebooting */
334 if (p->iTCO_version == 1)
335 tmrval /= 2;
7e6811da 336
9e0ea345
WVS
337 /* from the specs: */
338 /* "Values of 0h-3h are ignored and should not be attempted" */
339 if (tmrval < 0x04)
340 return -EINVAL;
ce1b95ca
GR
341 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
342 (p->iTCO_version == 1 && tmrval > 0x03f))
9e0ea345
WVS
343 return -EINVAL;
344
e033351d
WVS
345 iTCO_vendor_pre_set_heartbeat(tmrval);
346
9e0ea345 347 /* Write new heartbeat to watchdog */
ce1b95ca
GR
348 if (p->iTCO_version >= 2) {
349 spin_lock(&p->io_lock);
350 val16 = inw(TCOv2_TMR(p));
9e0ea345
WVS
351 val16 &= 0xfc00;
352 val16 |= tmrval;
ce1b95ca
GR
353 outw(val16, TCOv2_TMR(p));
354 val16 = inw(TCOv2_TMR(p));
355 spin_unlock(&p->io_lock);
9e0ea345
WVS
356
357 if ((val16 & 0x3ff) != tmrval)
358 return -EINVAL;
ce1b95ca
GR
359 } else if (p->iTCO_version == 1) {
360 spin_lock(&p->io_lock);
361 val8 = inb(TCOv1_TMR(p));
9e0ea345
WVS
362 val8 &= 0xc0;
363 val8 |= (tmrval & 0xff);
ce1b95ca
GR
364 outb(val8, TCOv1_TMR(p));
365 val8 = inb(TCOv1_TMR(p));
366 spin_unlock(&p->io_lock);
9e0ea345
WVS
367
368 if ((val8 & 0x3f) != tmrval)
369 return -EINVAL;
370 }
371
bff23431 372 wd_dev->timeout = t;
9e0ea345
WVS
373 return 0;
374}
375
bff23431 376static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
9e0ea345 377{
ce1b95ca 378 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
9e0ea345
WVS
379 unsigned int val16;
380 unsigned char val8;
bff23431 381 unsigned int time_left = 0;
9e0ea345
WVS
382
383 /* read the TCO Timer */
ce1b95ca
GR
384 if (p->iTCO_version >= 2) {
385 spin_lock(&p->io_lock);
386 val16 = inw(TCO_RLD(p));
9e0ea345 387 val16 &= 0x3ff;
ce1b95ca 388 spin_unlock(&p->io_lock);
9e0ea345 389
ce1b95ca
GR
390 time_left = ticks_to_seconds(p, val16);
391 } else if (p->iTCO_version == 1) {
392 spin_lock(&p->io_lock);
393 val8 = inb(TCO_RLD(p));
9e0ea345 394 val8 &= 0x3f;
ce1b95ca
GR
395 if (!(inw(TCO1_STS(p)) & 0x0008))
396 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
397 spin_unlock(&p->io_lock);
9e0ea345 398
ce1b95ca 399 time_left = ticks_to_seconds(p, val8);
9e0ea345 400 }
bff23431 401 return time_left;
9e0ea345
WVS
402}
403
9e0ea345
WVS
404/*
405 * Kernel Interfaces
406 */
407
bff23431
WVS
408static const struct watchdog_info ident = {
409 .options = WDIOF_SETTIMEOUT |
410 WDIOF_KEEPALIVEPING |
411 WDIOF_MAGICCLOSE,
412 .firmware_version = 0,
413 .identity = DRV_NAME,
414};
415
416static const struct watchdog_ops iTCO_wdt_ops = {
0e6fa3fb 417 .owner = THIS_MODULE,
bff23431 418 .start = iTCO_wdt_start,
5f5e1909
JH
419 .stop = iTCO_wdt_stop,
420 .ping = iTCO_wdt_ping,
bff23431
WVS
421 .set_timeout = iTCO_wdt_set_timeout,
422 .get_timeleft = iTCO_wdt_get_timeleft,
9e0ea345
WVS
423};
424
9e0ea345
WVS
425/*
426 * Init & exit routines
427 */
428
78e45696 429static int iTCO_wdt_probe(struct platform_device *pdev)
9e0ea345 430{
78e45696
GR
431 struct device *dev = &pdev->dev;
432 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
ce1b95ca
GR
433 struct iTCO_wdt_private *p;
434 unsigned long val32;
435 int ret;
887c8ec7 436
420b54de 437 if (!pdata)
ce1b95ca 438 return -ENODEV;
887c8ec7 439
78e45696 440 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
ce1b95ca
GR
441 if (!p)
442 return -ENOMEM;
887c8ec7 443
ce1b95ca 444 spin_lock_init(&p->io_lock);
887c8ec7 445
78e45696 446 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
ce1b95ca
GR
447 if (!p->tco_res)
448 return -ENODEV;
887c8ec7 449
78e45696 450 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
ce1b95ca
GR
451 if (!p->smi_res)
452 return -ENODEV;
453
454 p->iTCO_version = pdata->version;
78e45696 455 p->pci_dev = to_pci_dev(dev->parent);
9e0ea345 456
140c91b2 457 iTCO_wdt_no_reboot_bit_setup(p, pdata);
f583a884 458
9e0ea345 459 /*
24b3a167
PT
460 * Get the Memory-Mapped GCS or PMC register, we need it for the
461 * NO_REBOOT flag (TCO v2 and v3).
9e0ea345 462 */
140c91b2 463 if (p->iTCO_version >= 2 && !pdata->update_no_reboot_bit) {
78e45696 464 p->gcs_pmc_res = platform_get_resource(pdev,
ce1b95ca
GR
465 IORESOURCE_MEM,
466 ICH_RES_MEM_GCS_PMC);
78e45696 467 p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
c7bbcc87
GR
468 if (IS_ERR(p->gcs_pmc))
469 return PTR_ERR(p->gcs_pmc);
9e0ea345
WVS
470 }
471
472 /* Check chipset's NO_REBOOT bit */
140c91b2 473 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
ce1b95ca 474 iTCO_vendor_check_noreboot_on()) {
27c766aa 475 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
c7bbcc87 476 return -ENODEV; /* Cannot reset NO_REBOOT bit */
9e0ea345
WVS
477 }
478
479 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
140c91b2 480 p->update_no_reboot_bit(p->no_reboot_priv, true);
9e0ea345 481
7cd5b08b 482 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
78e45696 483 if (!devm_request_region(dev, p->smi_res->start,
c7bbcc87 484 resource_size(p->smi_res),
78e45696 485 pdev->name)) {
887c8ec7 486 pr_err("I/O address 0x%04llx already in use, device disabled\n",
ce1b95ca 487 (u64)SMI_EN(p));
c7bbcc87 488 return -EBUSY;
9e0ea345 489 }
ce1b95ca 490 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
887c8ec7
AS
491 /*
492 * Bit 13: TCO_EN -> 0
493 * Disables TCO logic generating an SMI#
494 */
ce1b95ca 495 val32 = inl(SMI_EN(p));
deb9197b 496 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
ce1b95ca 497 outl(val32, SMI_EN(p));
deb9197b 498 }
9e0ea345 499
78e45696 500 if (!devm_request_region(dev, p->tco_res->start,
c7bbcc87 501 resource_size(p->tco_res),
78e45696 502 pdev->name)) {
887c8ec7 503 pr_err("I/O address 0x%04llx already in use, device disabled\n",
ce1b95ca 504 (u64)TCOBASE(p));
c7bbcc87 505 return -EBUSY;
9e0ea345
WVS
506 }
507
887c8ec7 508 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
ce1b95ca 509 pdata->name, pdata->version, (u64)TCOBASE(p));
9e0ea345
WVS
510
511 /* Clear out the (probably old) status */
ce1b95ca 512 switch (p->iTCO_version) {
3b3a1c8f 513 case 5:
2a7a0e9b 514 case 4:
ce1b95ca
GR
515 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
516 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
2a7a0e9b
MF
517 break;
518 case 3:
ce1b95ca 519 outl(0x20008, TCO1_STS(p));
2a7a0e9b
MF
520 break;
521 case 2:
522 case 1:
523 default:
ce1b95ca
GR
524 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
525 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
526 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
2a7a0e9b 527 break;
24b3a167 528 }
9e0ea345 529
ce1b95ca
GR
530 p->wddev.info = &ident,
531 p->wddev.ops = &iTCO_wdt_ops,
532 p->wddev.bootstatus = 0;
533 p->wddev.timeout = WATCHDOG_TIMEOUT;
534 watchdog_set_nowayout(&p->wddev, nowayout);
78e45696 535 p->wddev.parent = dev;
ce1b95ca
GR
536
537 watchdog_set_drvdata(&p->wddev, p);
78e45696 538 platform_set_drvdata(pdev, p);
bff23431 539
9e0ea345 540 /* Make sure the watchdog is not running */
ce1b95ca 541 iTCO_wdt_stop(&p->wddev);
9e0ea345 542
0e6fa3fb
AC
543 /* Check that the heartbeat value is within it's range;
544 if not reset to the default */
ce1b95ca
GR
545 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
546 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
bff23431
WVS
547 pr_info("timeout value out of range, using %d\n",
548 WATCHDOG_TIMEOUT);
9e0ea345
WVS
549 }
550
d3d77b5a 551 watchdog_stop_on_reboot(&p->wddev);
78e45696 552 ret = devm_watchdog_register_device(dev, &p->wddev);
9e0ea345 553 if (ret != 0) {
bff23431 554 pr_err("cannot register watchdog device (err=%d)\n", ret);
c7bbcc87 555 return ret;
9e0ea345
WVS
556 }
557
27c766aa
JP
558 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
559 heartbeat, nowayout);
9e0ea345
WVS
560
561 return 0;
9e0ea345
WVS
562}
563
78e45696 564static int iTCO_wdt_remove(struct platform_device *pdev)
9e0ea345 565{
78e45696 566 struct iTCO_wdt_private *p = platform_get_drvdata(pdev);
ce1b95ca 567
c7bbcc87
GR
568 /* Stop the timer before we leave */
569 if (!nowayout)
570 iTCO_wdt_stop(&p->wddev);
9e0ea345 571
3836cc0f
WVS
572 return 0;
573}
574
f321c9cb
RW
575#ifdef CONFIG_PM_SLEEP
576/*
577 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
578 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
579 * watchdog is stopped by the platform firmware.
580 */
581
582#ifdef CONFIG_ACPI
583static inline bool need_suspend(void)
584{
585 return acpi_target_system_state() == ACPI_STATE_S0;
586}
587#else
588static inline bool need_suspend(void) { return true; }
589#endif
590
591static int iTCO_wdt_suspend_noirq(struct device *dev)
592{
ce1b95ca 593 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
f321c9cb
RW
594 int ret = 0;
595
ce1b95ca
GR
596 p->suspended = false;
597 if (watchdog_active(&p->wddev) && need_suspend()) {
598 ret = iTCO_wdt_stop(&p->wddev);
f321c9cb 599 if (!ret)
ce1b95ca 600 p->suspended = true;
f321c9cb
RW
601 }
602 return ret;
603}
604
605static int iTCO_wdt_resume_noirq(struct device *dev)
606{
ce1b95ca
GR
607 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
608
609 if (p->suspended)
610 iTCO_wdt_start(&p->wddev);
f321c9cb
RW
611
612 return 0;
613}
614
6e938f6e 615static const struct dev_pm_ops iTCO_wdt_pm = {
f321c9cb
RW
616 .suspend_noirq = iTCO_wdt_suspend_noirq,
617 .resume_noirq = iTCO_wdt_resume_noirq,
618};
619
620#define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
621#else
622#define ITCO_WDT_PM_OPS NULL
623#endif /* CONFIG_PM_SLEEP */
624
3836cc0f
WVS
625static struct platform_driver iTCO_wdt_driver = {
626 .probe = iTCO_wdt_probe,
82268714 627 .remove = iTCO_wdt_remove,
3836cc0f 628 .driver = {
3836cc0f 629 .name = DRV_NAME,
f321c9cb 630 .pm = ITCO_WDT_PM_OPS,
3836cc0f
WVS
631 },
632};
633
634static int __init iTCO_wdt_init_module(void)
635{
27c766aa 636 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
3836cc0f 637
9616bd2a 638 return platform_driver_register(&iTCO_wdt_driver);
3836cc0f
WVS
639}
640
641static void __exit iTCO_wdt_cleanup_module(void)
642{
3836cc0f 643 platform_driver_unregister(&iTCO_wdt_driver);
27c766aa 644 pr_info("Watchdog Module Unloaded\n");
9e0ea345
WVS
645}
646
647module_init(iTCO_wdt_init_module);
648module_exit(iTCO_wdt_cleanup_module);
649
650MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
651MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f 652MODULE_VERSION(DRV_VERSION);
9e0ea345 653MODULE_LICENSE("GPL");
e5de32e3 654MODULE_ALIAS("platform:" DRV_NAME);