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Commit | Line | Data |
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9e0ea345 | 1 | /* |
cb711a19 | 2 | * intel TCO Watchdog Driver |
9e0ea345 | 3 | * |
deb9197b | 4 | * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. |
9e0ea345 WVS |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor | |
12 | * provide warranty for any of this software. This material is | |
13 | * provided "AS-IS" and at no charge. | |
14 | * | |
15 | * The TCO watchdog is implemented in the following I/O controller hubs: | |
16 | * (See the intel documentation on http://developer.intel.com.) | |
cb711a19 WVS |
17 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
18 | * document number 290687-002, 298242-027: 82801BA (ICH2) | |
19 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) | |
20 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) | |
21 | * document number 290744-001, 290745-025: 82801DB (ICH4) | |
22 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) | |
23 | * document number 273599-001, 273645-002: 82801E (C-ICH) | |
24 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) | |
25 | * document number 300641-004, 300884-013: 6300ESB | |
26 | * document number 301473-002, 301474-026: 82801F (ICH6) | |
27 | * document number 313082-001, 313075-006: 631xESB, 632xESB | |
28 | * document number 307013-003, 307014-024: 82801G (ICH7) | |
d38bd479 | 29 | * document number 322896-001, 322897-001: NM10 |
cb711a19 WVS |
30 | * document number 313056-003, 313057-017: 82801H (ICH8) |
31 | * document number 316972-004, 316973-012: 82801I (ICH9) | |
32 | * document number 319973-002, 319974-002: 82801J (ICH10) | |
3c9d8ecc | 33 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
4946f835 | 34 | * document number 320066-003, 320257-008: EP80597 (IICH) |
203f8d89 | 35 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
c54fb811 | 36 | * document number TBD : Patsburg (PBG) |
203f8d89 | 37 | * document number TBD : DH89xxCC |
aa1f4652 | 38 | * document number TBD : Panther Point |
84e83c28 | 39 | * document number TBD : Lynx Point |
7fb9c1a4 | 40 | * document number TBD : Lynx Point-LP |
9e0ea345 WVS |
41 | */ |
42 | ||
43 | /* | |
44 | * Includes, defines, variables, module parameters, ... | |
45 | */ | |
46 | ||
27c766aa JP |
47 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
48 | ||
9e0ea345 | 49 | /* Module and version information */ |
7944d3a5 | 50 | #define DRV_NAME "iTCO_wdt" |
24b3a167 | 51 | #define DRV_VERSION "1.11" |
9e0ea345 WVS |
52 | |
53 | /* Includes */ | |
f321c9cb | 54 | #include <linux/acpi.h> /* For ACPI support */ |
3836cc0f WVS |
55 | #include <linux/module.h> /* For module specific items */ |
56 | #include <linux/moduleparam.h> /* For new moduleparam's */ | |
57 | #include <linux/types.h> /* For standard types (like size_t) */ | |
58 | #include <linux/errno.h> /* For the -ENODEV/... values */ | |
59 | #include <linux/kernel.h> /* For printk/panic/... */ | |
3836cc0f | 60 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
3836cc0f WVS |
61 | #include <linux/init.h> /* For __init/__exit/... */ |
62 | #include <linux/fs.h> /* For file operations */ | |
63 | #include <linux/platform_device.h> /* For platform_driver framework */ | |
64 | #include <linux/pci.h> /* For pci functions */ | |
65 | #include <linux/ioport.h> /* For io-port access */ | |
66 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | |
0e6fa3fb AC |
67 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
68 | #include <linux/io.h> /* For inb/outb/... */ | |
420b54de | 69 | #include <linux/platform_data/itco_wdt.h> |
3836cc0f | 70 | |
0e6fa3fb | 71 | #include "iTCO_vendor.h" |
9e0ea345 | 72 | |
9e0ea345 | 73 | /* Address definitions for the TCO */ |
0e6fa3fb | 74 | /* TCO base address */ |
887c8ec7 | 75 | #define TCOBASE (iTCO_wdt_private.tco_res->start) |
0e6fa3fb | 76 | /* SMI Control and Enable Register */ |
887c8ec7 | 77 | #define SMI_EN (iTCO_wdt_private.smi_res->start) |
9e0ea345 | 78 | |
0a7e6582 WVS |
79 | #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ |
80 | #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ | |
81 | #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ | |
82 | #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ | |
83 | #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ | |
84 | #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ | |
85 | #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ | |
86 | #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ | |
87 | #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ | |
9e0ea345 WVS |
88 | |
89 | /* internal variables */ | |
0e6fa3fb AC |
90 | static struct { /* this is private data for the iTCO_wdt device */ |
91 | /* TCO version/generation */ | |
92 | unsigned int iTCO_version; | |
887c8ec7 AS |
93 | struct resource *tco_res; |
94 | struct resource *smi_res; | |
24b3a167 PT |
95 | /* |
96 | * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), | |
97 | * or memory-mapped PMC register bit 4 (TCO version 3). | |
98 | */ | |
99 | struct resource *gcs_pmc_res; | |
100 | unsigned long __iomem *gcs_pmc; | |
0e6fa3fb AC |
101 | /* the lock for io operations */ |
102 | spinlock_t io_lock; | |
887c8ec7 | 103 | struct platform_device *dev; |
0e6fa3fb AC |
104 | /* the PCI-device */ |
105 | struct pci_dev *pdev; | |
f321c9cb RW |
106 | /* whether or not the watchdog has been suspended */ |
107 | bool suspended; | |
9e0ea345 WVS |
108 | } iTCO_wdt_private; |
109 | ||
110 | /* module parameters */ | |
bff23431 WVS |
111 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ |
112 | static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ | |
9e0ea345 | 113 | module_param(heartbeat, int, 0); |
7e6811da PB |
114 | MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " |
115 | "5..76 (TCO v1) or 3..614 (TCO v2), default=" | |
bff23431 | 116 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); |
9e0ea345 | 117 | |
86a1e189 WVS |
118 | static bool nowayout = WATCHDOG_NOWAYOUT; |
119 | module_param(nowayout, bool, 0); | |
0e6fa3fb AC |
120 | MODULE_PARM_DESC(nowayout, |
121 | "Watchdog cannot be stopped once started (default=" | |
122 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
e033351d | 123 | |
0d098587 | 124 | static int turn_SMI_watchdog_clear_off = 1; |
deb9197b WVS |
125 | module_param(turn_SMI_watchdog_clear_off, int, 0); |
126 | MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, | |
0d098587 | 127 | "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); |
deb9197b | 128 | |
9e0ea345 WVS |
129 | /* |
130 | * Some TCO specific functions | |
131 | */ | |
132 | ||
24b3a167 PT |
133 | /* |
134 | * The iTCO v1 and v2's internal timer is stored as ticks which decrement | |
135 | * every 0.6 seconds. v3's internal timer is stored as seconds (some | |
136 | * datasheets incorrectly state 0.6 seconds). | |
137 | */ | |
138 | static inline unsigned int seconds_to_ticks(int secs) | |
9e0ea345 | 139 | { |
24b3a167 PT |
140 | return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6; |
141 | } | |
142 | ||
143 | static inline unsigned int ticks_to_seconds(int ticks) | |
144 | { | |
145 | return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10; | |
9e0ea345 WVS |
146 | } |
147 | ||
2a7a0e9b MF |
148 | static inline u32 no_reboot_bit(void) |
149 | { | |
150 | u32 enable_bit; | |
151 | ||
152 | switch (iTCO_wdt_private.iTCO_version) { | |
3b3a1c8f | 153 | case 5: |
2a7a0e9b MF |
154 | case 3: |
155 | enable_bit = 0x00000010; | |
156 | break; | |
157 | case 2: | |
158 | enable_bit = 0x00000020; | |
159 | break; | |
160 | case 4: | |
161 | case 1: | |
162 | default: | |
163 | enable_bit = 0x00000002; | |
164 | break; | |
165 | } | |
166 | ||
167 | return enable_bit; | |
168 | } | |
169 | ||
9e0ea345 WVS |
170 | static void iTCO_wdt_set_NO_REBOOT_bit(void) |
171 | { | |
172 | u32 val32; | |
173 | ||
174 | /* Set the NO_REBOOT bit: this disables reboots */ | |
2a7a0e9b | 175 | if (iTCO_wdt_private.iTCO_version >= 2) { |
24b3a167 | 176 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
2a7a0e9b | 177 | val32 |= no_reboot_bit(); |
24b3a167 | 178 | writel(val32, iTCO_wdt_private.gcs_pmc); |
9e0ea345 WVS |
179 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
180 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
2a7a0e9b | 181 | val32 |= no_reboot_bit(); |
9e0ea345 WVS |
182 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); |
183 | } | |
184 | } | |
185 | ||
186 | static int iTCO_wdt_unset_NO_REBOOT_bit(void) | |
187 | { | |
2a7a0e9b MF |
188 | u32 enable_bit = no_reboot_bit(); |
189 | u32 val32 = 0; | |
9e0ea345 WVS |
190 | |
191 | /* Unset the NO_REBOOT bit: this enables reboots */ | |
2a7a0e9b | 192 | if (iTCO_wdt_private.iTCO_version >= 2) { |
24b3a167 | 193 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
2a7a0e9b | 194 | val32 &= ~enable_bit; |
24b3a167 | 195 | writel(val32, iTCO_wdt_private.gcs_pmc); |
9e0ea345 | 196 | |
24b3a167 | 197 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
9e0ea345 WVS |
198 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
199 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
2a7a0e9b | 200 | val32 &= ~enable_bit; |
9e0ea345 WVS |
201 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); |
202 | ||
203 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
9e0ea345 WVS |
204 | } |
205 | ||
2a7a0e9b MF |
206 | if (val32 & enable_bit) |
207 | return -EIO; | |
208 | ||
209 | return 0; | |
9e0ea345 WVS |
210 | } |
211 | ||
bff23431 | 212 | static int iTCO_wdt_start(struct watchdog_device *wd_dev) |
9e0ea345 WVS |
213 | { |
214 | unsigned int val; | |
215 | ||
216 | spin_lock(&iTCO_wdt_private.io_lock); | |
217 | ||
bff23431 | 218 | iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout); |
e033351d | 219 | |
9e0ea345 WVS |
220 | /* disable chipset's NO_REBOOT bit */ |
221 | if (iTCO_wdt_unset_NO_REBOOT_bit()) { | |
2ba7d7b3 | 222 | spin_unlock(&iTCO_wdt_private.io_lock); |
27c766aa | 223 | pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); |
9e0ea345 WVS |
224 | return -EIO; |
225 | } | |
226 | ||
7cd5b08b WVS |
227 | /* Force the timer to its reload value by writing to the TCO_RLD |
228 | register */ | |
24b3a167 | 229 | if (iTCO_wdt_private.iTCO_version >= 2) |
7cd5b08b WVS |
230 | outw(0x01, TCO_RLD); |
231 | else if (iTCO_wdt_private.iTCO_version == 1) | |
232 | outb(0x01, TCO_RLD); | |
233 | ||
9e0ea345 WVS |
234 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
235 | val = inw(TCO1_CNT); | |
236 | val &= 0xf7ff; | |
237 | outw(val, TCO1_CNT); | |
238 | val = inw(TCO1_CNT); | |
239 | spin_unlock(&iTCO_wdt_private.io_lock); | |
240 | ||
241 | if (val & 0x0800) | |
242 | return -1; | |
243 | return 0; | |
244 | } | |
245 | ||
bff23431 | 246 | static int iTCO_wdt_stop(struct watchdog_device *wd_dev) |
9e0ea345 WVS |
247 | { |
248 | unsigned int val; | |
249 | ||
250 | spin_lock(&iTCO_wdt_private.io_lock); | |
251 | ||
887c8ec7 | 252 | iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res); |
e033351d | 253 | |
9e0ea345 WVS |
254 | /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
255 | val = inw(TCO1_CNT); | |
256 | val |= 0x0800; | |
257 | outw(val, TCO1_CNT); | |
258 | val = inw(TCO1_CNT); | |
259 | ||
260 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
261 | iTCO_wdt_set_NO_REBOOT_bit(); | |
262 | ||
263 | spin_unlock(&iTCO_wdt_private.io_lock); | |
264 | ||
265 | if ((val & 0x0800) == 0) | |
266 | return -1; | |
267 | return 0; | |
268 | } | |
269 | ||
bff23431 | 270 | static int iTCO_wdt_ping(struct watchdog_device *wd_dev) |
9e0ea345 WVS |
271 | { |
272 | spin_lock(&iTCO_wdt_private.io_lock); | |
273 | ||
bff23431 | 274 | iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout); |
e033351d | 275 | |
9e0ea345 | 276 | /* Reload the timer by writing to the TCO Timer Counter register */ |
24b3a167 | 277 | if (iTCO_wdt_private.iTCO_version >= 2) { |
9e0ea345 | 278 | outw(0x01, TCO_RLD); |
24b3a167 | 279 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
7e6811da PB |
280 | /* Reset the timeout status bit so that the timer |
281 | * needs to count down twice again before rebooting */ | |
282 | outw(0x0008, TCO1_STS); /* write 1 to clear bit */ | |
283 | ||
9e0ea345 | 284 | outb(0x01, TCO_RLD); |
7e6811da | 285 | } |
9e0ea345 WVS |
286 | |
287 | spin_unlock(&iTCO_wdt_private.io_lock); | |
288 | return 0; | |
289 | } | |
290 | ||
bff23431 | 291 | static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) |
9e0ea345 WVS |
292 | { |
293 | unsigned int val16; | |
294 | unsigned char val8; | |
295 | unsigned int tmrval; | |
296 | ||
297 | tmrval = seconds_to_ticks(t); | |
7e6811da PB |
298 | |
299 | /* For TCO v1 the timer counts down twice before rebooting */ | |
300 | if (iTCO_wdt_private.iTCO_version == 1) | |
301 | tmrval /= 2; | |
302 | ||
9e0ea345 WVS |
303 | /* from the specs: */ |
304 | /* "Values of 0h-3h are ignored and should not be attempted" */ | |
305 | if (tmrval < 0x04) | |
306 | return -EINVAL; | |
24b3a167 | 307 | if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) || |
9e0ea345 WVS |
308 | ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) |
309 | return -EINVAL; | |
310 | ||
e033351d WVS |
311 | iTCO_vendor_pre_set_heartbeat(tmrval); |
312 | ||
9e0ea345 | 313 | /* Write new heartbeat to watchdog */ |
24b3a167 | 314 | if (iTCO_wdt_private.iTCO_version >= 2) { |
9e0ea345 WVS |
315 | spin_lock(&iTCO_wdt_private.io_lock); |
316 | val16 = inw(TCOv2_TMR); | |
317 | val16 &= 0xfc00; | |
318 | val16 |= tmrval; | |
319 | outw(val16, TCOv2_TMR); | |
320 | val16 = inw(TCOv2_TMR); | |
321 | spin_unlock(&iTCO_wdt_private.io_lock); | |
322 | ||
323 | if ((val16 & 0x3ff) != tmrval) | |
324 | return -EINVAL; | |
325 | } else if (iTCO_wdt_private.iTCO_version == 1) { | |
326 | spin_lock(&iTCO_wdt_private.io_lock); | |
327 | val8 = inb(TCOv1_TMR); | |
328 | val8 &= 0xc0; | |
329 | val8 |= (tmrval & 0xff); | |
330 | outb(val8, TCOv1_TMR); | |
331 | val8 = inb(TCOv1_TMR); | |
332 | spin_unlock(&iTCO_wdt_private.io_lock); | |
333 | ||
334 | if ((val8 & 0x3f) != tmrval) | |
335 | return -EINVAL; | |
336 | } | |
337 | ||
bff23431 | 338 | wd_dev->timeout = t; |
9e0ea345 WVS |
339 | return 0; |
340 | } | |
341 | ||
bff23431 | 342 | static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) |
9e0ea345 WVS |
343 | { |
344 | unsigned int val16; | |
345 | unsigned char val8; | |
bff23431 | 346 | unsigned int time_left = 0; |
9e0ea345 WVS |
347 | |
348 | /* read the TCO Timer */ | |
24b3a167 | 349 | if (iTCO_wdt_private.iTCO_version >= 2) { |
9e0ea345 WVS |
350 | spin_lock(&iTCO_wdt_private.io_lock); |
351 | val16 = inw(TCO_RLD); | |
352 | val16 &= 0x3ff; | |
353 | spin_unlock(&iTCO_wdt_private.io_lock); | |
354 | ||
24b3a167 | 355 | time_left = ticks_to_seconds(val16); |
9e0ea345 WVS |
356 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
357 | spin_lock(&iTCO_wdt_private.io_lock); | |
358 | val8 = inb(TCO_RLD); | |
359 | val8 &= 0x3f; | |
7e6811da PB |
360 | if (!(inw(TCO1_STS) & 0x0008)) |
361 | val8 += (inb(TCOv1_TMR) & 0x3f); | |
9e0ea345 WVS |
362 | spin_unlock(&iTCO_wdt_private.io_lock); |
363 | ||
24b3a167 | 364 | time_left = ticks_to_seconds(val8); |
9e0ea345 | 365 | } |
bff23431 | 366 | return time_left; |
9e0ea345 WVS |
367 | } |
368 | ||
9e0ea345 WVS |
369 | /* |
370 | * Kernel Interfaces | |
371 | */ | |
372 | ||
bff23431 WVS |
373 | static const struct watchdog_info ident = { |
374 | .options = WDIOF_SETTIMEOUT | | |
375 | WDIOF_KEEPALIVEPING | | |
376 | WDIOF_MAGICCLOSE, | |
377 | .firmware_version = 0, | |
378 | .identity = DRV_NAME, | |
379 | }; | |
380 | ||
381 | static const struct watchdog_ops iTCO_wdt_ops = { | |
0e6fa3fb | 382 | .owner = THIS_MODULE, |
bff23431 | 383 | .start = iTCO_wdt_start, |
5f5e1909 JH |
384 | .stop = iTCO_wdt_stop, |
385 | .ping = iTCO_wdt_ping, | |
bff23431 WVS |
386 | .set_timeout = iTCO_wdt_set_timeout, |
387 | .get_timeleft = iTCO_wdt_get_timeleft, | |
9e0ea345 WVS |
388 | }; |
389 | ||
bff23431 WVS |
390 | static struct watchdog_device iTCO_wdt_watchdog_dev = { |
391 | .info = &ident, | |
5f5e1909 | 392 | .ops = &iTCO_wdt_ops, |
9e0ea345 WVS |
393 | }; |
394 | ||
9e0ea345 WVS |
395 | /* |
396 | * Init & exit routines | |
397 | */ | |
398 | ||
4b12b896 | 399 | static void iTCO_wdt_cleanup(void) |
887c8ec7 AS |
400 | { |
401 | /* Stop the timer before we leave */ | |
402 | if (!nowayout) | |
bff23431 | 403 | iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); |
887c8ec7 AS |
404 | |
405 | /* Deregister */ | |
bff23431 | 406 | watchdog_unregister_device(&iTCO_wdt_watchdog_dev); |
887c8ec7 AS |
407 | |
408 | /* release resources */ | |
409 | release_region(iTCO_wdt_private.tco_res->start, | |
410 | resource_size(iTCO_wdt_private.tco_res)); | |
411 | release_region(iTCO_wdt_private.smi_res->start, | |
412 | resource_size(iTCO_wdt_private.smi_res)); | |
24b3a167 PT |
413 | if (iTCO_wdt_private.iTCO_version >= 2) { |
414 | iounmap(iTCO_wdt_private.gcs_pmc); | |
415 | release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, | |
416 | resource_size(iTCO_wdt_private.gcs_pmc_res)); | |
887c8ec7 AS |
417 | } |
418 | ||
419 | iTCO_wdt_private.tco_res = NULL; | |
420 | iTCO_wdt_private.smi_res = NULL; | |
24b3a167 PT |
421 | iTCO_wdt_private.gcs_pmc_res = NULL; |
422 | iTCO_wdt_private.gcs_pmc = NULL; | |
887c8ec7 AS |
423 | } |
424 | ||
2d991a16 | 425 | static int iTCO_wdt_probe(struct platform_device *dev) |
9e0ea345 | 426 | { |
887c8ec7 | 427 | int ret = -ENODEV; |
12d60e28 | 428 | unsigned long val32; |
420b54de | 429 | struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev); |
887c8ec7 | 430 | |
420b54de | 431 | if (!pdata) |
887c8ec7 AS |
432 | goto out; |
433 | ||
434 | spin_lock_init(&iTCO_wdt_private.io_lock); | |
435 | ||
436 | iTCO_wdt_private.tco_res = | |
437 | platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO); | |
438 | if (!iTCO_wdt_private.tco_res) | |
439 | goto out; | |
440 | ||
441 | iTCO_wdt_private.smi_res = | |
442 | platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI); | |
443 | if (!iTCO_wdt_private.smi_res) | |
444 | goto out; | |
445 | ||
420b54de | 446 | iTCO_wdt_private.iTCO_version = pdata->version; |
887c8ec7 AS |
447 | iTCO_wdt_private.dev = dev; |
448 | iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent); | |
9e0ea345 WVS |
449 | |
450 | /* | |
24b3a167 PT |
451 | * Get the Memory-Mapped GCS or PMC register, we need it for the |
452 | * NO_REBOOT flag (TCO v2 and v3). | |
9e0ea345 | 453 | */ |
24b3a167 PT |
454 | if (iTCO_wdt_private.iTCO_version >= 2) { |
455 | iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev, | |
887c8ec7 | 456 | IORESOURCE_MEM, |
24b3a167 | 457 | ICH_RES_MEM_GCS_PMC); |
887c8ec7 | 458 | |
24b3a167 | 459 | if (!iTCO_wdt_private.gcs_pmc_res) |
887c8ec7 AS |
460 | goto out; |
461 | ||
24b3a167 PT |
462 | if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start, |
463 | resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) { | |
887c8ec7 | 464 | ret = -EBUSY; |
de8cd9a3 DL |
465 | goto out; |
466 | } | |
24b3a167 PT |
467 | iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start, |
468 | resource_size(iTCO_wdt_private.gcs_pmc_res)); | |
469 | if (!iTCO_wdt_private.gcs_pmc) { | |
887c8ec7 | 470 | ret = -EIO; |
24b3a167 | 471 | goto unreg_gcs_pmc; |
887c8ec7 | 472 | } |
9e0ea345 WVS |
473 | } |
474 | ||
475 | /* Check chipset's NO_REBOOT bit */ | |
e033351d | 476 | if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { |
27c766aa | 477 | pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); |
9e0ea345 | 478 | ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ |
24b3a167 | 479 | goto unmap_gcs_pmc; |
9e0ea345 WVS |
480 | } |
481 | ||
482 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
483 | iTCO_wdt_set_NO_REBOOT_bit(); | |
484 | ||
7cd5b08b | 485 | /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ |
887c8ec7 AS |
486 | if (!request_region(iTCO_wdt_private.smi_res->start, |
487 | resource_size(iTCO_wdt_private.smi_res), dev->name)) { | |
488 | pr_err("I/O address 0x%04llx already in use, device disabled\n", | |
4b98b32a | 489 | (u64)SMI_EN); |
887c8ec7 | 490 | ret = -EBUSY; |
24b3a167 | 491 | goto unmap_gcs_pmc; |
9e0ea345 | 492 | } |
0d098587 | 493 | if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) { |
887c8ec7 AS |
494 | /* |
495 | * Bit 13: TCO_EN -> 0 | |
496 | * Disables TCO logic generating an SMI# | |
497 | */ | |
deb9197b WVS |
498 | val32 = inl(SMI_EN); |
499 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ | |
500 | outl(val32, SMI_EN); | |
501 | } | |
9e0ea345 | 502 | |
887c8ec7 AS |
503 | if (!request_region(iTCO_wdt_private.tco_res->start, |
504 | resource_size(iTCO_wdt_private.tco_res), dev->name)) { | |
505 | pr_err("I/O address 0x%04llx already in use, device disabled\n", | |
4b98b32a | 506 | (u64)TCOBASE); |
887c8ec7 AS |
507 | ret = -EBUSY; |
508 | goto unreg_smi; | |
9e0ea345 WVS |
509 | } |
510 | ||
887c8ec7 | 511 | pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", |
420b54de | 512 | pdata->name, pdata->version, (u64)TCOBASE); |
9e0ea345 WVS |
513 | |
514 | /* Clear out the (probably old) status */ | |
2a7a0e9b | 515 | switch (iTCO_wdt_private.iTCO_version) { |
3b3a1c8f | 516 | case 5: |
2a7a0e9b MF |
517 | case 4: |
518 | outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ | |
519 | outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ | |
520 | break; | |
521 | case 3: | |
24b3a167 | 522 | outl(0x20008, TCO1_STS); |
2a7a0e9b MF |
523 | break; |
524 | case 2: | |
525 | case 1: | |
526 | default: | |
24b3a167 PT |
527 | outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ |
528 | outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ | |
529 | outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */ | |
2a7a0e9b | 530 | break; |
24b3a167 | 531 | } |
9e0ea345 | 532 | |
bff23431 WVS |
533 | iTCO_wdt_watchdog_dev.bootstatus = 0; |
534 | iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT; | |
535 | watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout); | |
c90789ba | 536 | iTCO_wdt_watchdog_dev.parent = &dev->dev; |
bff23431 | 537 | |
9e0ea345 | 538 | /* Make sure the watchdog is not running */ |
bff23431 | 539 | iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); |
9e0ea345 | 540 | |
0e6fa3fb AC |
541 | /* Check that the heartbeat value is within it's range; |
542 | if not reset to the default */ | |
bff23431 WVS |
543 | if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) { |
544 | iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT); | |
545 | pr_info("timeout value out of range, using %d\n", | |
546 | WATCHDOG_TIMEOUT); | |
9e0ea345 WVS |
547 | } |
548 | ||
bff23431 | 549 | ret = watchdog_register_device(&iTCO_wdt_watchdog_dev); |
9e0ea345 | 550 | if (ret != 0) { |
bff23431 | 551 | pr_err("cannot register watchdog device (err=%d)\n", ret); |
887c8ec7 | 552 | goto unreg_tco; |
9e0ea345 WVS |
553 | } |
554 | ||
27c766aa JP |
555 | pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", |
556 | heartbeat, nowayout); | |
9e0ea345 WVS |
557 | |
558 | return 0; | |
559 | ||
887c8ec7 AS |
560 | unreg_tco: |
561 | release_region(iTCO_wdt_private.tco_res->start, | |
562 | resource_size(iTCO_wdt_private.tco_res)); | |
563 | unreg_smi: | |
564 | release_region(iTCO_wdt_private.smi_res->start, | |
565 | resource_size(iTCO_wdt_private.smi_res)); | |
24b3a167 PT |
566 | unmap_gcs_pmc: |
567 | if (iTCO_wdt_private.iTCO_version >= 2) | |
568 | iounmap(iTCO_wdt_private.gcs_pmc); | |
569 | unreg_gcs_pmc: | |
570 | if (iTCO_wdt_private.iTCO_version >= 2) | |
571 | release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, | |
572 | resource_size(iTCO_wdt_private.gcs_pmc_res)); | |
887c8ec7 AS |
573 | out: |
574 | iTCO_wdt_private.tco_res = NULL; | |
575 | iTCO_wdt_private.smi_res = NULL; | |
24b3a167 PT |
576 | iTCO_wdt_private.gcs_pmc_res = NULL; |
577 | iTCO_wdt_private.gcs_pmc = NULL; | |
9e0ea345 | 578 | |
ec26985b | 579 | return ret; |
9e0ea345 WVS |
580 | } |
581 | ||
4b12b896 | 582 | static int iTCO_wdt_remove(struct platform_device *dev) |
9e0ea345 | 583 | { |
887c8ec7 | 584 | if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res) |
9e0ea345 WVS |
585 | iTCO_wdt_cleanup(); |
586 | ||
3836cc0f WVS |
587 | return 0; |
588 | } | |
589 | ||
590 | static void iTCO_wdt_shutdown(struct platform_device *dev) | |
591 | { | |
bff23431 | 592 | iTCO_wdt_stop(NULL); |
3836cc0f WVS |
593 | } |
594 | ||
f321c9cb RW |
595 | #ifdef CONFIG_PM_SLEEP |
596 | /* | |
597 | * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so | |
598 | * the watchdog cannot be pinged while in that state. In ACPI sleep states the | |
599 | * watchdog is stopped by the platform firmware. | |
600 | */ | |
601 | ||
602 | #ifdef CONFIG_ACPI | |
603 | static inline bool need_suspend(void) | |
604 | { | |
605 | return acpi_target_system_state() == ACPI_STATE_S0; | |
606 | } | |
607 | #else | |
608 | static inline bool need_suspend(void) { return true; } | |
609 | #endif | |
610 | ||
611 | static int iTCO_wdt_suspend_noirq(struct device *dev) | |
612 | { | |
613 | int ret = 0; | |
614 | ||
615 | iTCO_wdt_private.suspended = false; | |
616 | if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) { | |
617 | ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); | |
618 | if (!ret) | |
619 | iTCO_wdt_private.suspended = true; | |
620 | } | |
621 | return ret; | |
622 | } | |
623 | ||
624 | static int iTCO_wdt_resume_noirq(struct device *dev) | |
625 | { | |
626 | if (iTCO_wdt_private.suspended) | |
627 | iTCO_wdt_start(&iTCO_wdt_watchdog_dev); | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
6e938f6e | 632 | static const struct dev_pm_ops iTCO_wdt_pm = { |
f321c9cb RW |
633 | .suspend_noirq = iTCO_wdt_suspend_noirq, |
634 | .resume_noirq = iTCO_wdt_resume_noirq, | |
635 | }; | |
636 | ||
637 | #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) | |
638 | #else | |
639 | #define ITCO_WDT_PM_OPS NULL | |
640 | #endif /* CONFIG_PM_SLEEP */ | |
641 | ||
3836cc0f WVS |
642 | static struct platform_driver iTCO_wdt_driver = { |
643 | .probe = iTCO_wdt_probe, | |
82268714 | 644 | .remove = iTCO_wdt_remove, |
3836cc0f | 645 | .shutdown = iTCO_wdt_shutdown, |
3836cc0f | 646 | .driver = { |
3836cc0f | 647 | .name = DRV_NAME, |
f321c9cb | 648 | .pm = ITCO_WDT_PM_OPS, |
3836cc0f WVS |
649 | }, |
650 | }; | |
651 | ||
652 | static int __init iTCO_wdt_init_module(void) | |
653 | { | |
654 | int err; | |
655 | ||
27c766aa | 656 | pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); |
3836cc0f WVS |
657 | |
658 | err = platform_driver_register(&iTCO_wdt_driver); | |
659 | if (err) | |
660 | return err; | |
661 | ||
3836cc0f | 662 | return 0; |
3836cc0f WVS |
663 | } |
664 | ||
665 | static void __exit iTCO_wdt_cleanup_module(void) | |
666 | { | |
3836cc0f | 667 | platform_driver_unregister(&iTCO_wdt_driver); |
27c766aa | 668 | pr_info("Watchdog Module Unloaded\n"); |
9e0ea345 WVS |
669 | } |
670 | ||
671 | module_init(iTCO_wdt_init_module); | |
672 | module_exit(iTCO_wdt_cleanup_module); | |
673 | ||
674 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); | |
675 | MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); | |
3836cc0f | 676 | MODULE_VERSION(DRV_VERSION); |
9e0ea345 | 677 | MODULE_LICENSE("GPL"); |
e5de32e3 | 678 | MODULE_ALIAS("platform:" DRV_NAME); |