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9e0ea345 | 1 | /* |
12d60e28 | 2 | * intel TCO Watchdog Driver (Used in i82801 and i63xxESB chipsets) |
9e0ea345 | 3 | * |
12d60e28 | 4 | * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>. |
9e0ea345 WVS |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor | |
12 | * provide warranty for any of this software. This material is | |
13 | * provided "AS-IS" and at no charge. | |
14 | * | |
15 | * The TCO watchdog is implemented in the following I/O controller hubs: | |
16 | * (See the intel documentation on http://developer.intel.com.) | |
17 | * 82801AA (ICH) : document number 290655-003, 290677-014, | |
18 | * 82801AB (ICHO) : document number 290655-003, 290677-014, | |
19 | * 82801BA (ICH2) : document number 290687-002, 298242-027, | |
20 | * 82801BAM (ICH2-M) : document number 290687-002, 298242-027, | |
21 | * 82801CA (ICH3-S) : document number 290733-003, 290739-013, | |
22 | * 82801CAM (ICH3-M) : document number 290716-001, 290718-007, | |
28d41f53 WVS |
23 | * 82801DB (ICH4) : document number 290744-001, 290745-025, |
24 | * 82801DBM (ICH4-M) : document number 252337-001, 252663-008, | |
9e0ea345 | 25 | * 82801E (C-ICH) : document number 273599-001, 273645-002, |
28d41f53 WVS |
26 | * 82801EB (ICH5) : document number 252516-001, 252517-028, |
27 | * 82801ER (ICH5R) : document number 252516-001, 252517-028, | |
28 | * 6300ESB (6300ESB) : document number 300641-004, 300884-013, | |
29 | * 82801FB (ICH6) : document number 301473-002, 301474-026, | |
30 | * 82801FR (ICH6R) : document number 301473-002, 301474-026, | |
31 | * 82801FBM (ICH6-M) : document number 301473-002, 301474-026, | |
32 | * 82801FW (ICH6W) : document number 301473-001, 301474-026, | |
33 | * 82801FRW (ICH6RW) : document number 301473-001, 301474-026, | |
34 | * 631xESB (631xESB) : document number 313082-001, 313075-006, | |
35 | * 632xESB (632xESB) : document number 313082-001, 313075-006, | |
36 | * 82801GB (ICH7) : document number 307013-003, 307014-024, | |
37 | * 82801GR (ICH7R) : document number 307013-003, 307014-024, | |
38 | * 82801GDH (ICH7DH) : document number 307013-003, 307014-024, | |
39 | * 82801GBM (ICH7-M) : document number 307013-003, 307014-024, | |
40 | * 82801GHM (ICH7-M DH) : document number 307013-003, 307014-024, | |
41 | * 82801GU (ICH7-U) : document number 307013-003, 307014-024, | |
42 | * 82801HB (ICH8) : document number 313056-003, 313057-017, | |
43 | * 82801HR (ICH8R) : document number 313056-003, 313057-017, | |
44 | * 82801HBM (ICH8M) : document number 313056-003, 313057-017, | |
45 | * 82801HH (ICH8DH) : document number 313056-003, 313057-017, | |
46 | * 82801HO (ICH8DO) : document number 313056-003, 313057-017, | |
47 | * 82801HEM (ICH8M-E) : document number 313056-003, 313057-017, | |
48 | * 82801IB (ICH9) : document number 316972-004, 316973-012, | |
49 | * 82801IR (ICH9R) : document number 316972-004, 316973-012, | |
50 | * 82801IH (ICH9DH) : document number 316972-004, 316973-012, | |
51 | * 82801IO (ICH9DO) : document number 316972-004, 316973-012, | |
52 | * 82801IBM (ICH9M) : document number 316972-004, 316973-012, | |
53 | * 82801IEM (ICH9M-E) : document number 316972-004, 316973-012, | |
54 | * 82801JIB (ICH10) : document number 319973-002, 319974-002, | |
55 | * 82801JIR (ICH10R) : document number 319973-002, 319974-002, | |
56 | * 82801JD (ICH10D) : document number 319973-002, 319974-002, | |
79e8941d SH |
57 | * 82801JDO (ICH10DO) : document number 319973-002, 319974-002, |
58 | * 5 Series (PCH) : document number 322169-001, 322170-001, | |
59 | * 3400 Series (PCH) : document number 322169-001, 322170-001 | |
9e0ea345 WVS |
60 | */ |
61 | ||
62 | /* | |
63 | * Includes, defines, variables, module parameters, ... | |
64 | */ | |
65 | ||
66 | /* Module and version information */ | |
7944d3a5 | 67 | #define DRV_NAME "iTCO_wdt" |
12d60e28 | 68 | #define DRV_VERSION "1.05" |
9e0ea345 WVS |
69 | #define PFX DRV_NAME ": " |
70 | ||
71 | /* Includes */ | |
3836cc0f WVS |
72 | #include <linux/module.h> /* For module specific items */ |
73 | #include <linux/moduleparam.h> /* For new moduleparam's */ | |
74 | #include <linux/types.h> /* For standard types (like size_t) */ | |
75 | #include <linux/errno.h> /* For the -ENODEV/... values */ | |
76 | #include <linux/kernel.h> /* For printk/panic/... */ | |
0e6fa3fb AC |
77 | #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV |
78 | (WATCHDOG_MINOR) */ | |
3836cc0f | 79 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
3836cc0f WVS |
80 | #include <linux/init.h> /* For __init/__exit/... */ |
81 | #include <linux/fs.h> /* For file operations */ | |
82 | #include <linux/platform_device.h> /* For platform_driver framework */ | |
83 | #include <linux/pci.h> /* For pci functions */ | |
84 | #include <linux/ioport.h> /* For io-port access */ | |
85 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ | |
0e6fa3fb AC |
86 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
87 | #include <linux/io.h> /* For inb/outb/... */ | |
3836cc0f | 88 | |
0e6fa3fb | 89 | #include "iTCO_vendor.h" |
9e0ea345 WVS |
90 | |
91 | /* TCO related info */ | |
92 | enum iTCO_chipsets { | |
93 | TCO_ICH = 0, /* ICH */ | |
94 | TCO_ICH0, /* ICH0 */ | |
95 | TCO_ICH2, /* ICH2 */ | |
96 | TCO_ICH2M, /* ICH2-M */ | |
97 | TCO_ICH3, /* ICH3-S */ | |
98 | TCO_ICH3M, /* ICH3-M */ | |
99 | TCO_ICH4, /* ICH4 */ | |
100 | TCO_ICH4M, /* ICH4-M */ | |
101 | TCO_CICH, /* C-ICH */ | |
102 | TCO_ICH5, /* ICH5 & ICH5R */ | |
103 | TCO_6300ESB, /* 6300ESB */ | |
104 | TCO_ICH6, /* ICH6 & ICH6R */ | |
105 | TCO_ICH6M, /* ICH6-M */ | |
106 | TCO_ICH6W, /* ICH6W & ICH6RW */ | |
28d41f53 | 107 | TCO_631XESB, /* 631xESB/632xESB */ |
9e0ea345 | 108 | TCO_ICH7, /* ICH7 & ICH7R */ |
28d41f53 WVS |
109 | TCO_ICH7DH, /* ICH7DH */ |
110 | TCO_ICH7M, /* ICH7-M & ICH7-U */ | |
9e0ea345 | 111 | TCO_ICH7MDH, /* ICH7-M DH */ |
a8edd74e WVS |
112 | TCO_ICH8, /* ICH8 & ICH8R */ |
113 | TCO_ICH8DH, /* ICH8DH */ | |
114 | TCO_ICH8DO, /* ICH8DO */ | |
acf60351 | 115 | TCO_ICH8M, /* ICH8M */ |
28d41f53 | 116 | TCO_ICH8ME, /* ICH8M-E */ |
286201dc WVS |
117 | TCO_ICH9, /* ICH9 */ |
118 | TCO_ICH9R, /* ICH9R */ | |
119 | TCO_ICH9DH, /* ICH9DH */ | |
7944d3a5 | 120 | TCO_ICH9DO, /* ICH9DO */ |
28d41f53 WVS |
121 | TCO_ICH9M, /* ICH9M */ |
122 | TCO_ICH9ME, /* ICH9M-E */ | |
123 | TCO_ICH10, /* ICH10 */ | |
124 | TCO_ICH10R, /* ICH10R */ | |
125 | TCO_ICH10D, /* ICH10D */ | |
126 | TCO_ICH10DO, /* ICH10DO */ | |
79e8941d SH |
127 | TCO_PCH, /* PCH Desktop Full Featured */ |
128 | TCO_PCHM, /* PCH Mobile Full Featured */ | |
129 | TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */ | |
9e0ea345 WVS |
130 | }; |
131 | ||
132 | static struct { | |
133 | char *name; | |
134 | unsigned int iTCO_version; | |
135 | } iTCO_chipset_info[] __devinitdata = { | |
136 | {"ICH", 1}, | |
137 | {"ICH0", 1}, | |
138 | {"ICH2", 1}, | |
139 | {"ICH2-M", 1}, | |
140 | {"ICH3-S", 1}, | |
141 | {"ICH3-M", 1}, | |
142 | {"ICH4", 1}, | |
143 | {"ICH4-M", 1}, | |
144 | {"C-ICH", 1}, | |
145 | {"ICH5 or ICH5R", 1}, | |
146 | {"6300ESB", 1}, | |
147 | {"ICH6 or ICH6R", 2}, | |
148 | {"ICH6-M", 2}, | |
149 | {"ICH6W or ICH6RW", 2}, | |
28d41f53 | 150 | {"631xESB/632xESB", 2}, |
9e0ea345 | 151 | {"ICH7 or ICH7R", 2}, |
28d41f53 WVS |
152 | {"ICH7DH", 2}, |
153 | {"ICH7-M or ICH7-U", 2}, | |
9e0ea345 | 154 | {"ICH7-M DH", 2}, |
bcbf25bd | 155 | {"ICH8 or ICH8R", 2}, |
a8edd74e WVS |
156 | {"ICH8DH", 2}, |
157 | {"ICH8DO", 2}, | |
acf60351 | 158 | {"ICH8M", 2}, |
28d41f53 | 159 | {"ICH8M-E", 2}, |
286201dc WVS |
160 | {"ICH9", 2}, |
161 | {"ICH9R", 2}, | |
162 | {"ICH9DH", 2}, | |
a49056da | 163 | {"ICH9DO", 2}, |
28d41f53 WVS |
164 | {"ICH9M", 2}, |
165 | {"ICH9M-E", 2}, | |
166 | {"ICH10", 2}, | |
167 | {"ICH10R", 2}, | |
168 | {"ICH10D", 2}, | |
169 | {"ICH10DO", 2}, | |
79e8941d SH |
170 | {"PCH Desktop Full Featured", 2}, |
171 | {"PCH Mobile Full Featured", 2}, | |
172 | {"PCH Mobile SFF Full Featured", 2}, | |
0e6fa3fb | 173 | {NULL, 0} |
9e0ea345 WVS |
174 | }; |
175 | ||
c87b639a WVS |
176 | #define ITCO_PCI_DEVICE(dev, data) \ |
177 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
178 | .device = dev, \ | |
179 | .subvendor = PCI_ANY_ID, \ | |
180 | .subdevice = PCI_ANY_ID, \ | |
181 | .class = 0, \ | |
182 | .class_mask = 0, \ | |
183 | .driver_data = data | |
184 | ||
9e0ea345 WVS |
185 | /* |
186 | * This data only exists for exporting the supported PCI ids | |
187 | * via MODULE_DEVICE_TABLE. We do not actually register a | |
188 | * pci_driver, because the I/O Controller Hub has also other | |
189 | * functions that probably will be registered by other drivers. | |
190 | */ | |
191 | static struct pci_device_id iTCO_wdt_pci_tbl[] = { | |
0e6fa3fb AC |
192 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)}, |
193 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)}, | |
194 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)}, | |
195 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)}, | |
196 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)}, | |
197 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)}, | |
198 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)}, | |
199 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)}, | |
200 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)}, | |
201 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)}, | |
c87b639a | 202 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)}, |
0e6fa3fb AC |
203 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)}, |
204 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)}, | |
205 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)}, | |
c87b639a WVS |
206 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, |
207 | { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, | |
208 | { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, | |
209 | { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)}, | |
210 | { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)}, | |
211 | { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)}, | |
212 | { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)}, | |
213 | { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)}, | |
214 | { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)}, | |
215 | { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)}, | |
216 | { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)}, | |
217 | { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)}, | |
218 | { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)}, | |
219 | { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)}, | |
220 | { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)}, | |
221 | { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, | |
28d41f53 WVS |
222 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, |
223 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)}, | |
224 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, | |
225 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, | |
226 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, | |
227 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, | |
228 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, | |
229 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, | |
230 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, | |
231 | { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, | |
232 | { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, | |
233 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, | |
234 | { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, | |
235 | { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)}, | |
236 | { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)}, | |
237 | { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)}, | |
238 | { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)}, | |
239 | { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)}, | |
240 | { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)}, | |
79e8941d SH |
241 | { ITCO_PCI_DEVICE(0x3b00, TCO_PCH)}, |
242 | { ITCO_PCI_DEVICE(0x3b01, TCO_PCHM)}, | |
243 | { ITCO_PCI_DEVICE(0x3b0d, TCO_PCHMSFF)}, | |
9e0ea345 WVS |
244 | { 0, }, /* End of list */ |
245 | }; | |
0e6fa3fb | 246 | MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); |
9e0ea345 WVS |
247 | |
248 | /* Address definitions for the TCO */ | |
0e6fa3fb | 249 | /* TCO base address */ |
0a7e6582 | 250 | #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60) |
0e6fa3fb | 251 | /* SMI Control and Enable Register */ |
0a7e6582 | 252 | #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30) |
9e0ea345 | 253 | |
0a7e6582 WVS |
254 | #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ |
255 | #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ | |
256 | #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ | |
257 | #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ | |
258 | #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ | |
259 | #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ | |
260 | #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ | |
261 | #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ | |
262 | #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ | |
9e0ea345 WVS |
263 | |
264 | /* internal variables */ | |
265 | static unsigned long is_active; | |
266 | static char expect_release; | |
0e6fa3fb AC |
267 | static struct { /* this is private data for the iTCO_wdt device */ |
268 | /* TCO version/generation */ | |
269 | unsigned int iTCO_version; | |
270 | /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ | |
271 | unsigned long ACPIBASE; | |
272 | /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/ | |
273 | unsigned long __iomem *gcs; | |
274 | /* the lock for io operations */ | |
275 | spinlock_t io_lock; | |
276 | /* the PCI-device */ | |
277 | struct pci_dev *pdev; | |
9e0ea345 WVS |
278 | } iTCO_wdt_private; |
279 | ||
0e6fa3fb AC |
280 | /* the watchdog platform device */ |
281 | static struct platform_device *iTCO_wdt_platform_device; | |
3836cc0f | 282 | |
9e0ea345 WVS |
283 | /* module parameters */ |
284 | #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ | |
285 | static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ | |
286 | module_param(heartbeat, int, 0); | |
143a2e54 WVS |
287 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. " |
288 | "(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" | |
289 | __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); | |
9e0ea345 WVS |
290 | |
291 | static int nowayout = WATCHDOG_NOWAYOUT; | |
292 | module_param(nowayout, int, 0); | |
0e6fa3fb AC |
293 | MODULE_PARM_DESC(nowayout, |
294 | "Watchdog cannot be stopped once started (default=" | |
295 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
e033351d | 296 | |
9e0ea345 WVS |
297 | /* |
298 | * Some TCO specific functions | |
299 | */ | |
300 | ||
301 | static inline unsigned int seconds_to_ticks(int seconds) | |
302 | { | |
303 | /* the internal timer is stored as ticks which decrement | |
304 | * every 0.6 seconds */ | |
305 | return (seconds * 10) / 6; | |
306 | } | |
307 | ||
308 | static void iTCO_wdt_set_NO_REBOOT_bit(void) | |
309 | { | |
310 | u32 val32; | |
311 | ||
312 | /* Set the NO_REBOOT bit: this disables reboots */ | |
313 | if (iTCO_wdt_private.iTCO_version == 2) { | |
314 | val32 = readl(iTCO_wdt_private.gcs); | |
315 | val32 |= 0x00000020; | |
316 | writel(val32, iTCO_wdt_private.gcs); | |
317 | } else if (iTCO_wdt_private.iTCO_version == 1) { | |
318 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
319 | val32 |= 0x00000002; | |
320 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); | |
321 | } | |
322 | } | |
323 | ||
324 | static int iTCO_wdt_unset_NO_REBOOT_bit(void) | |
325 | { | |
326 | int ret = 0; | |
327 | u32 val32; | |
328 | ||
329 | /* Unset the NO_REBOOT bit: this enables reboots */ | |
330 | if (iTCO_wdt_private.iTCO_version == 2) { | |
331 | val32 = readl(iTCO_wdt_private.gcs); | |
332 | val32 &= 0xffffffdf; | |
333 | writel(val32, iTCO_wdt_private.gcs); | |
334 | ||
335 | val32 = readl(iTCO_wdt_private.gcs); | |
336 | if (val32 & 0x00000020) | |
337 | ret = -EIO; | |
338 | } else if (iTCO_wdt_private.iTCO_version == 1) { | |
339 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
340 | val32 &= 0xfffffffd; | |
341 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); | |
342 | ||
343 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); | |
344 | if (val32 & 0x00000002) | |
345 | ret = -EIO; | |
346 | } | |
347 | ||
348 | return ret; /* returns: 0 = OK, -EIO = Error */ | |
349 | } | |
350 | ||
351 | static int iTCO_wdt_start(void) | |
352 | { | |
353 | unsigned int val; | |
354 | ||
355 | spin_lock(&iTCO_wdt_private.io_lock); | |
356 | ||
e033351d WVS |
357 | iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat); |
358 | ||
9e0ea345 WVS |
359 | /* disable chipset's NO_REBOOT bit */ |
360 | if (iTCO_wdt_unset_NO_REBOOT_bit()) { | |
2ba7d7b3 | 361 | spin_unlock(&iTCO_wdt_private.io_lock); |
143a2e54 WVS |
362 | printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, " |
363 | "reboot disabled by hardware\n"); | |
9e0ea345 WVS |
364 | return -EIO; |
365 | } | |
366 | ||
7cd5b08b WVS |
367 | /* Force the timer to its reload value by writing to the TCO_RLD |
368 | register */ | |
369 | if (iTCO_wdt_private.iTCO_version == 2) | |
370 | outw(0x01, TCO_RLD); | |
371 | else if (iTCO_wdt_private.iTCO_version == 1) | |
372 | outb(0x01, TCO_RLD); | |
373 | ||
9e0ea345 WVS |
374 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
375 | val = inw(TCO1_CNT); | |
376 | val &= 0xf7ff; | |
377 | outw(val, TCO1_CNT); | |
378 | val = inw(TCO1_CNT); | |
379 | spin_unlock(&iTCO_wdt_private.io_lock); | |
380 | ||
381 | if (val & 0x0800) | |
382 | return -1; | |
383 | return 0; | |
384 | } | |
385 | ||
386 | static int iTCO_wdt_stop(void) | |
387 | { | |
388 | unsigned int val; | |
389 | ||
390 | spin_lock(&iTCO_wdt_private.io_lock); | |
391 | ||
e033351d WVS |
392 | iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE); |
393 | ||
9e0ea345 WVS |
394 | /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
395 | val = inw(TCO1_CNT); | |
396 | val |= 0x0800; | |
397 | outw(val, TCO1_CNT); | |
398 | val = inw(TCO1_CNT); | |
399 | ||
400 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
401 | iTCO_wdt_set_NO_REBOOT_bit(); | |
402 | ||
403 | spin_unlock(&iTCO_wdt_private.io_lock); | |
404 | ||
405 | if ((val & 0x0800) == 0) | |
406 | return -1; | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static int iTCO_wdt_keepalive(void) | |
411 | { | |
412 | spin_lock(&iTCO_wdt_private.io_lock); | |
413 | ||
e033351d WVS |
414 | iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat); |
415 | ||
9e0ea345 | 416 | /* Reload the timer by writing to the TCO Timer Counter register */ |
0e6fa3fb | 417 | if (iTCO_wdt_private.iTCO_version == 2) |
9e0ea345 | 418 | outw(0x01, TCO_RLD); |
0e6fa3fb | 419 | else if (iTCO_wdt_private.iTCO_version == 1) |
9e0ea345 | 420 | outb(0x01, TCO_RLD); |
9e0ea345 WVS |
421 | |
422 | spin_unlock(&iTCO_wdt_private.io_lock); | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static int iTCO_wdt_set_heartbeat(int t) | |
427 | { | |
428 | unsigned int val16; | |
429 | unsigned char val8; | |
430 | unsigned int tmrval; | |
431 | ||
432 | tmrval = seconds_to_ticks(t); | |
433 | /* from the specs: */ | |
434 | /* "Values of 0h-3h are ignored and should not be attempted" */ | |
435 | if (tmrval < 0x04) | |
436 | return -EINVAL; | |
437 | if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) || | |
438 | ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) | |
439 | return -EINVAL; | |
440 | ||
e033351d WVS |
441 | iTCO_vendor_pre_set_heartbeat(tmrval); |
442 | ||
9e0ea345 WVS |
443 | /* Write new heartbeat to watchdog */ |
444 | if (iTCO_wdt_private.iTCO_version == 2) { | |
445 | spin_lock(&iTCO_wdt_private.io_lock); | |
446 | val16 = inw(TCOv2_TMR); | |
447 | val16 &= 0xfc00; | |
448 | val16 |= tmrval; | |
449 | outw(val16, TCOv2_TMR); | |
450 | val16 = inw(TCOv2_TMR); | |
451 | spin_unlock(&iTCO_wdt_private.io_lock); | |
452 | ||
453 | if ((val16 & 0x3ff) != tmrval) | |
454 | return -EINVAL; | |
455 | } else if (iTCO_wdt_private.iTCO_version == 1) { | |
456 | spin_lock(&iTCO_wdt_private.io_lock); | |
457 | val8 = inb(TCOv1_TMR); | |
458 | val8 &= 0xc0; | |
459 | val8 |= (tmrval & 0xff); | |
460 | outb(val8, TCOv1_TMR); | |
461 | val8 = inb(TCOv1_TMR); | |
462 | spin_unlock(&iTCO_wdt_private.io_lock); | |
463 | ||
464 | if ((val8 & 0x3f) != tmrval) | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
468 | heartbeat = t; | |
469 | return 0; | |
470 | } | |
471 | ||
0e6fa3fb | 472 | static int iTCO_wdt_get_timeleft(int *time_left) |
9e0ea345 WVS |
473 | { |
474 | unsigned int val16; | |
475 | unsigned char val8; | |
476 | ||
477 | /* read the TCO Timer */ | |
478 | if (iTCO_wdt_private.iTCO_version == 2) { | |
479 | spin_lock(&iTCO_wdt_private.io_lock); | |
480 | val16 = inw(TCO_RLD); | |
481 | val16 &= 0x3ff; | |
482 | spin_unlock(&iTCO_wdt_private.io_lock); | |
483 | ||
484 | *time_left = (val16 * 6) / 10; | |
485 | } else if (iTCO_wdt_private.iTCO_version == 1) { | |
486 | spin_lock(&iTCO_wdt_private.io_lock); | |
487 | val8 = inb(TCO_RLD); | |
488 | val8 &= 0x3f; | |
489 | spin_unlock(&iTCO_wdt_private.io_lock); | |
490 | ||
491 | *time_left = (val8 * 6) / 10; | |
80060362 JG |
492 | } else |
493 | return -EINVAL; | |
9e0ea345 WVS |
494 | return 0; |
495 | } | |
496 | ||
497 | /* | |
498 | * /dev/watchdog handling | |
499 | */ | |
500 | ||
0e6fa3fb | 501 | static int iTCO_wdt_open(struct inode *inode, struct file *file) |
9e0ea345 WVS |
502 | { |
503 | /* /dev/watchdog can only be opened once */ | |
504 | if (test_and_set_bit(0, &is_active)) | |
505 | return -EBUSY; | |
506 | ||
507 | /* | |
508 | * Reload and activate timer | |
509 | */ | |
9e0ea345 WVS |
510 | iTCO_wdt_start(); |
511 | return nonseekable_open(inode, file); | |
512 | } | |
513 | ||
0e6fa3fb | 514 | static int iTCO_wdt_release(struct inode *inode, struct file *file) |
9e0ea345 WVS |
515 | { |
516 | /* | |
517 | * Shut off the timer. | |
518 | */ | |
519 | if (expect_release == 42) { | |
520 | iTCO_wdt_stop(); | |
521 | } else { | |
0e6fa3fb AC |
522 | printk(KERN_CRIT PFX |
523 | "Unexpected close, not stopping watchdog!\n"); | |
9e0ea345 WVS |
524 | iTCO_wdt_keepalive(); |
525 | } | |
526 | clear_bit(0, &is_active); | |
527 | expect_release = 0; | |
528 | return 0; | |
529 | } | |
530 | ||
0e6fa3fb AC |
531 | static ssize_t iTCO_wdt_write(struct file *file, const char __user *data, |
532 | size_t len, loff_t *ppos) | |
9e0ea345 WVS |
533 | { |
534 | /* See if we got the magic character 'V' and reload the timer */ | |
535 | if (len) { | |
536 | if (!nowayout) { | |
537 | size_t i; | |
538 | ||
0e6fa3fb AC |
539 | /* note: just in case someone wrote the magic |
540 | character five months ago... */ | |
9e0ea345 WVS |
541 | expect_release = 0; |
542 | ||
0e6fa3fb AC |
543 | /* scan to see whether or not we got the |
544 | magic character */ | |
9e0ea345 WVS |
545 | for (i = 0; i != len; i++) { |
546 | char c; | |
7944d3a5 | 547 | if (get_user(c, data + i)) |
9e0ea345 WVS |
548 | return -EFAULT; |
549 | if (c == 'V') | |
550 | expect_release = 42; | |
551 | } | |
552 | } | |
553 | ||
554 | /* someone wrote to us, we should reload the timer */ | |
555 | iTCO_wdt_keepalive(); | |
556 | } | |
557 | return len; | |
558 | } | |
559 | ||
0e6fa3fb AC |
560 | static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, |
561 | unsigned long arg) | |
9e0ea345 WVS |
562 | { |
563 | int new_options, retval = -EINVAL; | |
564 | int new_heartbeat; | |
9e0ea345 WVS |
565 | void __user *argp = (void __user *)arg; |
566 | int __user *p = argp; | |
567 | static struct watchdog_info ident = { | |
568 | .options = WDIOF_SETTIMEOUT | | |
569 | WDIOF_KEEPALIVEPING | | |
570 | WDIOF_MAGICCLOSE, | |
571 | .firmware_version = 0, | |
572 | .identity = DRV_NAME, | |
573 | }; | |
574 | ||
575 | switch (cmd) { | |
0e6fa3fb AC |
576 | case WDIOC_GETSUPPORT: |
577 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | |
578 | case WDIOC_GETSTATUS: | |
579 | case WDIOC_GETBOOTSTATUS: | |
580 | return put_user(0, p); | |
9e0ea345 | 581 | |
0e6fa3fb AC |
582 | case WDIOC_SETOPTIONS: |
583 | { | |
584 | if (get_user(new_options, p)) | |
585 | return -EFAULT; | |
9e0ea345 | 586 | |
0e6fa3fb AC |
587 | if (new_options & WDIOS_DISABLECARD) { |
588 | iTCO_wdt_stop(); | |
589 | retval = 0; | |
9e0ea345 | 590 | } |
0e6fa3fb | 591 | if (new_options & WDIOS_ENABLECARD) { |
9e0ea345 | 592 | iTCO_wdt_keepalive(); |
0e6fa3fb AC |
593 | iTCO_wdt_start(); |
594 | retval = 0; | |
9e0ea345 | 595 | } |
0e6fa3fb AC |
596 | return retval; |
597 | } | |
0c06090c WVS |
598 | case WDIOC_KEEPALIVE: |
599 | iTCO_wdt_keepalive(); | |
600 | return 0; | |
601 | ||
0e6fa3fb AC |
602 | case WDIOC_SETTIMEOUT: |
603 | { | |
604 | if (get_user(new_heartbeat, p)) | |
605 | return -EFAULT; | |
606 | if (iTCO_wdt_set_heartbeat(new_heartbeat)) | |
607 | return -EINVAL; | |
608 | iTCO_wdt_keepalive(); | |
609 | /* Fall */ | |
610 | } | |
611 | case WDIOC_GETTIMEOUT: | |
612 | return put_user(heartbeat, p); | |
613 | case WDIOC_GETTIMELEFT: | |
614 | { | |
615 | int time_left; | |
616 | if (iTCO_wdt_get_timeleft(&time_left)) | |
617 | return -EINVAL; | |
618 | return put_user(time_left, p); | |
619 | } | |
620 | default: | |
621 | return -ENOTTY; | |
9e0ea345 WVS |
622 | } |
623 | } | |
624 | ||
9e0ea345 WVS |
625 | /* |
626 | * Kernel Interfaces | |
627 | */ | |
628 | ||
2b8693c0 | 629 | static const struct file_operations iTCO_wdt_fops = { |
0e6fa3fb AC |
630 | .owner = THIS_MODULE, |
631 | .llseek = no_llseek, | |
632 | .write = iTCO_wdt_write, | |
633 | .unlocked_ioctl = iTCO_wdt_ioctl, | |
634 | .open = iTCO_wdt_open, | |
635 | .release = iTCO_wdt_release, | |
9e0ea345 WVS |
636 | }; |
637 | ||
638 | static struct miscdevice iTCO_wdt_miscdev = { | |
639 | .minor = WATCHDOG_MINOR, | |
640 | .name = "watchdog", | |
641 | .fops = &iTCO_wdt_fops, | |
642 | }; | |
643 | ||
9e0ea345 WVS |
644 | /* |
645 | * Init & exit routines | |
646 | */ | |
647 | ||
0e6fa3fb AC |
648 | static int __devinit iTCO_wdt_init(struct pci_dev *pdev, |
649 | const struct pci_device_id *ent, struct platform_device *dev) | |
9e0ea345 WVS |
650 | { |
651 | int ret; | |
652 | u32 base_address; | |
653 | unsigned long RCBA; | |
12d60e28 | 654 | unsigned long val32; |
9e0ea345 WVS |
655 | |
656 | /* | |
657 | * Find the ACPI/PM base I/O address which is the base | |
658 | * for the TCO registers (TCOBASE=ACPIBASE + 0x60) | |
659 | * ACPIBASE is bits [15:7] from 0x40-0x43 | |
660 | */ | |
661 | pci_read_config_dword(pdev, 0x40, &base_address); | |
0d4804b3 | 662 | base_address &= 0x0000ff80; |
9e0ea345 WVS |
663 | if (base_address == 0x00000000) { |
664 | /* Something's wrong here, ACPIBASE has to be set */ | |
665 | printk(KERN_ERR PFX "failed to get TCOBASE address\n"); | |
4802c653 | 666 | pci_dev_put(pdev); |
9e0ea345 WVS |
667 | return -ENODEV; |
668 | } | |
0e6fa3fb AC |
669 | iTCO_wdt_private.iTCO_version = |
670 | iTCO_chipset_info[ent->driver_data].iTCO_version; | |
9e0ea345 WVS |
671 | iTCO_wdt_private.ACPIBASE = base_address; |
672 | iTCO_wdt_private.pdev = pdev; | |
673 | ||
0e6fa3fb AC |
674 | /* Get the Memory-Mapped GCS register, we need it for the |
675 | NO_REBOOT flag (TCO v2). To get access to it you have to | |
676 | read RCBA from PCI Config space 0xf0 and use it as base. | |
677 | GCS = RCBA + ICH6_GCS(0x3410). */ | |
9e0ea345 WVS |
678 | if (iTCO_wdt_private.iTCO_version == 2) { |
679 | pci_read_config_dword(pdev, 0xf0, &base_address); | |
de8cd9a3 DL |
680 | if ((base_address & 1) == 0) { |
681 | printk(KERN_ERR PFX "RCBA is disabled by harddware\n"); | |
682 | ret = -ENODEV; | |
683 | goto out; | |
684 | } | |
9e0ea345 | 685 | RCBA = base_address & 0xffffc000; |
0e6fa3fb | 686 | iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4); |
9e0ea345 WVS |
687 | } |
688 | ||
689 | /* Check chipset's NO_REBOOT bit */ | |
e033351d | 690 | if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { |
143a2e54 WVS |
691 | printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, " |
692 | "reboot disabled by hardware\n"); | |
9e0ea345 | 693 | ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ |
de8cd9a3 | 694 | goto out_unmap; |
9e0ea345 WVS |
695 | } |
696 | ||
697 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ | |
698 | iTCO_wdt_set_NO_REBOOT_bit(); | |
699 | ||
7cd5b08b | 700 | /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ |
9e0ea345 | 701 | if (!request_region(SMI_EN, 4, "iTCO_wdt")) { |
0e6fa3fb AC |
702 | printk(KERN_ERR PFX |
703 | "I/O address 0x%04lx already in use\n", SMI_EN); | |
9e0ea345 | 704 | ret = -EIO; |
de8cd9a3 | 705 | goto out_unmap; |
9e0ea345 | 706 | } |
12d60e28 WVS |
707 | /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ |
708 | val32 = inl(SMI_EN); | |
709 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ | |
710 | outl(val32, SMI_EN); | |
9e0ea345 | 711 | |
0e6fa3fb AC |
712 | /* The TCO I/O registers reside in a 32-byte range pointed to |
713 | by the TCOBASE value */ | |
714 | if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) { | |
715 | printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", | |
9e0ea345 WVS |
716 | TCOBASE); |
717 | ret = -EIO; | |
7cd5b08b | 718 | goto unreg_smi_en; |
9e0ea345 WVS |
719 | } |
720 | ||
0e6fa3fb AC |
721 | printk(KERN_INFO PFX |
722 | "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", | |
723 | iTCO_chipset_info[ent->driver_data].name, | |
724 | iTCO_chipset_info[ent->driver_data].iTCO_version, | |
725 | TCOBASE); | |
9e0ea345 WVS |
726 | |
727 | /* Clear out the (probably old) status */ | |
c6904ddb WVS |
728 | outb(8, TCO1_STS); /* Clear the Time Out Status bit */ |
729 | outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */ | |
730 | outb(4, TCO2_STS); /* Clear BOOT_STS bit */ | |
9e0ea345 WVS |
731 | |
732 | /* Make sure the watchdog is not running */ | |
733 | iTCO_wdt_stop(); | |
734 | ||
0e6fa3fb AC |
735 | /* Check that the heartbeat value is within it's range; |
736 | if not reset to the default */ | |
9e0ea345 WVS |
737 | if (iTCO_wdt_set_heartbeat(heartbeat)) { |
738 | iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); | |
143a2e54 WVS |
739 | printk(KERN_INFO PFX |
740 | "heartbeat value must be 2 < heartbeat < 39 (TCO v1) " | |
741 | "or 613 (TCO v2), using %d\n", heartbeat); | |
9e0ea345 WVS |
742 | } |
743 | ||
9e0ea345 WVS |
744 | ret = misc_register(&iTCO_wdt_miscdev); |
745 | if (ret != 0) { | |
0e6fa3fb AC |
746 | printk(KERN_ERR PFX |
747 | "cannot register miscdev on minor=%d (err=%d)\n", | |
748 | WATCHDOG_MINOR, ret); | |
1bef84be | 749 | goto unreg_region; |
9e0ea345 WVS |
750 | } |
751 | ||
0e6fa3fb AC |
752 | printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", |
753 | heartbeat, nowayout); | |
9e0ea345 WVS |
754 | |
755 | return 0; | |
756 | ||
9e0ea345 | 757 | unreg_region: |
0e6fa3fb | 758 | release_region(TCOBASE, 0x20); |
7cd5b08b WVS |
759 | unreg_smi_en: |
760 | release_region(SMI_EN, 4); | |
de8cd9a3 | 761 | out_unmap: |
9e0ea345 WVS |
762 | if (iTCO_wdt_private.iTCO_version == 2) |
763 | iounmap(iTCO_wdt_private.gcs); | |
de8cd9a3 | 764 | out: |
4802c653 | 765 | pci_dev_put(iTCO_wdt_private.pdev); |
1bef84be | 766 | iTCO_wdt_private.ACPIBASE = 0; |
9e0ea345 WVS |
767 | return ret; |
768 | } | |
769 | ||
08113e39 | 770 | static void __devexit iTCO_wdt_cleanup(void) |
9e0ea345 WVS |
771 | { |
772 | /* Stop the timer before we leave */ | |
773 | if (!nowayout) | |
774 | iTCO_wdt_stop(); | |
775 | ||
776 | /* Deregister */ | |
777 | misc_deregister(&iTCO_wdt_miscdev); | |
9e0ea345 | 778 | release_region(TCOBASE, 0x20); |
7cd5b08b | 779 | release_region(SMI_EN, 4); |
9e0ea345 WVS |
780 | if (iTCO_wdt_private.iTCO_version == 2) |
781 | iounmap(iTCO_wdt_private.gcs); | |
4802c653 | 782 | pci_dev_put(iTCO_wdt_private.pdev); |
1bef84be | 783 | iTCO_wdt_private.ACPIBASE = 0; |
9e0ea345 WVS |
784 | } |
785 | ||
08113e39 | 786 | static int __devinit iTCO_wdt_probe(struct platform_device *dev) |
9e0ea345 WVS |
787 | { |
788 | int found = 0; | |
789 | struct pci_dev *pdev = NULL; | |
790 | const struct pci_device_id *ent; | |
791 | ||
792 | spin_lock_init(&iTCO_wdt_private.io_lock); | |
793 | ||
794 | for_each_pci_dev(pdev) { | |
795 | ent = pci_match_id(iTCO_wdt_pci_tbl, pdev); | |
796 | if (ent) { | |
3836cc0f | 797 | if (!(iTCO_wdt_init(pdev, ent, dev))) { |
9e0ea345 WVS |
798 | found++; |
799 | break; | |
800 | } | |
801 | } | |
802 | } | |
803 | ||
804 | if (!found) { | |
805 | printk(KERN_INFO PFX "No card detected\n"); | |
806 | return -ENODEV; | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
08113e39 | 812 | static int __devexit iTCO_wdt_remove(struct platform_device *dev) |
9e0ea345 WVS |
813 | { |
814 | if (iTCO_wdt_private.ACPIBASE) | |
815 | iTCO_wdt_cleanup(); | |
816 | ||
3836cc0f WVS |
817 | return 0; |
818 | } | |
819 | ||
820 | static void iTCO_wdt_shutdown(struct platform_device *dev) | |
821 | { | |
822 | iTCO_wdt_stop(); | |
823 | } | |
824 | ||
825 | #define iTCO_wdt_suspend NULL | |
826 | #define iTCO_wdt_resume NULL | |
827 | ||
828 | static struct platform_driver iTCO_wdt_driver = { | |
829 | .probe = iTCO_wdt_probe, | |
08113e39 | 830 | .remove = __devexit_p(iTCO_wdt_remove), |
3836cc0f WVS |
831 | .shutdown = iTCO_wdt_shutdown, |
832 | .suspend = iTCO_wdt_suspend, | |
833 | .resume = iTCO_wdt_resume, | |
834 | .driver = { | |
835 | .owner = THIS_MODULE, | |
836 | .name = DRV_NAME, | |
837 | }, | |
838 | }; | |
839 | ||
840 | static int __init iTCO_wdt_init_module(void) | |
841 | { | |
842 | int err; | |
843 | ||
7cd5b08b WVS |
844 | printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n", |
845 | DRV_VERSION); | |
3836cc0f WVS |
846 | |
847 | err = platform_driver_register(&iTCO_wdt_driver); | |
848 | if (err) | |
849 | return err; | |
850 | ||
0e6fa3fb AC |
851 | iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, |
852 | -1, NULL, 0); | |
3836cc0f WVS |
853 | if (IS_ERR(iTCO_wdt_platform_device)) { |
854 | err = PTR_ERR(iTCO_wdt_platform_device); | |
855 | goto unreg_platform_driver; | |
856 | } | |
857 | ||
858 | return 0; | |
859 | ||
860 | unreg_platform_driver: | |
861 | platform_driver_unregister(&iTCO_wdt_driver); | |
862 | return err; | |
863 | } | |
864 | ||
865 | static void __exit iTCO_wdt_cleanup_module(void) | |
866 | { | |
867 | platform_device_unregister(iTCO_wdt_platform_device); | |
868 | platform_driver_unregister(&iTCO_wdt_driver); | |
9e0ea345 WVS |
869 | printk(KERN_INFO PFX "Watchdog Module Unloaded.\n"); |
870 | } | |
871 | ||
872 | module_init(iTCO_wdt_init_module); | |
873 | module_exit(iTCO_wdt_cleanup_module); | |
874 | ||
875 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); | |
876 | MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); | |
3836cc0f | 877 | MODULE_VERSION(DRV_VERSION); |
9e0ea345 WVS |
878 | MODULE_LICENSE("GPL"); |
879 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |