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[WATCHDOG] spin_lock_init() fixes
[mirror_ubuntu-bionic-kernel.git] / drivers / watchdog / iTCO_wdt.c
CommitLineData
9e0ea345
WVS		 1/*
2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
3 *
bffda5c8 4 * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
9e0ea345
WVS		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
a8edd74e
WVS		 38 * 82801HB (ICH8) : document number 313056-002, 313057-004,
39 * 82801HR (ICH8R) : document number 313056-002, 313057-004,
40 * 82801HH (ICH8DH) : document number 313056-002, 313057-004,
41 * 82801HO (ICH8DO) : document number 313056-002, 313057-004,
286201dc
WVS		 42 * 82801IB (ICH9) : document number 316972-001, 316973-001,
43 * 82801IR (ICH9R) : document number 316972-001, 316973-001,
44 * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
45 * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
998e6787
SK		 46 * 631xESB (631xESB) : document number 313082-001, 313075-005,
47 * 632xESB (632xESB) : document number 313082-001, 313075-005
9e0ea345
WVS		 48 */
49
50/*
51 * Includes, defines, variables, module parameters, ...
52 */
53
54/* Module and version information */
55#define DRV_NAME "iTCO_wdt"
286201dc
WVS		 56#define DRV_VERSION "1.02"
57#define DRV_RELDATE "26-Jul-2007"
9e0ea345
WVS		 58#define PFX DRV_NAME ": "
59
60/* Includes */
3836cc0f
WVS		 61#include <linux/module.h> /* For module specific items */
62#include <linux/moduleparam.h> /* For new moduleparam's */
63#include <linux/types.h> /* For standard types (like size_t) */
64#include <linux/errno.h> /* For the -ENODEV/... values */
65#include <linux/kernel.h> /* For printk/panic/... */
66#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
67#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f
WVS		 68#include <linux/init.h> /* For __init/__exit/... */
69#include <linux/fs.h> /* For file operations */
70#include <linux/platform_device.h> /* For platform_driver framework */
71#include <linux/pci.h> /* For pci functions */
72#include <linux/ioport.h> /* For io-port access */
73#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
74
75#include <asm/uaccess.h> /* For copy_to_user/put_user/... */
76#include <asm/io.h> /* For inb/outb/... */
9e0ea345
WVS		 77
78/* TCO related info */
79enum iTCO_chipsets {
80 TCO_ICH = 0, /* ICH */
81 TCO_ICH0, /* ICH0 */
82 TCO_ICH2, /* ICH2 */
83 TCO_ICH2M, /* ICH2-M */
84 TCO_ICH3, /* ICH3-S */
85 TCO_ICH3M, /* ICH3-M */
86 TCO_ICH4, /* ICH4 */
87 TCO_ICH4M, /* ICH4-M */
88 TCO_CICH, /* C-ICH */
89 TCO_ICH5, /* ICH5 & ICH5R */
90 TCO_6300ESB, /* 6300ESB */
91 TCO_ICH6, /* ICH6 & ICH6R */
92 TCO_ICH6M, /* ICH6-M */
93 TCO_ICH6W, /* ICH6W & ICH6RW */
94 TCO_ICH7, /* ICH7 & ICH7R */
95 TCO_ICH7M, /* ICH7-M */
96 TCO_ICH7MDH, /* ICH7-M DH */
a8edd74e
WVS		 97 TCO_ICH8, /* ICH8 & ICH8R */
98 TCO_ICH8DH, /* ICH8DH */
99 TCO_ICH8DO, /* ICH8DO */
286201dc
WVS		 100 TCO_ICH9, /* ICH9 */
101 TCO_ICH9R, /* ICH9R */
102 TCO_ICH9DH, /* ICH9DH */
998e6787 103 TCO_631XESB, /* 631xESB/632xESB */
9e0ea345
WVS		 104};
105
106static struct {
107 char *name;
108 unsigned int iTCO_version;
109} iTCO_chipset_info[] __devinitdata = {
110 {"ICH", 1},
111 {"ICH0", 1},
112 {"ICH2", 1},
113 {"ICH2-M", 1},
114 {"ICH3-S", 1},
115 {"ICH3-M", 1},
116 {"ICH4", 1},
117 {"ICH4-M", 1},
118 {"C-ICH", 1},
119 {"ICH5 or ICH5R", 1},
120 {"6300ESB", 1},
121 {"ICH6 or ICH6R", 2},
122 {"ICH6-M", 2},
123 {"ICH6W or ICH6RW", 2},
124 {"ICH7 or ICH7R", 2},
125 {"ICH7-M", 2},
126 {"ICH7-M DH", 2},
bcbf25bd 127 {"ICH8 or ICH8R", 2},
a8edd74e
WVS		 128 {"ICH8DH", 2},
129 {"ICH8DO", 2},
286201dc
WVS		 130 {"ICH9", 2},
131 {"ICH9R", 2},
132 {"ICH9DH", 2},
998e6787 133 {"631xESB/632xESB", 2},
9e0ea345
WVS		 134 {NULL,0}
135};
136
137/*
138 * This data only exists for exporting the supported PCI ids
139 * via MODULE_DEVICE_TABLE. We do not actually register a
140 * pci_driver, because the I/O Controller Hub has also other
141 * functions that probably will be registered by other drivers.
142 */
143static struct pci_device_id iTCO_wdt_pci_tbl[] = {
144 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH },
145 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH0 },
146 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2 },
147 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2M },
148 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3 },
149 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3M },
150 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4 },
151 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4M },
152 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_CICH },
153 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH5 },
154 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_6300ESB },
155 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6 },
156 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6M },
157 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6W },
158 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7 },
159 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7M },
160 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7MDH },
bcbf25bd 161 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8 },
a8edd74e
WVS		 162 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DH },
163 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DO },
286201dc
WVS		 164 { PCI_VENDOR_ID_INTEL, 0x2918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9 },
165 { PCI_VENDOR_ID_INTEL, 0x2916, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9R },
166 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9DH },
998e6787 167 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
7e0a86f7
WVS		 168 { PCI_VENDOR_ID_INTEL, 0x2671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
169 { PCI_VENDOR_ID_INTEL, 0x2672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
170 { PCI_VENDOR_ID_INTEL, 0x2673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
171 { PCI_VENDOR_ID_INTEL, 0x2674, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
172 { PCI_VENDOR_ID_INTEL, 0x2675, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
173 { PCI_VENDOR_ID_INTEL, 0x2676, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
174 { PCI_VENDOR_ID_INTEL, 0x2677, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
175 { PCI_VENDOR_ID_INTEL, 0x2678, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
176 { PCI_VENDOR_ID_INTEL, 0x2679, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
177 { PCI_VENDOR_ID_INTEL, 0x267a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
178 { PCI_VENDOR_ID_INTEL, 0x267b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
179 { PCI_VENDOR_ID_INTEL, 0x267c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
180 { PCI_VENDOR_ID_INTEL, 0x267d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
181 { PCI_VENDOR_ID_INTEL, 0x267e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
182 { PCI_VENDOR_ID_INTEL, 0x267f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
9e0ea345
WVS		 183 { 0, }, /* End of list */
184};
185MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
186
187/* Address definitions for the TCO */
188#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
189#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
190
191#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
192#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
193#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
194#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
195#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
196#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
197#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
198#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
199#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
200
201/* internal variables */
202static unsigned long is_active;
203static char expect_release;
204static struct { /* this is private data for the iTCO_wdt device */
205 unsigned int iTCO_version; /* TCO version/generation */
206 unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
207 unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
208 spinlock_t io_lock; /* the lock for io operations */
209 struct pci_dev *pdev; /* the PCI-device */
210} iTCO_wdt_private;
211
3836cc0f
WVS		 212static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
213
9e0ea345
WVS		 214/* module parameters */
215#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
216static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
217module_param(heartbeat, int, 0);
218MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
219
220static int nowayout = WATCHDOG_NOWAYOUT;
221module_param(nowayout, int, 0);
bffda5c8 222MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
9e0ea345 223
e033351d
WVS		 224/* iTCO Vendor Specific Support hooks */
225#ifdef CONFIG_ITCO_VENDOR_SUPPORT
226extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
227extern void iTCO_vendor_pre_stop(unsigned long);
228extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
229extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
230extern int iTCO_vendor_check_noreboot_on(void);
231#else
232#define iTCO_vendor_pre_start(acpibase, heartbeat) {}
233#define iTCO_vendor_pre_stop(acpibase) {}
234#define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
235#define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
236#define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
237#endif
238
9e0ea345
WVS		 239/*
240 * Some TCO specific functions
241 */
242
243static inline unsigned int seconds_to_ticks(int seconds)
244{
245 /* the internal timer is stored as ticks which decrement
246 * every 0.6 seconds */
247 return (seconds * 10) / 6;
248}
249
250static void iTCO_wdt_set_NO_REBOOT_bit(void)
251{
252 u32 val32;
253
254 /* Set the NO_REBOOT bit: this disables reboots */
255 if (iTCO_wdt_private.iTCO_version == 2) {
256 val32 = readl(iTCO_wdt_private.gcs);
257 val32 |= 0x00000020;
258 writel(val32, iTCO_wdt_private.gcs);
259 } else if (iTCO_wdt_private.iTCO_version == 1) {
260 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
261 val32 |= 0x00000002;
262 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
263 }
264}
265
266static int iTCO_wdt_unset_NO_REBOOT_bit(void)
267{
268 int ret = 0;
269 u32 val32;
270
271 /* Unset the NO_REBOOT bit: this enables reboots */
272 if (iTCO_wdt_private.iTCO_version == 2) {
273 val32 = readl(iTCO_wdt_private.gcs);
274 val32 &= 0xffffffdf;
275 writel(val32, iTCO_wdt_private.gcs);
276
277 val32 = readl(iTCO_wdt_private.gcs);
278 if (val32 & 0x00000020)
279 ret = -EIO;
280 } else if (iTCO_wdt_private.iTCO_version == 1) {
281 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
282 val32 &= 0xfffffffd;
283 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
284
285 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
286 if (val32 & 0x00000002)
287 ret = -EIO;
288 }
289
290 return ret; /* returns: 0 = OK, -EIO = Error */
291}
292
293static int iTCO_wdt_start(void)
294{
295 unsigned int val;
296
297 spin_lock(&iTCO_wdt_private.io_lock);
298
e033351d
WVS		 299 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
300
9e0ea345
WVS		 301 /* disable chipset's NO_REBOOT bit */
302 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
2ba7d7b3 303 spin_unlock(&iTCO_wdt_private.io_lock);
9e0ea345
WVS		 304 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
305 return -EIO;
306 }
307
308 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
309 val = inw(TCO1_CNT);
310 val &= 0xf7ff;
311 outw(val, TCO1_CNT);
312 val = inw(TCO1_CNT);
313 spin_unlock(&iTCO_wdt_private.io_lock);
314
315 if (val & 0x0800)
316 return -1;
317 return 0;
318}
319
320static int iTCO_wdt_stop(void)
321{
322 unsigned int val;
323
324 spin_lock(&iTCO_wdt_private.io_lock);
325
e033351d
WVS		 326 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
327
9e0ea345
WVS		 328 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
329 val = inw(TCO1_CNT);
330 val |= 0x0800;
331 outw(val, TCO1_CNT);
332 val = inw(TCO1_CNT);
333
334 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
335 iTCO_wdt_set_NO_REBOOT_bit();
336
337 spin_unlock(&iTCO_wdt_private.io_lock);
338
339 if ((val & 0x0800) == 0)
340 return -1;
341 return 0;
342}
343
344static int iTCO_wdt_keepalive(void)
345{
346 spin_lock(&iTCO_wdt_private.io_lock);
347
e033351d
WVS		 348 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
349
9e0ea345
WVS		 350 /* Reload the timer by writing to the TCO Timer Counter register */
351 if (iTCO_wdt_private.iTCO_version == 2) {
352 outw(0x01, TCO_RLD);
353 } else if (iTCO_wdt_private.iTCO_version == 1) {
354 outb(0x01, TCO_RLD);
355 }
356
357 spin_unlock(&iTCO_wdt_private.io_lock);
358 return 0;
359}
360
361static int iTCO_wdt_set_heartbeat(int t)
362{
363 unsigned int val16;
364 unsigned char val8;
365 unsigned int tmrval;
366
367 tmrval = seconds_to_ticks(t);
368 /* from the specs: */
369 /* "Values of 0h-3h are ignored and should not be attempted" */
370 if (tmrval < 0x04)
371 return -EINVAL;
372 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
373 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
374 return -EINVAL;
375
e033351d
WVS		 376 iTCO_vendor_pre_set_heartbeat(tmrval);
377
9e0ea345
WVS		 378 /* Write new heartbeat to watchdog */
379 if (iTCO_wdt_private.iTCO_version == 2) {
380 spin_lock(&iTCO_wdt_private.io_lock);
381 val16 = inw(TCOv2_TMR);
382 val16 &= 0xfc00;
383 val16 |= tmrval;
384 outw(val16, TCOv2_TMR);
385 val16 = inw(TCOv2_TMR);
386 spin_unlock(&iTCO_wdt_private.io_lock);
387
388 if ((val16 & 0x3ff) != tmrval)
389 return -EINVAL;
390 } else if (iTCO_wdt_private.iTCO_version == 1) {
391 spin_lock(&iTCO_wdt_private.io_lock);
392 val8 = inb(TCOv1_TMR);
393 val8 &= 0xc0;
394 val8 |= (tmrval & 0xff);
395 outb(val8, TCOv1_TMR);
396 val8 = inb(TCOv1_TMR);
397 spin_unlock(&iTCO_wdt_private.io_lock);
398
399 if ((val8 & 0x3f) != tmrval)
400 return -EINVAL;
401 }
402
403 heartbeat = t;
404 return 0;
405}
406
407static int iTCO_wdt_get_timeleft (int *time_left)
408{
409 unsigned int val16;
410 unsigned char val8;
411
412 /* read the TCO Timer */
413 if (iTCO_wdt_private.iTCO_version == 2) {
414 spin_lock(&iTCO_wdt_private.io_lock);
415 val16 = inw(TCO_RLD);
416 val16 &= 0x3ff;
417 spin_unlock(&iTCO_wdt_private.io_lock);
418
419 *time_left = (val16 * 6) / 10;
420 } else if (iTCO_wdt_private.iTCO_version == 1) {
421 spin_lock(&iTCO_wdt_private.io_lock);
422 val8 = inb(TCO_RLD);
423 val8 &= 0x3f;
424 spin_unlock(&iTCO_wdt_private.io_lock);
425
426 *time_left = (val8 * 6) / 10;
80060362
JG		 427 } else
428 return -EINVAL;
9e0ea345
WVS		 429 return 0;
430}
431
432/*
433 * /dev/watchdog handling
434 */
435
436static int iTCO_wdt_open (struct inode *inode, struct file *file)
437{
438 /* /dev/watchdog can only be opened once */
439 if (test_and_set_bit(0, &is_active))
440 return -EBUSY;
441
442 /*
443 * Reload and activate timer
444 */
445 iTCO_wdt_keepalive();
446 iTCO_wdt_start();
447 return nonseekable_open(inode, file);
448}
449
450static int iTCO_wdt_release (struct inode *inode, struct file *file)
451{
452 /*
453 * Shut off the timer.
454 */
455 if (expect_release == 42) {
456 iTCO_wdt_stop();
457 } else {
458 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
459 iTCO_wdt_keepalive();
460 }
461 clear_bit(0, &is_active);
462 expect_release = 0;
463 return 0;
464}
465
466static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
467 size_t len, loff_t * ppos)
468{
469 /* See if we got the magic character 'V' and reload the timer */
470 if (len) {
471 if (!nowayout) {
472 size_t i;
473
474 /* note: just in case someone wrote the magic character
475 * five months ago... */
476 expect_release = 0;
477
478 /* scan to see whether or not we got the magic character */
479 for (i = 0; i != len; i++) {
480 char c;
481 if (get_user(c, data+i))
482 return -EFAULT;
483 if (c == 'V')
484 expect_release = 42;
485 }
486 }
487
488 /* someone wrote to us, we should reload the timer */
489 iTCO_wdt_keepalive();
490 }
491 return len;
492}
493
494static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
495 unsigned int cmd, unsigned long arg)
496{
497 int new_options, retval = -EINVAL;
498 int new_heartbeat;
9e0ea345
WVS		 499 void __user *argp = (void __user *)arg;
500 int __user *p = argp;
501 static struct watchdog_info ident = {
502 .options = WDIOF_SETTIMEOUT |
503 WDIOF_KEEPALIVEPING |
504 WDIOF_MAGICCLOSE,
505 .firmware_version = 0,
506 .identity = DRV_NAME,
507 };
508
509 switch (cmd) {
510 case WDIOC_GETSUPPORT:
511 return copy_to_user(argp, &ident,
512 sizeof (ident)) ? -EFAULT : 0;
513
514 case WDIOC_GETSTATUS:
515 case WDIOC_GETBOOTSTATUS:
516 return put_user(0, p);
517
518 case WDIOC_KEEPALIVE:
519 iTCO_wdt_keepalive();
520 return 0;
521
522 case WDIOC_SETOPTIONS:
523 {
524 if (get_user(new_options, p))
525 return -EFAULT;
526
527 if (new_options & WDIOS_DISABLECARD) {
528 iTCO_wdt_stop();
529 retval = 0;
530 }
531
532 if (new_options & WDIOS_ENABLECARD) {
533 iTCO_wdt_keepalive();
534 iTCO_wdt_start();
535 retval = 0;
536 }
537
538 return retval;
539 }
540
541 case WDIOC_SETTIMEOUT:
542 {
543 if (get_user(new_heartbeat, p))
544 return -EFAULT;
545
546 if (iTCO_wdt_set_heartbeat(new_heartbeat))
547 return -EINVAL;
548
549 iTCO_wdt_keepalive();
550 /* Fall */
551 }
552
553 case WDIOC_GETTIMEOUT:
554 return put_user(heartbeat, p);
555
556 case WDIOC_GETTIMELEFT:
557 {
80060362
JG		 558 int time_left;
559
9e0ea345
WVS		 560 if (iTCO_wdt_get_timeleft(&time_left))
561 return -EINVAL;
562
563 return put_user(time_left, p);
564 }
565
566 default:
f311896a 567 return -ENOTTY;
9e0ea345
WVS		 568 }
569}
570
9e0ea345
WVS		 571/*
572 * Kernel Interfaces
573 */
574
2b8693c0 575static const struct file_operations iTCO_wdt_fops = {
9e0ea345
WVS		 576 .owner = THIS_MODULE,
577 .llseek = no_llseek,
578 .write = iTCO_wdt_write,
579 .ioctl = iTCO_wdt_ioctl,
580 .open = iTCO_wdt_open,
581 .release = iTCO_wdt_release,
582};
583
584static struct miscdevice iTCO_wdt_miscdev = {
585 .minor = WATCHDOG_MINOR,
586 .name = "watchdog",
587 .fops = &iTCO_wdt_fops,
588};
589
9e0ea345
WVS		 590/*
591 * Init & exit routines
592 */
593
3836cc0f 594static int iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
9e0ea345
WVS		 595{
596 int ret;
597 u32 base_address;
598 unsigned long RCBA;
599 unsigned long val32;
600
601 /*
602 * Find the ACPI/PM base I/O address which is the base
603 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
604 * ACPIBASE is bits [15:7] from 0x40-0x43
605 */
606 pci_read_config_dword(pdev, 0x40, &base_address);
0d4804b3 607 base_address &= 0x0000ff80;
9e0ea345
WVS		 608 if (base_address == 0x00000000) {
609 /* Something's wrong here, ACPIBASE has to be set */
610 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
4802c653 611 pci_dev_put(pdev);
9e0ea345
WVS		 612 return -ENODEV;
613 }
614 iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
615 iTCO_wdt_private.ACPIBASE = base_address;
616 iTCO_wdt_private.pdev = pdev;
617
618 /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
619 /* To get access to it you have to read RCBA from PCI Config space 0xf0
620 and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
621 if (iTCO_wdt_private.iTCO_version == 2) {
622 pci_read_config_dword(pdev, 0xf0, &base_address);
623 RCBA = base_address & 0xffffc000;
624 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
625 }
626
627 /* Check chipset's NO_REBOOT bit */
e033351d 628 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
9e0ea345
WVS		 629 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
630 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
631 goto out;
632 }
633
634 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
635 iTCO_wdt_set_NO_REBOOT_bit();
636
637 /* Set the TCO_EN bit in SMI_EN register */
638 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
639 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
640 SMI_EN );
641 ret = -EIO;
642 goto out;
643 }
644 val32 = inl(SMI_EN);
645 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
646 outl(val32, SMI_EN);
647 release_region(SMI_EN, 4);
648
649 /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
650 if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
651 printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
652 TCOBASE);
653 ret = -EIO;
654 goto out;
655 }
656
657 printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
658 iTCO_chipset_info[ent->driver_data].name,
659 iTCO_chipset_info[ent->driver_data].iTCO_version,
660 TCOBASE);
661
662 /* Clear out the (probably old) status */
663 outb(0, TCO1_STS);
664 outb(3, TCO2_STS);
665
666 /* Make sure the watchdog is not running */
667 iTCO_wdt_stop();
668
669 /* Check that the heartbeat value is within it's range ; if not reset to the default */
670 if (iTCO_wdt_set_heartbeat(heartbeat)) {
671 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
672 printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
673 heartbeat);
674 }
675
9e0ea345
WVS		 676 ret = misc_register(&iTCO_wdt_miscdev);
677 if (ret != 0) {
678 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
679 WATCHDOG_MINOR, ret);
1bef84be 680 goto unreg_region;
9e0ea345
WVS		 681 }
682
683 printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
684 heartbeat, nowayout);
685
686 return 0;
687
9e0ea345
WVS		 688unreg_region:
689 release_region (TCOBASE, 0x20);
690out:
691 if (iTCO_wdt_private.iTCO_version == 2)
692 iounmap(iTCO_wdt_private.gcs);
4802c653 693 pci_dev_put(iTCO_wdt_private.pdev);
1bef84be 694 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 695 return ret;
696}
697
3836cc0f 698static void iTCO_wdt_cleanup(void)
9e0ea345
WVS		 699{
700 /* Stop the timer before we leave */
701 if (!nowayout)
702 iTCO_wdt_stop();
703
704 /* Deregister */
705 misc_deregister(&iTCO_wdt_miscdev);
9e0ea345
WVS		 706 release_region(TCOBASE, 0x20);
707 if (iTCO_wdt_private.iTCO_version == 2)
708 iounmap(iTCO_wdt_private.gcs);
4802c653 709 pci_dev_put(iTCO_wdt_private.pdev);
1bef84be 710 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 711}
712
3836cc0f 713static int iTCO_wdt_probe(struct platform_device *dev)
9e0ea345
WVS		 714{
715 int found = 0;
716 struct pci_dev *pdev = NULL;
717 const struct pci_device_id *ent;
718
719 spin_lock_init(&iTCO_wdt_private.io_lock);
720
721 for_each_pci_dev(pdev) {
722 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
723 if (ent) {
3836cc0f 724 if (!(iTCO_wdt_init(pdev, ent, dev))) {
9e0ea345
WVS		 725 found++;
726 break;
727 }
728 }
729 }
730
731 if (!found) {
732 printk(KERN_INFO PFX "No card detected\n");
733 return -ENODEV;
734 }
735
736 return 0;
737}
738
3836cc0f 739static int iTCO_wdt_remove(struct platform_device *dev)
9e0ea345
WVS		 740{
741 if (iTCO_wdt_private.ACPIBASE)
742 iTCO_wdt_cleanup();
743
3836cc0f
WVS		 744 return 0;
745}
746
747static void iTCO_wdt_shutdown(struct platform_device *dev)
748{
749 iTCO_wdt_stop();
750}
751
752#define iTCO_wdt_suspend NULL
753#define iTCO_wdt_resume NULL
754
755static struct platform_driver iTCO_wdt_driver = {
756 .probe = iTCO_wdt_probe,
757 .remove = iTCO_wdt_remove,
758 .shutdown = iTCO_wdt_shutdown,
759 .suspend = iTCO_wdt_suspend,
760 .resume = iTCO_wdt_resume,
761 .driver = {
762 .owner = THIS_MODULE,
763 .name = DRV_NAME,
764 },
765};
766
767static int __init iTCO_wdt_init_module(void)
768{
769 int err;
770
771 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
772 DRV_VERSION, DRV_RELDATE);
773
774 err = platform_driver_register(&iTCO_wdt_driver);
775 if (err)
776 return err;
777
778 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
779 if (IS_ERR(iTCO_wdt_platform_device)) {
780 err = PTR_ERR(iTCO_wdt_platform_device);
781 goto unreg_platform_driver;
782 }
783
784 return 0;
785
786unreg_platform_driver:
787 platform_driver_unregister(&iTCO_wdt_driver);
788 return err;
789}
790
791static void __exit iTCO_wdt_cleanup_module(void)
792{
793 platform_device_unregister(iTCO_wdt_platform_device);
794 platform_driver_unregister(&iTCO_wdt_driver);
9e0ea345
WVS		 795 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
796}
797
798module_init(iTCO_wdt_init_module);
799module_exit(iTCO_wdt_cleanup_module);
800
801MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
802MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f 803MODULE_VERSION(DRV_VERSION);
9e0ea345
WVS		 804MODULE_LICENSE("GPL");
805MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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