[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / imgpdc_wdt.c

/*
 * Imagination Technologies PowerDown Controller Watchdog Timer.
 *
 * Copyright (c) 2014 Imagination Technologies Ltd.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
 *                                                     2012 Henrik Nordstrom
 *
 * Notes
 * -----
 * The timeout value is rounded to the next power of two clock cycles.
 * This is configured using the PDC_WDT_CONFIG register, according to this
 * formula:
 *
 *     timeout = 2^(delay + 1) clock cycles
 *
 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
 *
 * Therefore, the hardware only allows to program watchdog timeouts, expressed
 * as a power of two number of watchdog clock cycles. The current implementation
 * guarantees that the actual watchdog timeout will be _at least_ the value
 * programmed in the imgpdg_wdt driver.
 *
 * The following table shows how the user-configured timeout relates
 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
 *
 * input timeout | WD_DELAY | actual timeout
 * -----------------------------------
 *      10       |   18     |  13 seconds
 *      20       |   19     |  26 seconds
 *      30       |   20     |  52 seconds
 *      60       |   21     |  104 seconds
 *
 * Albeit coarse, this granularity would suffice most watchdog uses.
 * If the platform allows it, the user should be able to change the watchdog
 * clock rate and achieve a finer timeout granularity.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/watchdog.h>

/* registers */
#define PDC_WDT_SOFT_RESET		0x00
#define PDC_WDT_CONFIG			0x04
  #define PDC_WDT_CONFIG_ENABLE		BIT(31)
  #define PDC_WDT_CONFIG_DELAY_MASK	0x1f

#define PDC_WDT_TICKLE1			0x08
#define PDC_WDT_TICKLE1_MAGIC		0xabcd1234
#define PDC_WDT_TICKLE2			0x0c
#define PDC_WDT_TICKLE2_MAGIC		0x4321dcba

#define PDC_WDT_TICKLE_STATUS_MASK	0x7
#define PDC_WDT_TICKLE_STATUS_SHIFT	0
#define PDC_WDT_TICKLE_STATUS_HRESET	0x0  /* Hard reset */
#define PDC_WDT_TICKLE_STATUS_TIMEOUT	0x1  /* Timeout */
#define PDC_WDT_TICKLE_STATUS_TICKLE	0x2  /* Tickled incorrectly */
#define PDC_WDT_TICKLE_STATUS_SRESET	0x3  /* Soft reset */
#define PDC_WDT_TICKLE_STATUS_USER	0x4  /* User reset */

/* Timeout values are in seconds */
#define PDC_WDT_MIN_TIMEOUT		1
#define PDC_WDT_DEF_TIMEOUT		64

static int heartbeat;
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds "
	"(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

struct pdc_wdt_dev {
	struct watchdog_device wdt_dev;
	struct clk *wdt_clk;
	struct clk *sys_clk;
	void __iomem *base;
};

static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
{
	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);

	writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
	writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);

	return 0;
}

static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
{
	unsigned int val;
	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);

	val = readl(wdt->base + PDC_WDT_CONFIG);
	val &= ~PDC_WDT_CONFIG_ENABLE;
	writel(val, wdt->base + PDC_WDT_CONFIG);

	/* Must tickle to finish the stop */
	pdc_wdt_keepalive(wdt_dev);

	return 0;
}

static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt)
{
	unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
	unsigned int val;

	val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
	val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
	writel(val, wdt->base + PDC_WDT_CONFIG);
}

static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
			       unsigned int new_timeout)
{
	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);

	wdt->wdt_dev.timeout = new_timeout;

	__pdc_wdt_set_timeout(wdt);

	return 0;
}

/* Start the watchdog timer (delay should already be set) */
static int pdc_wdt_start(struct watchdog_device *wdt_dev)
{
	unsigned int val;
	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);

	__pdc_wdt_set_timeout(wdt);

	val = readl(wdt->base + PDC_WDT_CONFIG);
	val |= PDC_WDT_CONFIG_ENABLE;
	writel(val, wdt->base + PDC_WDT_CONFIG);

	return 0;
}

static int pdc_wdt_restart(struct watchdog_device *wdt_dev,
			   unsigned long action, void *data)
{
	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);

	/* Assert SOFT_RESET */
	writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);

	return 0;
}

static const struct watchdog_info pdc_wdt_info = {
	.identity	= "IMG PDC Watchdog",
	.options	= WDIOF_SETTIMEOUT |
			  WDIOF_KEEPALIVEPING |
			  WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops pdc_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= pdc_wdt_start,
	.stop		= pdc_wdt_stop,
	.ping		= pdc_wdt_keepalive,
	.set_timeout	= pdc_wdt_set_timeout,
	.restart        = pdc_wdt_restart,
};

static int pdc_wdt_probe(struct platform_device *pdev)
{
	u64 div;
	int ret, val;
	unsigned long clk_rate;
	struct pdc_wdt_dev *pdc_wdt;

	pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL);
	if (!pdc_wdt)
		return -ENOMEM;

	pdc_wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pdc_wdt->base))
		return PTR_ERR(pdc_wdt->base);

	pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys");
	if (IS_ERR(pdc_wdt->sys_clk)) {
		dev_err(&pdev->dev, "failed to get the sys clock\n");
		return PTR_ERR(pdc_wdt->sys_clk);
	}

	pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt");
	if (IS_ERR(pdc_wdt->wdt_clk)) {
		dev_err(&pdev->dev, "failed to get the wdt clock\n");
		return PTR_ERR(pdc_wdt->wdt_clk);
	}

	ret = clk_prepare_enable(pdc_wdt->sys_clk);
	if (ret) {
		dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
		return ret;
	}

	ret = clk_prepare_enable(pdc_wdt->wdt_clk);
	if (ret) {
		dev_err(&pdev->dev, "could not prepare or enable wdt clock\n");
		goto disable_sys_clk;
	}

	/* We use the clock rate to calculate the max timeout */
	clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
	if (clk_rate == 0) {
		dev_err(&pdev->dev, "failed to get clock rate\n");
		ret = -EINVAL;
		goto disable_wdt_clk;
	}

	if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
		dev_err(&pdev->dev, "invalid clock rate\n");
		ret = -EINVAL;
		goto disable_wdt_clk;
	}

	if (order_base_2(clk_rate) == 0)
		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
	else
		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;

	pdc_wdt->wdt_dev.info = &pdc_wdt_info;
	pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;

	div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1);
	do_div(div, clk_rate);
	pdc_wdt->wdt_dev.max_timeout = div;
	pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;
	pdc_wdt->wdt_dev.parent = &pdev->dev;
	watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);

	watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev);

	pdc_wdt_stop(&pdc_wdt->wdt_dev);

	/* Find what caused the last reset */
	val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
	val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
	switch (val) {
	case PDC_WDT_TICKLE_STATUS_TICKLE:
	case PDC_WDT_TICKLE_STATUS_TIMEOUT:
		pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;
		dev_info(&pdev->dev,
			 "watchdog module last reset due to timeout\n");
		break;
	case PDC_WDT_TICKLE_STATUS_HRESET:
		dev_info(&pdev->dev,
			 "watchdog module last reset due to hard reset\n");
		break;
	case PDC_WDT_TICKLE_STATUS_SRESET:
		dev_info(&pdev->dev,
			 "watchdog module last reset due to soft reset\n");
		break;
	case PDC_WDT_TICKLE_STATUS_USER:
		dev_info(&pdev->dev,
			 "watchdog module last reset due to user reset\n");
		break;
	default:
		dev_info(&pdev->dev,
			 "contains an illegal status code (%08x)\n", val);
		break;
	}

	watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
	watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128);

	platform_set_drvdata(pdev, pdc_wdt);

	ret = watchdog_register_device(&pdc_wdt->wdt_dev);
	if (ret)
		goto disable_wdt_clk;

	return 0;

disable_wdt_clk:
	clk_disable_unprepare(pdc_wdt->wdt_clk);
disable_sys_clk:
	clk_disable_unprepare(pdc_wdt->sys_clk);
	return ret;
}

static void pdc_wdt_shutdown(struct platform_device *pdev)
{
	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);

	pdc_wdt_stop(&pdc_wdt->wdt_dev);
}

static int pdc_wdt_remove(struct platform_device *pdev)
{
	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);

	pdc_wdt_stop(&pdc_wdt->wdt_dev);
	watchdog_unregister_device(&pdc_wdt->wdt_dev);
	clk_disable_unprepare(pdc_wdt->wdt_clk);
	clk_disable_unprepare(pdc_wdt->sys_clk);

	return 0;
}

static const struct of_device_id pdc_wdt_match[] = {
	{ .compatible = "img,pdc-wdt" },
	{}
};
MODULE_DEVICE_TABLE(of, pdc_wdt_match);

static struct platform_driver pdc_wdt_driver = {
	.driver = {
		.name = "imgpdc-wdt",
		.of_match_table	= pdc_wdt_match,
	},
	.probe = pdc_wdt_probe,
	.remove = pdc_wdt_remove,
	.shutdown = pdc_wdt_shutdown,
};
module_platform_driver(pdc_wdt_driver);

MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
93937669 NT	1	/*
	2	* Imagination Technologies PowerDown Controller Watchdog Timer.
	3	*
	4	* Copyright (c) 2014 Imagination Technologies Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*
	10	* Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
	11	* 2012 Henrik Nordstrom
c1f26387 EG	12	*
	13	* Notes
	14	* -----
	15	* The timeout value is rounded to the next power of two clock cycles.
	16	* This is configured using the PDC_WDT_CONFIG register, according to this
	17	* formula:
	18	*
	19	* timeout = 2^(delay + 1) clock cycles
	20	*
	21	* Where 'delay' is the value written in PDC_WDT_CONFIG register.
	22	*
	23	* Therefore, the hardware only allows to program watchdog timeouts, expressed
	24	* as a power of two number of watchdog clock cycles. The current implementation
	25	* guarantees that the actual watchdog timeout will be _at least_ the value
	26	* programmed in the imgpdg_wdt driver.
	27	*
	28	* The following table shows how the user-configured timeout relates
	29	* to the actual hardware timeout (watchdog clock @ 40000 Hz):
	30	*
	31	* input timeout \| WD_DELAY \| actual timeout
	32	* -----------------------------------
	33	* 10 \| 18 \| 13 seconds
	34	* 20 \| 19 \| 26 seconds
	35	* 30 \| 20 \| 52 seconds
	36	* 60 \| 21 \| 104 seconds
	37	*
	38	* Albeit coarse, this granularity would suffice most watchdog uses.
	39	* If the platform allows it, the user should be able to change the watchdog
	40	* clock rate and achieve a finer timeout granularity.
93937669 NT	41	*/
	42
	43	#include <linux/clk.h>
	44	#include <linux/io.h>
	45	#include <linux/log2.h>
	46	#include <linux/module.h>
ac316725	47	#include <linux/mod_devicetable.h>
93937669 NT	48	#include <linux/platform_device.h>
	49	#include <linux/slab.h>
	50	#include <linux/watchdog.h>
	51
	52	/* registers */
	53	#define PDC_WDT_SOFT_RESET 0x00
	54	#define PDC_WDT_CONFIG 0x04
	55	#define PDC_WDT_CONFIG_ENABLE BIT(31)
	56	#define PDC_WDT_CONFIG_DELAY_MASK 0x1f
	57
	58	#define PDC_WDT_TICKLE1 0x08
	59	#define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
	60	#define PDC_WDT_TICKLE2 0x0c
	61	#define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
	62
	63	#define PDC_WDT_TICKLE_STATUS_MASK 0x7
	64	#define PDC_WDT_TICKLE_STATUS_SHIFT 0
	65	#define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
	66	#define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */
	67	#define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */
	68	#define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
	69	#define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
	70
	71	/* Timeout values are in seconds */
	72	#define PDC_WDT_MIN_TIMEOUT 1
	73	#define PDC_WDT_DEF_TIMEOUT 64
	74
7094e1dd	75	static int heartbeat;
93937669	76	module_param(heartbeat, int, 0);
ae6ee2fd JH	77	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds "
ae6ee2fd JH	78	"(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT) ")");
93937669 NT	79
	80	static bool nowayout = WATCHDOG_NOWAYOUT;
	81	module_param(nowayout, bool, 0);
	82	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	83	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	84
	85	struct pdc_wdt_dev {
	86	struct watchdog_device wdt_dev;
	87	struct clk *wdt_clk;
	88	struct clk *sys_clk;
	89	void __iomem *base;
	90	};
	91
	92	static int pdc_wdt_keepalive(struct watchdog_device *wdt_dev)
	93	{
	94	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
	95
	96	writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);
	97	writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);
	98
	99	return 0;
	100	}
	101
	102	static int pdc_wdt_stop(struct watchdog_device *wdt_dev)
	103	{
	104	unsigned int val;
	105	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
	106
	107	val = readl(wdt->base + PDC_WDT_CONFIG);
	108	val &= ~PDC_WDT_CONFIG_ENABLE;
	109	writel(val, wdt->base + PDC_WDT_CONFIG);
	110
	111	/* Must tickle to finish the stop */
	112	pdc_wdt_keepalive(wdt_dev);
	113
	114	return 0;
	115	}
	116
8aa453a5 AB	117	static void __pdc_wdt_set_timeout(struct pdc_wdt_dev *wdt)
	118	{
	119	unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);
	120	unsigned int val;
	121
	122	val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;
	123	val \|= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;
	124	writel(val, wdt->base + PDC_WDT_CONFIG);
	125	}
	126
93937669 NT	127	static int pdc_wdt_set_timeout(struct watchdog_device *wdt_dev,
	128	unsigned int new_timeout)
	129	{
93937669	130	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
93937669 NT	131
	132	wdt->wdt_dev.timeout = new_timeout;
	133
8aa453a5	134	__pdc_wdt_set_timeout(wdt);
93937669 NT	135
	136	return 0;
	137	}
	138
	139	/* Start the watchdog timer (delay should already be set) */
	140	static int pdc_wdt_start(struct watchdog_device *wdt_dev)
	141	{
	142	unsigned int val;
	143	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
	144
8aa453a5 AB	145	__pdc_wdt_set_timeout(wdt);
8aa453a5 AB	146
93937669 NT	147	val = readl(wdt->base + PDC_WDT_CONFIG);
	148	val \|= PDC_WDT_CONFIG_ENABLE;
	149	writel(val, wdt->base + PDC_WDT_CONFIG);
	150
	151	return 0;
	152	}
	153
4d8b229d GR	154	static int pdc_wdt_restart(struct watchdog_device *wdt_dev,
4d8b229d GR	155	unsigned long action, void *data)
0f10d9c5 DR	156	{
	157	struct pdc_wdt_dev *wdt = watchdog_get_drvdata(wdt_dev);
	158
	159	/* Assert SOFT_RESET */
	160	writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);
	161
	162	return 0;
	163	}
	164
6c368932	165	static const struct watchdog_info pdc_wdt_info = {
93937669 NT	166	.identity = "IMG PDC Watchdog",
	167	.options = WDIOF_SETTIMEOUT \|
	168	WDIOF_KEEPALIVEPING \|
	169	WDIOF_MAGICCLOSE,
	170	};
	171
	172	static const struct watchdog_ops pdc_wdt_ops = {
	173	.owner = THIS_MODULE,
	174	.start = pdc_wdt_start,
	175	.stop = pdc_wdt_stop,
	176	.ping = pdc_wdt_keepalive,
	177	.set_timeout = pdc_wdt_set_timeout,
0f10d9c5	178	.restart = pdc_wdt_restart,
93937669 NT	179	};
	180
	181	static int pdc_wdt_probe(struct platform_device *pdev)
	182	{
deb8d50e	183	u64 div;
93937669 NT	184	int ret, val;
93937669 NT	185	unsigned long clk_rate;
93937669 NT	186	struct pdc_wdt_dev *pdc_wdt;
	187
	188	pdc_wdt = devm_kzalloc(&pdev->dev, sizeof(*pdc_wdt), GFP_KERNEL);
	189	if (!pdc_wdt)
	190	return -ENOMEM;
	191
0f0a6a28	192	pdc_wdt->base = devm_platform_ioremap_resource(pdev, 0);
93937669 NT	193	if (IS_ERR(pdc_wdt->base))
	194	return PTR_ERR(pdc_wdt->base);
	195
	196	pdc_wdt->sys_clk = devm_clk_get(&pdev->dev, "sys");
	197	if (IS_ERR(pdc_wdt->sys_clk)) {
	198	dev_err(&pdev->dev, "failed to get the sys clock\n");
	199	return PTR_ERR(pdc_wdt->sys_clk);
	200	}
	201
	202	pdc_wdt->wdt_clk = devm_clk_get(&pdev->dev, "wdt");
	203	if (IS_ERR(pdc_wdt->wdt_clk)) {
	204	dev_err(&pdev->dev, "failed to get the wdt clock\n");
	205	return PTR_ERR(pdc_wdt->wdt_clk);
	206	}
	207
	208	ret = clk_prepare_enable(pdc_wdt->sys_clk);
	209	if (ret) {
	210	dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
	211	return ret;
	212	}
	213
	214	ret = clk_prepare_enable(pdc_wdt->wdt_clk);
	215	if (ret) {
	216	dev_err(&pdev->dev, "could not prepare or enable wdt clock\n");
	217	goto disable_sys_clk;
	218	}
	219
	220	/* We use the clock rate to calculate the max timeout */
	221	clk_rate = clk_get_rate(pdc_wdt->wdt_clk);
	222	if (clk_rate == 0) {
	223	dev_err(&pdev->dev, "failed to get clock rate\n");
	224	ret = -EINVAL;
	225	goto disable_wdt_clk;
	226	}
	227
	228	if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) {
	229	dev_err(&pdev->dev, "invalid clock rate\n");
	230	ret = -EINVAL;
	231	goto disable_wdt_clk;
	232	}
	233
	234	if (order_base_2(clk_rate) == 0)
	235	pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;
	236	else
	237	pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;
	238
	239	pdc_wdt->wdt_dev.info = &pdc_wdt_info;
	240	pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;
deb8d50e EG	241
	242	div = 1ULL << (PDC_WDT_CONFIG_DELAY_MASK + 1);
	243	do_div(div, clk_rate);
	244	pdc_wdt->wdt_dev.max_timeout = div;
7094e1dd	245	pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;
93937669	246	pdc_wdt->wdt_dev.parent = &pdev->dev;
a629c08f	247	watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);
93937669	248
7094e1dd	249	watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, &pdev->dev);
93937669 NT	250
	251	pdc_wdt_stop(&pdc_wdt->wdt_dev);
	252
	253	/* Find what caused the last reset */
	254	val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);
	255	val = (val & PDC_WDT_TICKLE_STATUS_MASK) >> PDC_WDT_TICKLE_STATUS_SHIFT;
	256	switch (val) {
	257	case PDC_WDT_TICKLE_STATUS_TICKLE:
	258	case PDC_WDT_TICKLE_STATUS_TIMEOUT:
	259	pdc_wdt->wdt_dev.bootstatus \|= WDIOF_CARDRESET;
	260	dev_info(&pdev->dev,
	261	"watchdog module last reset due to timeout\n");
	262	break;
	263	case PDC_WDT_TICKLE_STATUS_HRESET:
	264	dev_info(&pdev->dev,
	265	"watchdog module last reset due to hard reset\n");
	266	break;
	267	case PDC_WDT_TICKLE_STATUS_SRESET:
	268	dev_info(&pdev->dev,
	269	"watchdog module last reset due to soft reset\n");
	270	break;
	271	case PDC_WDT_TICKLE_STATUS_USER:
	272	dev_info(&pdev->dev,
	273	"watchdog module last reset due to user reset\n");
	274	break;
	275	default:
	276	dev_info(&pdev->dev,
	277	"contains an illegal status code (%08x)\n", val);
	278	break;
	279	}
	280
	281	watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);
0f10d9c5	282	watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128);
93937669 NT	283
93937669 NT	284	platform_set_drvdata(pdev, pdc_wdt);
93937669 NT	285
	286	ret = watchdog_register_device(&pdc_wdt->wdt_dev);
	287	if (ret)
	288	goto disable_wdt_clk;
	289
	290	return 0;
	291
	292	disable_wdt_clk:
	293	clk_disable_unprepare(pdc_wdt->wdt_clk);
	294	disable_sys_clk:
	295	clk_disable_unprepare(pdc_wdt->sys_clk);
	296	return ret;
	297	}
	298
	299	static void pdc_wdt_shutdown(struct platform_device *pdev)
	300	{
	301	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
	302
	303	pdc_wdt_stop(&pdc_wdt->wdt_dev);
	304	}
	305
	306	static int pdc_wdt_remove(struct platform_device *pdev)
	307	{
	308	struct pdc_wdt_dev *pdc_wdt = platform_get_drvdata(pdev);
	309
	310	pdc_wdt_stop(&pdc_wdt->wdt_dev);
	311	watchdog_unregister_device(&pdc_wdt->wdt_dev);
	312	clk_disable_unprepare(pdc_wdt->wdt_clk);
	313	clk_disable_unprepare(pdc_wdt->sys_clk);
	314
	315	return 0;
	316	}
	317
	318	static const struct of_device_id pdc_wdt_match[] = {
	319	{ .compatible = "img,pdc-wdt" },
	320	{}
	321	};
	322	MODULE_DEVICE_TABLE(of, pdc_wdt_match);
	323
	324	static struct platform_driver pdc_wdt_driver = {
	325	.driver = {
	326	.name = "imgpdc-wdt",
	327	.of_match_table = pdc_wdt_match,
	328	},
	329	.probe = pdc_wdt_probe,
	330	.remove = pdc_wdt_remove,
	331	.shutdown = pdc_wdt_shutdown,
	332	};
	333	module_platform_driver(pdc_wdt_driver);
	334
	335	MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
	336	MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
	337	MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
	338	MODULE_LICENSE("GPL v2");