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Commit | Line | Data |
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bb2fd8a8 WS |
1 | /* |
2 | * Watchdog driver for IMX2 and later processors | |
3 | * | |
4 | * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de> | |
1a9c5efa | 5 | * Copyright (C) 2014 Freescale Semiconductor, Inc. |
bb2fd8a8 WS |
6 | * |
7 | * some parts adapted by similar drivers from Darius Augulis and Vladimir | |
8 | * Zapolskiy, additional improvements by Wim Van Sebroeck. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * NOTE: MX1 has a slightly different Watchdog than MX2 and later: | |
15 | * | |
16 | * MX1: MX2+: | |
17 | * ---- ----- | |
18 | * Registers: 32-bit 16-bit | |
19 | * Stopable timer: Yes No | |
20 | * Need to enable clk: No Yes | |
21 | * Halt on suspend: Manual Can be automatic | |
22 | */ | |
23 | ||
30cb042a | 24 | #include <linux/clk.h> |
334a9d81 | 25 | #include <linux/delay.h> |
bb2fd8a8 | 26 | #include <linux/init.h> |
39487f66 | 27 | #include <linux/interrupt.h> |
30cb042a | 28 | #include <linux/io.h> |
bb2fd8a8 | 29 | #include <linux/kernel.h> |
bb2fd8a8 WS |
30 | #include <linux/module.h> |
31 | #include <linux/moduleparam.h> | |
f728f4bf | 32 | #include <linux/of_address.h> |
bb2fd8a8 | 33 | #include <linux/platform_device.h> |
a7977003 | 34 | #include <linux/regmap.h> |
30cb042a | 35 | #include <linux/watchdog.h> |
bb2fd8a8 WS |
36 | |
37 | #define DRIVER_NAME "imx2-wdt" | |
38 | ||
39 | #define IMX2_WDT_WCR 0x00 /* Control Register */ | |
40 | #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */ | |
68d4cb80 VZ |
41 | #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ |
42 | #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ | |
43 | #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */ | |
44 | #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */ | |
45 | #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */ | |
bb2fd8a8 WS |
46 | |
47 | #define IMX2_WDT_WSR 0x02 /* Service Register */ | |
48 | #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */ | |
49 | #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */ | |
50 | ||
474ef121 | 51 | #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */ |
68d4cb80 | 52 | #define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */ |
474ef121 | 53 | |
39487f66 VZ |
54 | #define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */ |
55 | #define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */ | |
56 | #define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */ | |
57 | #define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */ | |
58 | ||
5fe65ce7 MP |
59 | #define IMX2_WDT_WMCR 0x08 /* Misc Register */ |
60 | ||
bb2fd8a8 WS |
61 | #define IMX2_WDT_MAX_TIME 128 |
62 | #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */ | |
63 | ||
64 | #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8) | |
65 | ||
faad5de0 | 66 | struct imx2_wdt_device { |
bb2fd8a8 | 67 | struct clk *clk; |
a7977003 | 68 | struct regmap *regmap; |
faad5de0 | 69 | struct watchdog_device wdog; |
bc677ff4 | 70 | bool ext_reset; |
faad5de0 | 71 | }; |
bb2fd8a8 | 72 | |
86a1e189 WVS |
73 | static bool nowayout = WATCHDOG_NOWAYOUT; |
74 | module_param(nowayout, bool, 0); | |
bb2fd8a8 WS |
75 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
76 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
77 | ||
78 | ||
79 | static unsigned timeout = IMX2_WDT_DEFAULT_TIME; | |
80 | module_param(timeout, uint, 0); | |
81 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" | |
82 | __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); | |
83 | ||
84 | static const struct watchdog_info imx2_wdt_info = { | |
85 | .identity = "imx2+ watchdog", | |
86 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, | |
87 | }; | |
88 | ||
39487f66 VZ |
89 | static const struct watchdog_info imx2_wdt_pretimeout_info = { |
90 | .identity = "imx2+ watchdog", | |
91 | .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | | |
92 | WDIOF_PRETIMEOUT, | |
93 | }; | |
94 | ||
4d8b229d GR |
95 | static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action, |
96 | void *data) | |
334a9d81 | 97 | { |
2d9d2475 | 98 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
334a9d81 | 99 | unsigned int wcr_enable = IMX2_WDT_WCR_WDE; |
2d9d2475 | 100 | |
bc677ff4 TH |
101 | /* Use internal reset or external - not both */ |
102 | if (wdev->ext_reset) | |
103 | wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */ | |
104 | else | |
105 | wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */ | |
106 | ||
334a9d81 | 107 | /* Assert SRS signal */ |
9493c0d8 | 108 | regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); |
334a9d81 JL |
109 | /* |
110 | * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be | |
111 | * written twice), we add another two writes to ensure there must be at | |
112 | * least two writes happen in the same one 32kHz clock period. We save | |
113 | * the target check here, since the writes shouldn't be a huge burden | |
114 | * for other platforms. | |
115 | */ | |
9493c0d8 FE |
116 | regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); |
117 | regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable); | |
334a9d81 JL |
118 | |
119 | /* wait for reset to assert... */ | |
120 | mdelay(500); | |
121 | ||
2d9d2475 | 122 | return 0; |
334a9d81 JL |
123 | } |
124 | ||
faad5de0 | 125 | static inline void imx2_wdt_setup(struct watchdog_device *wdog) |
bb2fd8a8 | 126 | { |
faad5de0 | 127 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
a7977003 XL |
128 | u32 val; |
129 | ||
faad5de0 | 130 | regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); |
bb2fd8a8 | 131 | |
1a9c5efa AH |
132 | /* Suspend timer in low power mode, write once-only */ |
133 | val |= IMX2_WDT_WCR_WDZST; | |
bb2fd8a8 WS |
134 | /* Strip the old watchdog Time-Out value */ |
135 | val &= ~IMX2_WDT_WCR_WT; | |
bc677ff4 TH |
136 | /* Generate internal chip-level reset if WDOG times out */ |
137 | if (!wdev->ext_reset) | |
138 | val &= ~IMX2_WDT_WCR_WRE; | |
139 | /* Or if external-reset assert WDOG_B reset only on time-out */ | |
140 | else | |
141 | val |= IMX2_WDT_WCR_WRE; | |
bb2fd8a8 WS |
142 | /* Keep Watchdog Disabled */ |
143 | val &= ~IMX2_WDT_WCR_WDE; | |
144 | /* Set the watchdog's Time-Out value */ | |
faad5de0 | 145 | val |= WDOG_SEC_TO_COUNT(wdog->timeout); |
bb2fd8a8 | 146 | |
faad5de0 | 147 | regmap_write(wdev->regmap, IMX2_WDT_WCR, val); |
bb2fd8a8 WS |
148 | |
149 | /* enable the watchdog */ | |
150 | val |= IMX2_WDT_WCR_WDE; | |
faad5de0 | 151 | regmap_write(wdev->regmap, IMX2_WDT_WCR, val); |
bb2fd8a8 WS |
152 | } |
153 | ||
faad5de0 | 154 | static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev) |
bb2fd8a8 | 155 | { |
faad5de0 | 156 | u32 val; |
bb2fd8a8 | 157 | |
faad5de0 AG |
158 | regmap_read(wdev->regmap, IMX2_WDT_WCR, &val); |
159 | ||
160 | return val & IMX2_WDT_WCR_WDE; | |
bb2fd8a8 WS |
161 | } |
162 | ||
faad5de0 | 163 | static int imx2_wdt_ping(struct watchdog_device *wdog) |
bb2fd8a8 | 164 | { |
faad5de0 | 165 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
bb2fd8a8 | 166 | |
faad5de0 AG |
167 | regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1); |
168 | regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2); | |
169 | return 0; | |
bb2fd8a8 WS |
170 | } |
171 | ||
faad5de0 AG |
172 | static int imx2_wdt_set_timeout(struct watchdog_device *wdog, |
173 | unsigned int new_timeout) | |
bb2fd8a8 | 174 | { |
faad5de0 AG |
175 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
176 | ||
30dd4a8f MG |
177 | wdog->timeout = new_timeout; |
178 | ||
faad5de0 | 179 | regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT, |
a7977003 | 180 | WDOG_SEC_TO_COUNT(new_timeout)); |
faad5de0 | 181 | return 0; |
bb2fd8a8 WS |
182 | } |
183 | ||
39487f66 VZ |
184 | static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog, |
185 | unsigned int new_pretimeout) | |
186 | { | |
187 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
188 | ||
189 | if (new_pretimeout >= IMX2_WDT_MAX_TIME) | |
190 | return -EINVAL; | |
191 | ||
192 | wdog->pretimeout = new_pretimeout; | |
193 | ||
194 | regmap_update_bits(wdev->regmap, IMX2_WDT_WICR, | |
195 | IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT, | |
196 | IMX2_WDT_WICR_WIE | (new_pretimeout << 1)); | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg) | |
201 | { | |
202 | struct watchdog_device *wdog = wdog_arg; | |
203 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
204 | ||
205 | regmap_write_bits(wdev->regmap, IMX2_WDT_WICR, | |
206 | IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS); | |
207 | ||
208 | watchdog_notify_pretimeout(wdog); | |
209 | ||
210 | return IRQ_HANDLED; | |
211 | } | |
212 | ||
faad5de0 | 213 | static int imx2_wdt_start(struct watchdog_device *wdog) |
bb2fd8a8 | 214 | { |
faad5de0 | 215 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); |
bb2fd8a8 | 216 | |
11d7aba9 | 217 | if (imx2_wdt_is_running(wdev)) |
faad5de0 | 218 | imx2_wdt_set_timeout(wdog, wdog->timeout); |
11d7aba9 | 219 | else |
faad5de0 AG |
220 | imx2_wdt_setup(wdog); |
221 | ||
11d7aba9 | 222 | set_bit(WDOG_HW_RUNNING, &wdog->status); |
bb2fd8a8 | 223 | |
11d7aba9 | 224 | return imx2_wdt_ping(wdog); |
bb2fd8a8 WS |
225 | } |
226 | ||
4bd8ce33 | 227 | static const struct watchdog_ops imx2_wdt_ops = { |
bb2fd8a8 | 228 | .owner = THIS_MODULE, |
faad5de0 | 229 | .start = imx2_wdt_start, |
faad5de0 AG |
230 | .ping = imx2_wdt_ping, |
231 | .set_timeout = imx2_wdt_set_timeout, | |
39487f66 | 232 | .set_pretimeout = imx2_wdt_set_pretimeout, |
2d9d2475 | 233 | .restart = imx2_wdt_restart, |
bb2fd8a8 WS |
234 | }; |
235 | ||
4bd8ce33 | 236 | static const struct regmap_config imx2_wdt_regmap_config = { |
a7977003 XL |
237 | .reg_bits = 16, |
238 | .reg_stride = 2, | |
239 | .val_bits = 16, | |
240 | .max_register = 0x8, | |
241 | }; | |
242 | ||
bb2fd8a8 WS |
243 | static int __init imx2_wdt_probe(struct platform_device *pdev) |
244 | { | |
faad5de0 AG |
245 | struct imx2_wdt_device *wdev; |
246 | struct watchdog_device *wdog; | |
bb2fd8a8 | 247 | struct resource *res; |
a7977003 XL |
248 | void __iomem *base; |
249 | int ret; | |
faad5de0 AG |
250 | u32 val; |
251 | ||
252 | wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL); | |
253 | if (!wdev) | |
254 | return -ENOMEM; | |
bb2fd8a8 WS |
255 | |
256 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a7977003 XL |
257 | base = devm_ioremap_resource(&pdev->dev, res); |
258 | if (IS_ERR(base)) | |
259 | return PTR_ERR(base); | |
260 | ||
faad5de0 AG |
261 | wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base, |
262 | &imx2_wdt_regmap_config); | |
263 | if (IS_ERR(wdev->regmap)) { | |
a7977003 | 264 | dev_err(&pdev->dev, "regmap init failed\n"); |
faad5de0 | 265 | return PTR_ERR(wdev->regmap); |
a7977003 | 266 | } |
bb2fd8a8 | 267 | |
faad5de0 AG |
268 | wdev->clk = devm_clk_get(&pdev->dev, NULL); |
269 | if (IS_ERR(wdev->clk)) { | |
bb2fd8a8 | 270 | dev_err(&pdev->dev, "can't get Watchdog clock\n"); |
faad5de0 | 271 | return PTR_ERR(wdev->clk); |
bb2fd8a8 WS |
272 | } |
273 | ||
faad5de0 AG |
274 | wdog = &wdev->wdog; |
275 | wdog->info = &imx2_wdt_info; | |
276 | wdog->ops = &imx2_wdt_ops; | |
277 | wdog->min_timeout = 1; | |
11d7aba9 | 278 | wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000; |
8135193c | 279 | wdog->parent = &pdev->dev; |
bb2fd8a8 | 280 | |
39487f66 VZ |
281 | ret = platform_get_irq(pdev, 0); |
282 | if (ret > 0) | |
283 | if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0, | |
284 | dev_name(&pdev->dev), wdog)) | |
285 | wdog->info = &imx2_wdt_pretimeout_info; | |
286 | ||
aefb163c FE |
287 | ret = clk_prepare_enable(wdev->clk); |
288 | if (ret) | |
289 | return ret; | |
bb2fd8a8 | 290 | |
faad5de0 AG |
291 | regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val); |
292 | wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0; | |
bb2fd8a8 | 293 | |
bc677ff4 TH |
294 | wdev->ext_reset = of_property_read_bool(pdev->dev.of_node, |
295 | "fsl,ext-reset-output"); | |
faad5de0 AG |
296 | wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME); |
297 | if (wdog->timeout != timeout) | |
298 | dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n", | |
299 | timeout, wdog->timeout); | |
300 | ||
301 | platform_set_drvdata(pdev, wdog); | |
302 | watchdog_set_drvdata(wdog, wdev); | |
303 | watchdog_set_nowayout(wdog, nowayout); | |
2d9d2475 | 304 | watchdog_set_restart_priority(wdog, 128); |
faad5de0 AG |
305 | watchdog_init_timeout(wdog, timeout, &pdev->dev); |
306 | ||
11d7aba9 GR |
307 | if (imx2_wdt_is_running(wdev)) { |
308 | imx2_wdt_set_timeout(wdog, wdog->timeout); | |
309 | set_bit(WDOG_HW_RUNNING, &wdog->status); | |
310 | } | |
faad5de0 | 311 | |
5fe65ce7 MP |
312 | /* |
313 | * Disable the watchdog power down counter at boot. Otherwise the power | |
314 | * down counter will pull down the #WDOG interrupt line for one clock | |
315 | * cycle. | |
316 | */ | |
317 | regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0); | |
318 | ||
faad5de0 AG |
319 | ret = watchdog_register_device(wdog); |
320 | if (ret) { | |
321 | dev_err(&pdev->dev, "cannot register watchdog device\n"); | |
db11cba2 | 322 | goto disable_clk; |
faad5de0 AG |
323 | } |
324 | ||
325 | dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n", | |
326 | wdog->timeout, nowayout); | |
327 | ||
328 | return 0; | |
db11cba2 FE |
329 | |
330 | disable_clk: | |
331 | clk_disable_unprepare(wdev->clk); | |
332 | return ret; | |
bb2fd8a8 WS |
333 | } |
334 | ||
335 | static int __exit imx2_wdt_remove(struct platform_device *pdev) | |
336 | { | |
faad5de0 AG |
337 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
338 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
bb2fd8a8 | 339 | |
faad5de0 | 340 | watchdog_unregister_device(wdog); |
bb2fd8a8 | 341 | |
faad5de0 | 342 | if (imx2_wdt_is_running(wdev)) { |
faad5de0 AG |
343 | imx2_wdt_ping(wdog); |
344 | dev_crit(&pdev->dev, "Device removed: Expect reboot!\n"); | |
bdf49574 | 345 | } |
bb2fd8a8 WS |
346 | return 0; |
347 | } | |
348 | ||
349 | static void imx2_wdt_shutdown(struct platform_device *pdev) | |
350 | { | |
faad5de0 AG |
351 | struct watchdog_device *wdog = platform_get_drvdata(pdev); |
352 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
353 | ||
354 | if (imx2_wdt_is_running(wdev)) { | |
355 | /* | |
11d7aba9 GR |
356 | * We are running, configure max timeout before reboot |
357 | * will take place. | |
faad5de0 | 358 | */ |
faad5de0 AG |
359 | imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); |
360 | imx2_wdt_ping(wdog); | |
361 | dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n"); | |
bb2fd8a8 WS |
362 | } |
363 | } | |
364 | ||
aefbaf3a | 365 | #ifdef CONFIG_PM_SLEEP |
bbd59009 | 366 | /* Disable watchdog if it is active or non-active but still running */ |
aefbaf3a XL |
367 | static int imx2_wdt_suspend(struct device *dev) |
368 | { | |
369 | struct watchdog_device *wdog = dev_get_drvdata(dev); | |
370 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
371 | ||
bbd59009 XL |
372 | /* The watchdog IP block is running */ |
373 | if (imx2_wdt_is_running(wdev)) { | |
374 | imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); | |
375 | imx2_wdt_ping(wdog); | |
bbd59009 | 376 | } |
aefbaf3a XL |
377 | |
378 | clk_disable_unprepare(wdev->clk); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | /* Enable watchdog and configure it if necessary */ | |
384 | static int imx2_wdt_resume(struct device *dev) | |
385 | { | |
386 | struct watchdog_device *wdog = dev_get_drvdata(dev); | |
387 | struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog); | |
aefb163c | 388 | int ret; |
aefbaf3a | 389 | |
aefb163c FE |
390 | ret = clk_prepare_enable(wdev->clk); |
391 | if (ret) | |
392 | return ret; | |
aefbaf3a XL |
393 | |
394 | if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) { | |
bbd59009 XL |
395 | /* |
396 | * If the watchdog is still active and resumes | |
397 | * from deep sleep state, need to restart the | |
398 | * watchdog again. | |
aefbaf3a XL |
399 | */ |
400 | imx2_wdt_setup(wdog); | |
11d7aba9 GR |
401 | } |
402 | if (imx2_wdt_is_running(wdev)) { | |
aefbaf3a XL |
403 | imx2_wdt_set_timeout(wdog, wdog->timeout); |
404 | imx2_wdt_ping(wdog); | |
aefbaf3a XL |
405 | } |
406 | ||
407 | return 0; | |
408 | } | |
409 | #endif | |
410 | ||
411 | static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend, | |
412 | imx2_wdt_resume); | |
413 | ||
f5a427ee SG |
414 | static const struct of_device_id imx2_wdt_dt_ids[] = { |
415 | { .compatible = "fsl,imx21-wdt", }, | |
416 | { /* sentinel */ } | |
417 | }; | |
813296a1 | 418 | MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids); |
f5a427ee | 419 | |
bb2fd8a8 | 420 | static struct platform_driver imx2_wdt_driver = { |
bb2fd8a8 WS |
421 | .remove = __exit_p(imx2_wdt_remove), |
422 | .shutdown = imx2_wdt_shutdown, | |
423 | .driver = { | |
424 | .name = DRIVER_NAME, | |
aefbaf3a | 425 | .pm = &imx2_wdt_pm_ops, |
f5a427ee | 426 | .of_match_table = imx2_wdt_dt_ids, |
bb2fd8a8 WS |
427 | }, |
428 | }; | |
429 | ||
1cb9204c | 430 | module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe); |
bb2fd8a8 WS |
431 | |
432 | MODULE_AUTHOR("Wolfram Sang"); | |
433 | MODULE_DESCRIPTION("Watchdog driver for IMX2 and later"); | |
434 | MODULE_LICENSE("GPL v2"); | |
bb2fd8a8 | 435 | MODULE_ALIAS("platform:" DRIVER_NAME); |