[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / imx2_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WDA	BIT(5)		/* -> External Reset WDOG_B */
#define IMX2_WDT_WCR_SRS	BIT(4)		/* -> Software Reset Signal */
#define IMX2_WDT_WCR_WRE	BIT(3)		/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	BIT(2)		/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	BIT(0)		/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	BIT(1)		/* -> Reset due to Timeout */

#define IMX2_WDT_WICR		0x06		/* Interrupt Control Register */
#define IMX2_WDT_WICR_WIE	BIT(15)		/* -> Interrupt Enable */
#define IMX2_WDT_WICR_WTIS	BIT(14)		/* -> Interrupt Status */
#define IMX2_WDT_WICR_WICT	0xFF		/* -> Interrupt Count Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128U
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct watchdog_device wdog;
	bool ext_reset;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timeout;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static const struct watchdog_info imx2_wdt_pretimeout_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
		   WDIOF_PRETIMEOUT,
};

static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
			    void *data)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;

	/* Use internal reset or external - not both */
	if (wdev->ext_reset)
		wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	else
		wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */

	/* Assert SRS signal */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return 0;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate internal chip-level reset if WDOG times out */
	if (!wdev->ext_reset)
		val &= ~IMX2_WDT_WCR_WRE;
	/* Or if external-reset assert WDOG_B reset only on time-out */
	else
		val |= IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
				   unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	unsigned int actual;

	actual = min(new_timeout, IMX2_WDT_MAX_TIME);
	__imx2_wdt_set_timeout(wdog, actual);
	wdog->timeout = new_timeout;
	return 0;
}

static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
				   unsigned int new_pretimeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (new_pretimeout >= IMX2_WDT_MAX_TIME)
		return -EINVAL;

	wdog->pretimeout = new_pretimeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
			   IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
			   IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
	return 0;
}

static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
{
	struct watchdog_device *wdog = wdog_arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
			  IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);

	watchdog_notify_pretimeout(wdog);

	return IRQ_HANDLED;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev))
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	else
		imx2_wdt_setup(wdog);

	set_bit(WDOG_HW_RUNNING, &wdog->status);

	return imx2_wdt_ping(wdog);
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
	.set_pretimeout = imx2_wdt_set_pretimeout,
	.restart = imx2_wdt_restart,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static void imx2_wdt_action(void *data)
{
	clk_disable_unprepare(data);
}

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->timeout		= IMX2_WDT_DEFAULT_TIME;
	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
	wdog->parent		= dev;

	ret = platform_get_irq(pdev, 0);
	if (ret > 0)
		if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
				      dev_name(dev), wdog))
			wdog->info = &imx2_wdt_pretimeout_info;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
	if (ret)
		return ret;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdev->ext_reset = of_property_read_bool(dev->of_node,
						"fsl,ext-reset-output");
	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_set_restart_priority(wdog, 128);
	watchdog_init_timeout(wdog, timeout, dev);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		set_bit(WDOG_HW_RUNNING, &wdog->status);
	}

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	return devm_watchdog_register_device(dev, wdog);
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, configure max timeout before reboot
		 * will take place.
		 */
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

/* Disable watchdog if it is active or non-active but still running */
static int __maybe_unused imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		/*
		 * Don't update wdog->timeout, we'll restore the current value
		 * during resume.
		 */
		__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int __maybe_unused imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
	}
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	}

	return 0;
}

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
cd6100fc	1	// SPDX-License-Identifier: GPL-2.0
bb2fd8a8 WS	2	/*
	3	* Watchdog driver for IMX2 and later processors
	4	*
62c35b44	5	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
1a9c5efa	6	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	7	*
	8	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	9	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	10	*
bb2fd8a8 WS	11	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	12	*
	13	* MX1: MX2+:
	14	* ---- -----
	15	* Registers: 32-bit 16-bit
	16	* Stopable timer: Yes No
	17	* Need to enable clk: No Yes
	18	* Halt on suspend: Manual Can be automatic
	19	*/
	20
30cb042a	21	#include <linux/clk.h>
334a9d81	22	#include <linux/delay.h>
bb2fd8a8	23	#include <linux/init.h>
39487f66	24	#include <linux/interrupt.h>
30cb042a	25	#include <linux/io.h>
bb2fd8a8	26	#include <linux/kernel.h>
bb2fd8a8 WS	27	#include <linux/module.h>
bb2fd8a8 WS	28	#include <linux/moduleparam.h>
f728f4bf	29	#include <linux/of_address.h>
bb2fd8a8	30	#include <linux/platform_device.h>
a7977003	31	#include <linux/regmap.h>
30cb042a	32	#include <linux/watchdog.h>
bb2fd8a8 WS	33
	34	#define DRIVER_NAME "imx2-wdt"
	35
	36	#define IMX2_WDT_WCR 0x00 /* Control Register */
	37	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
68d4cb80 VZ	38	#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
	39	#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
	40	#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
	41	#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
	42	#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	43
	44	#define IMX2_WDT_WSR 0x02 /* Service Register */
	45	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	46	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	47
474ef121	48	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
68d4cb80	49	#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
474ef121	50
39487f66 VZ	51	#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
	52	#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
	53	#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
	54	#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
	55
5fe65ce7 MP	56	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MP	57
144783a8	58	#define IMX2_WDT_MAX_TIME 128U
bb2fd8a8 WS	59	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	60
	61	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	62
faad5de0	63	struct imx2_wdt_device {
bb2fd8a8	64	struct clk *clk;
a7977003	65	struct regmap *regmap;
faad5de0	66	struct watchdog_device wdog;
bc677ff4	67	bool ext_reset;
faad5de0	68	};
bb2fd8a8	69
86a1e189 WVS	70	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	71	module_param(nowayout, bool, 0);
bb2fd8a8 WS	72	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	73	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	74
2b77f008	75	static unsigned timeout;
bb2fd8a8 WS	76	module_param(timeout, uint, 0);
	77	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	78	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	79
	80	static const struct watchdog_info imx2_wdt_info = {
	81	.identity = "imx2+ watchdog",
	82	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	83	};
	84
39487f66 VZ	85	static const struct watchdog_info imx2_wdt_pretimeout_info = {
	86	.identity = "imx2+ watchdog",
	87	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \|
	88	WDIOF_PRETIMEOUT,
	89	};
	90
4d8b229d GR	91	static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
4d8b229d GR	92	void *data)
334a9d81	93	{
2d9d2475	94	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334a9d81	95	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
2d9d2475	96
bc677ff4 TH	97	/* Use internal reset or external - not both */
	98	if (wdev->ext_reset)
	99	wcr_enable \|= IMX2_WDT_WCR_SRS; /* do not assert int reset */
	100	else
	101	wcr_enable \|= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
	102
334a9d81	103	/* Assert SRS signal */
9493c0d8	104	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	105	/*
	106	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	107	* written twice), we add another two writes to ensure there must be at
	108	* least two writes happen in the same one 32kHz clock period. We save
	109	* the target check here, since the writes shouldn't be a huge burden
	110	* for other platforms.
	111	*/
9493c0d8 FE	112	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
9493c0d8 FE	113	regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
334a9d81 JL	114
	115	/* wait for reset to assert... */
	116	mdelay(500);
	117
2d9d2475	118	return 0;
334a9d81 JL	119	}
334a9d81 JL	120
faad5de0	121	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	122	{
faad5de0	123	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	124	u32 val;
a7977003 XL	125
faad5de0	126	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	127
1a9c5efa AH	128	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	129	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	130	/* Strip the old watchdog Time-Out value */
bb2fd8a8 WS	131	val &= ~IMX2_WDT_WCR_WT;
bc677ff4 TH	132	/* Generate internal chip-level reset if WDOG times out */
	133	if (!wdev->ext_reset)
	134	val &= ~IMX2_WDT_WCR_WRE;
	135	/* Or if external-reset assert WDOG_B reset only on time-out */
	136	else
	137	val \|= IMX2_WDT_WCR_WRE;
bb2fd8a8 WS	138	/* Keep Watchdog Disabled */
	139	val &= ~IMX2_WDT_WCR_WDE;
	140	/* Set the watchdog's Time-Out value */
faad5de0	141	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	142
faad5de0	143	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	144
	145	/* enable the watchdog */
	146	val \|= IMX2_WDT_WCR_WDE;
faad5de0	147	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	148	}
bb2fd8a8 WS	149
faad5de0	150	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	151	{
faad5de0	152	u32 val;
bb2fd8a8	153
faad5de0 AG	154	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	155
	156	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	157	}
bb2fd8a8 WS	158
faad5de0	159	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	160	{
faad5de0	161	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	162
faad5de0 AG	163	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	164	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	165	return 0;
bb2fd8a8 WS	166	}
bb2fd8a8 WS	167
0be26725 MK	168	static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
0be26725 MK	169	unsigned int new_timeout)
bb2fd8a8	170	{
faad5de0 AG	171	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	172
	173	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	174	WDOG_SEC_TO_COUNT(new_timeout));
0be26725 MK	175	}
	176
	177	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
	178	unsigned int new_timeout)
	179	{
b07e228e	180	unsigned int actual;
0be26725	181
144783a8	182	actual = min(new_timeout, IMX2_WDT_MAX_TIME);
b07e228e	183	__imx2_wdt_set_timeout(wdog, actual);
0be26725	184	wdog->timeout = new_timeout;
faad5de0	185	return 0;
bb2fd8a8 WS	186	}
bb2fd8a8 WS	187
39487f66 VZ	188	static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
	189	unsigned int new_pretimeout)
	190	{
	191	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	192
	193	if (new_pretimeout >= IMX2_WDT_MAX_TIME)
	194	return -EINVAL;
	195
	196	wdog->pretimeout = new_pretimeout;
	197
	198	regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
	199	IMX2_WDT_WICR_WIE \| IMX2_WDT_WICR_WICT,
	200	IMX2_WDT_WICR_WIE \| (new_pretimeout << 1));
	201	return 0;
	202	}
	203
	204	static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
	205	{
	206	struct watchdog_device *wdog = wdog_arg;
	207	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	208
	209	regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
	210	IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
	211
	212	watchdog_notify_pretimeout(wdog);
	213
	214	return IRQ_HANDLED;
	215	}
	216
faad5de0	217	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	218	{
faad5de0	219	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	220
11d7aba9	221	if (imx2_wdt_is_running(wdev))
faad5de0	222	imx2_wdt_set_timeout(wdog, wdog->timeout);
11d7aba9	223	else
faad5de0 AG	224	imx2_wdt_setup(wdog);
faad5de0 AG	225
11d7aba9	226	set_bit(WDOG_HW_RUNNING, &wdog->status);
bb2fd8a8	227
11d7aba9	228	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	229	}
bb2fd8a8 WS	230
4bd8ce33	231	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	232	.owner = THIS_MODULE,
faad5de0	233	.start = imx2_wdt_start,
faad5de0 AG	234	.ping = imx2_wdt_ping,
faad5de0 AG	235	.set_timeout = imx2_wdt_set_timeout,
39487f66	236	.set_pretimeout = imx2_wdt_set_pretimeout,
2d9d2475	237	.restart = imx2_wdt_restart,
bb2fd8a8 WS	238	};
bb2fd8a8 WS	239
4bd8ce33	240	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	241	.reg_bits = 16,
	242	.reg_stride = 2,
	243	.val_bits = 16,
	244	.max_register = 0x8,
	245	};
	246
436867b6 AH	247	static void imx2_wdt_action(void *data)
	248	{
	249	clk_disable_unprepare(data);
	250	}
	251
bb2fd8a8 WS	252	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	253	{
86865322	254	struct device *dev = &pdev->dev;
faad5de0 AG	255	struct imx2_wdt_device *wdev;
faad5de0 AG	256	struct watchdog_device *wdog;
a7977003 XL	257	void __iomem *base;
a7977003 XL	258	int ret;
faad5de0 AG	259	u32 val;
faad5de0 AG	260
86865322	261	wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
faad5de0 AG	262	if (!wdev)
faad5de0 AG	263	return -ENOMEM;
bb2fd8a8	264
24b82256	265	base = devm_platform_ioremap_resource(pdev, 0);
a7977003 XL	266	if (IS_ERR(base))
	267	return PTR_ERR(base);
	268
86865322	269	wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
faad5de0 AG	270	&imx2_wdt_regmap_config);
faad5de0 AG	271	if (IS_ERR(wdev->regmap)) {
86865322	272	dev_err(dev, "regmap init failed\n");
faad5de0	273	return PTR_ERR(wdev->regmap);
a7977003	274	}
bb2fd8a8	275
86865322	276	wdev->clk = devm_clk_get(dev, NULL);
faad5de0	277	if (IS_ERR(wdev->clk)) {
86865322	278	dev_err(dev, "can't get Watchdog clock\n");
faad5de0	279	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	280	}
bb2fd8a8 WS	281
faad5de0 AG	282	wdog = &wdev->wdog;
	283	wdog->info = &imx2_wdt_info;
	284	wdog->ops = &imx2_wdt_ops;
	285	wdog->min_timeout = 1;
2b77f008	286	wdog->timeout = IMX2_WDT_DEFAULT_TIME;
11d7aba9	287	wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
86865322	288	wdog->parent = dev;
bb2fd8a8	289
39487f66 VZ	290	ret = platform_get_irq(pdev, 0);
39487f66 VZ	291	if (ret > 0)
86865322 AH	292	if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
86865322 AH	293	dev_name(dev), wdog))
39487f66 VZ	294	wdog->info = &imx2_wdt_pretimeout_info;
39487f66 VZ	295
aefb163c FE	296	ret = clk_prepare_enable(wdev->clk);
	297	if (ret)
	298	return ret;
bb2fd8a8	299
436867b6 AH	300	ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
	301	if (ret)
	302	return ret;
	303
faad5de0 AG	304	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	305	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	306
86865322	307	wdev->ext_reset = of_property_read_bool(dev->of_node,
bc677ff4	308	"fsl,ext-reset-output");
faad5de0 AG	309	platform_set_drvdata(pdev, wdog);
	310	watchdog_set_drvdata(wdog, wdev);
	311	watchdog_set_nowayout(wdog, nowayout);
2d9d2475	312	watchdog_set_restart_priority(wdog, 128);
86865322	313	watchdog_init_timeout(wdog, timeout, dev);
faad5de0	314
11d7aba9 GR	315	if (imx2_wdt_is_running(wdev)) {
	316	imx2_wdt_set_timeout(wdog, wdog->timeout);
	317	set_bit(WDOG_HW_RUNNING, &wdog->status);
	318	}
faad5de0	319
5fe65ce7 MP	320	/*
	321	* Disable the watchdog power down counter at boot. Otherwise the power
	322	* down counter will pull down the #WDOG interrupt line for one clock
	323	* cycle.
	324	*/
	325	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	326
436867b6	327	return devm_watchdog_register_device(dev, wdog);
bb2fd8a8 WS	328	}
	329
	330	static void imx2_wdt_shutdown(struct platform_device *pdev)
	331	{
faad5de0 AG	332	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	333	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	334
	335	if (imx2_wdt_is_running(wdev)) {
	336	/*
11d7aba9 GR	337	* We are running, configure max timeout before reboot
11d7aba9 GR	338	* will take place.
faad5de0	339	*/
faad5de0 AG	340	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	341	imx2_wdt_ping(wdog);
	342	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	343	}
	344	}
	345
bbd59009	346	/* Disable watchdog if it is active or non-active but still running */
ebe66ded	347	static int __maybe_unused imx2_wdt_suspend(struct device *dev)
aefbaf3a XL	348	{
	349	struct watchdog_device *wdog = dev_get_drvdata(dev);
	350	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	351
bbd59009 XL	352	/* The watchdog IP block is running */
bbd59009 XL	353	if (imx2_wdt_is_running(wdev)) {
0be26725 MK	354	/*
	355	* Don't update wdog->timeout, we'll restore the current value
	356	* during resume.
	357	*/
	358	__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
bbd59009	359	imx2_wdt_ping(wdog);
bbd59009	360	}
aefbaf3a XL	361
	362	clk_disable_unprepare(wdev->clk);
	363
	364	return 0;
	365	}
	366
	367	/* Enable watchdog and configure it if necessary */
ebe66ded	368	static int __maybe_unused imx2_wdt_resume(struct device *dev)
aefbaf3a XL	369	{
	370	struct watchdog_device *wdog = dev_get_drvdata(dev);
	371	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	372	int ret;
aefbaf3a	373
aefb163c FE	374	ret = clk_prepare_enable(wdev->clk);
	375	if (ret)
	376	return ret;
aefbaf3a XL	377
aefbaf3a XL	378	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	379	/*
	380	* If the watchdog is still active and resumes
	381	* from deep sleep state, need to restart the
	382	* watchdog again.
aefbaf3a XL	383	*/
aefbaf3a XL	384	imx2_wdt_setup(wdog);
11d7aba9 GR	385	}
11d7aba9 GR	386	if (imx2_wdt_is_running(wdev)) {
aefbaf3a XL	387	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a XL	388	imx2_wdt_ping(wdog);
aefbaf3a XL	389	}
	390
	391	return 0;
	392	}
aefbaf3a XL	393
	394	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	395	imx2_wdt_resume);
	396
f5a427ee SG	397	static const struct of_device_id imx2_wdt_dt_ids[] = {
	398	{ .compatible = "fsl,imx21-wdt", },
	399	{ /* sentinel */ }
	400	};
813296a1	401	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	402
bb2fd8a8	403	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	404	.shutdown = imx2_wdt_shutdown,
	405	.driver = {
	406	.name = DRIVER_NAME,
aefbaf3a	407	.pm = &imx2_wdt_pm_ops,
f5a427ee	408	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	409	},
	410	};
	411
1cb9204c	412	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	413
	414	MODULE_AUTHOR("Wolfram Sang");
	415	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	416	MODULE_LICENSE("GPL v2");
bb2fd8a8	417	MODULE_ALIAS("platform:" DRIVER_NAME);