[mirror_ubuntu-artful-kernel.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct timer_list timer;	/* Pings the watchdog when closed */
	struct watchdog_device wdog;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate reset if WDOG times out */
	val &= ~IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void imx2_wdt_timer_ping(unsigned long arg)
{
	struct watchdog_device *wdog = (struct watchdog_device *)arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	imx2_wdt_ping(wdog);
	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/* delete the timer that pings the watchdog after close */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	} else
		imx2_wdt_setup(wdog);

	return imx2_wdt_ping(wdog);
}

static int imx2_wdt_stop(struct watchdog_device *wdog)
{
	/*
	 * We don't need a clk_disable, it cannot be disabled once started.
	 * We use a timer to ping the watchdog while /dev/watchdog is closed
	 */
	imx2_wdt_timer_ping((unsigned long)wdog);
	return 0;
}

static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_timer_ping((unsigned long)wdog);
	}
}

static struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.stop = imx2_wdt_stop,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
};

static struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_timeout	= IMX2_WDT_MAX_TIME;

	clk_prepare_enable(wdev->clk);

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);

	imx2_wdt_ping_if_active(wdog);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		return ret;
	}

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		del_timer_sync(&wdev->timer);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, we need to delete the timer but will
		 * give max timeout before reboot will take place
		 */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
bb2fd8a8	25	#include <linux/init.h>
30cb042a XL	26	#include <linux/io.h>
30cb042a XL	27	#include <linux/jiffies.h>
bb2fd8a8	28	#include <linux/kernel.h>
bb2fd8a8 WS	29	#include <linux/module.h>
bb2fd8a8 WS	30	#include <linux/moduleparam.h>
f728f4bf	31	#include <linux/of_address.h>
bb2fd8a8	32	#include <linux/platform_device.h>
a7977003	33	#include <linux/regmap.h>
bb2fd8a8	34	#include <linux/timer.h>
30cb042a	35	#include <linux/watchdog.h>
bb2fd8a8 WS	36
	37	#define DRIVER_NAME "imx2-wdt"
	38
	39	#define IMX2_WDT_WCR 0x00 /* Control Register */
	40	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
	41	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
	42	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	43	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	44
	45	#define IMX2_WDT_WSR 0x02 /* Service Register */
	46	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	47	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	48
474ef121 OS	49	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	50	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	51
bb2fd8a8 WS	52	#define IMX2_WDT_MAX_TIME 128
	53	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	54
	55	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	56
faad5de0	57	struct imx2_wdt_device {
bb2fd8a8	58	struct clk *clk;
a7977003	59	struct regmap *regmap;
bb2fd8a8	60	struct timer_list timer; /* Pings the watchdog when closed */
faad5de0 AG	61	struct watchdog_device wdog;
faad5de0 AG	62	};
bb2fd8a8	63
86a1e189 WVS	64	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	65	module_param(nowayout, bool, 0);
bb2fd8a8 WS	66	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	67	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	68
	69
	70	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	71	module_param(timeout, uint, 0);
	72	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	73	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	74
	75	static const struct watchdog_info imx2_wdt_info = {
	76	.identity = "imx2+ watchdog",
	77	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	78	};
	79
faad5de0	80	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	81	{
faad5de0	82	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	83	u32 val;
a7977003 XL	84
faad5de0	85	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	86
1a9c5efa AH	87	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	88	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	89	/* Strip the old watchdog Time-Out value */
	90	val &= ~IMX2_WDT_WCR_WT;
	91	/* Generate reset if WDOG times out */
	92	val &= ~IMX2_WDT_WCR_WRE;
	93	/* Keep Watchdog Disabled */
	94	val &= ~IMX2_WDT_WCR_WDE;
	95	/* Set the watchdog's Time-Out value */
faad5de0	96	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	97
faad5de0	98	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	99
	100	/* enable the watchdog */
	101	val \|= IMX2_WDT_WCR_WDE;
faad5de0	102	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	103	}
bb2fd8a8 WS	104
faad5de0	105	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	106	{
faad5de0	107	u32 val;
bb2fd8a8	108
faad5de0 AG	109	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	110
	111	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	112	}
bb2fd8a8 WS	113
faad5de0	114	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	115	{
faad5de0	116	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	117
faad5de0 AG	118	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	119	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	120	return 0;
bb2fd8a8 WS	121	}
bb2fd8a8 WS	122
faad5de0	123	static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8	124	{
faad5de0 AG	125	struct watchdog_device wdog = (struct watchdog_device )arg;
	126	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	127
	128	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	129	imx2_wdt_ping(wdog);
	130	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8 WS	131	}
bb2fd8a8 WS	132
faad5de0 AG	133	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	134	unsigned int new_timeout)
bb2fd8a8	135	{
faad5de0 AG	136	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	137
	138	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	139	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	140	return 0;
bb2fd8a8 WS	141	}
bb2fd8a8 WS	142
faad5de0	143	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	144	{
faad5de0	145	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	146
faad5de0 AG	147	if (imx2_wdt_is_running(wdev)) {
	148	/* delete the timer that pings the watchdog after close */
	149	del_timer_sync(&wdev->timer);
	150	imx2_wdt_set_timeout(wdog, wdog->timeout);
	151	} else
	152	imx2_wdt_setup(wdog);
	153
	154	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	155	}
bb2fd8a8 WS	156
faad5de0	157	static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8	158	{
faad5de0 AG	159	/*
	160	* We don't need a clk_disable, it cannot be disabled once started.
	161	* We use a timer to ping the watchdog while /dev/watchdog is closed
	162	*/
	163	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	164	return 0;
	165	}
	166
faad5de0	167	static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8	168	{
faad5de0	169	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	170
faad5de0 AG	171	if (imx2_wdt_is_running(wdev)) {
	172	imx2_wdt_set_timeout(wdog, wdog->timeout);
	173	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	174	}
	175	}
	176
faad5de0	177	static struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	178	.owner = THIS_MODULE,
faad5de0 AG	179	.start = imx2_wdt_start,
	180	.stop = imx2_wdt_stop,
	181	.ping = imx2_wdt_ping,
	182	.set_timeout = imx2_wdt_set_timeout,
bb2fd8a8 WS	183	};
bb2fd8a8 WS	184
a7977003 XL	185	static struct regmap_config imx2_wdt_regmap_config = {
	186	.reg_bits = 16,
	187	.reg_stride = 2,
	188	.val_bits = 16,
	189	.max_register = 0x8,
	190	};
	191
bb2fd8a8 WS	192	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	193	{
faad5de0 AG	194	struct imx2_wdt_device *wdev;
faad5de0 AG	195	struct watchdog_device *wdog;
bb2fd8a8	196	struct resource *res;
a7977003 XL	197	void __iomem *base;
a7977003 XL	198	int ret;
faad5de0 AG	199	u32 val;
	200
	201	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	202	if (!wdev)
	203	return -ENOMEM;
bb2fd8a8 WS	204
bb2fd8a8 WS	205	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	206	base = devm_ioremap_resource(&pdev->dev, res);
	207	if (IS_ERR(base))
	208	return PTR_ERR(base);
	209
faad5de0 AG	210	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	211	&imx2_wdt_regmap_config);
	212	if (IS_ERR(wdev->regmap)) {
a7977003	213	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	214	return PTR_ERR(wdev->regmap);
a7977003	215	}
bb2fd8a8	216
faad5de0 AG	217	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	218	if (IS_ERR(wdev->clk)) {
bb2fd8a8	219	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	220	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	221	}
bb2fd8a8 WS	222
faad5de0 AG	223	wdog = &wdev->wdog;
	224	wdog->info = &imx2_wdt_info;
	225	wdog->ops = &imx2_wdt_ops;
	226	wdog->min_timeout = 1;
	227	wdog->max_timeout = IMX2_WDT_MAX_TIME;
bb2fd8a8	228
faad5de0	229	clk_prepare_enable(wdev->clk);
bb2fd8a8	230
faad5de0 AG	231	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	232	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	233
faad5de0 AG	234	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	235	if (wdog->timeout != timeout)
	236	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	237	timeout, wdog->timeout);
	238
	239	platform_set_drvdata(pdev, wdog);
	240	watchdog_set_drvdata(wdog, wdev);
	241	watchdog_set_nowayout(wdog, nowayout);
	242	watchdog_init_timeout(wdog, timeout, &pdev->dev);
	243
	244	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8	245
faad5de0 AG	246	imx2_wdt_ping_if_active(wdog);
	247
	248	ret = watchdog_register_device(wdog);
	249	if (ret) {
	250	dev_err(&pdev->dev, "cannot register watchdog device\n");
	251	return ret;
	252	}
	253
	254	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	255	wdog->timeout, nowayout);
	256
	257	return 0;
bb2fd8a8 WS	258	}
	259
	260	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	261	{
faad5de0 AG	262	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	263	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	264
faad5de0	265	watchdog_unregister_device(wdog);
bb2fd8a8	266
faad5de0 AG	267	if (imx2_wdt_is_running(wdev)) {
	268	del_timer_sync(&wdev->timer);
	269	imx2_wdt_ping(wdog);
	270	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	271	}
bb2fd8a8 WS	272	return 0;
	273	}
	274
	275	static void imx2_wdt_shutdown(struct platform_device *pdev)
	276	{
faad5de0 AG	277	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	278	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	279
	280	if (imx2_wdt_is_running(wdev)) {
	281	/*
	282	* We are running, we need to delete the timer but will
	283	* give max timeout before reboot will take place
	284	*/
	285	del_timer_sync(&wdev->timer);
	286	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	287	imx2_wdt_ping(wdog);
	288	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	289	}
	290	}
	291
f5a427ee SG	292	static const struct of_device_id imx2_wdt_dt_ids[] = {
	293	{ .compatible = "fsl,imx21-wdt", },
	294	{ /* sentinel */ }
	295	};
813296a1	296	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	297
bb2fd8a8	298	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	299	.remove = __exit_p(imx2_wdt_remove),
	300	.shutdown = imx2_wdt_shutdown,
	301	.driver = {
	302	.name = DRIVER_NAME,
	303	.owner = THIS_MODULE,
f5a427ee	304	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	305	},
	306	};
	307
1cb9204c	308	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	309
	310	MODULE_AUTHOR("Wolfram Sang");
	311	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	312	MODULE_LICENSE("GPL v2");
bb2fd8a8	313	MODULE_ALIAS("platform:" DRIVER_NAME);