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bb2fd8a8
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1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa 5 * Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8
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6 *
7 * some parts adapted by similar drivers from Darius Augulis and Vladimir
8 * Zapolskiy, additional improvements by Wim Van Sebroeck.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
15 *
16 * MX1: MX2+:
17 * ---- -----
18 * Registers: 32-bit 16-bit
19 * Stopable timer: Yes No
20 * Need to enable clk: No Yes
21 * Halt on suspend: Manual Can be automatic
22 */
23
30cb042a 24#include <linux/clk.h>
334a9d81 25#include <linux/delay.h>
bb2fd8a8 26#include <linux/init.h>
30cb042a
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27#include <linux/io.h>
28#include <linux/jiffies.h>
bb2fd8a8 29#include <linux/kernel.h>
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30#include <linux/module.h>
31#include <linux/moduleparam.h>
334a9d81 32#include <linux/notifier.h>
f728f4bf 33#include <linux/of_address.h>
bb2fd8a8 34#include <linux/platform_device.h>
334a9d81 35#include <linux/reboot.h>
a7977003 36#include <linux/regmap.h>
bb2fd8a8 37#include <linux/timer.h>
30cb042a 38#include <linux/watchdog.h>
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39
40#define DRIVER_NAME "imx2-wdt"
41
42#define IMX2_WDT_WCR 0x00 /* Control Register */
43#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
44#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
45#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa 46#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
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47
48#define IMX2_WDT_WSR 0x02 /* Service Register */
49#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
50#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
51
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52#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
53#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
54
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55#define IMX2_WDT_MAX_TIME 128
56#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
57
58#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
59
faad5de0 60struct imx2_wdt_device {
bb2fd8a8 61 struct clk *clk;
a7977003 62 struct regmap *regmap;
bb2fd8a8 63 struct timer_list timer; /* Pings the watchdog when closed */
faad5de0 64 struct watchdog_device wdog;
334a9d81 65 struct notifier_block restart_handler;
faad5de0 66};
bb2fd8a8 67
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68static bool nowayout = WATCHDOG_NOWAYOUT;
69module_param(nowayout, bool, 0);
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70MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
71 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
72
73
74static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
75module_param(timeout, uint, 0);
76MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
77 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
78
79static const struct watchdog_info imx2_wdt_info = {
80 .identity = "imx2+ watchdog",
81 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
82};
83
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84static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
85 void *cmd)
86{
87 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
88 struct imx2_wdt_device *wdev = container_of(this,
89 struct imx2_wdt_device,
90 restart_handler);
91 /* Assert SRS signal */
92 regmap_write(wdev->regmap, 0, wcr_enable);
93 /*
94 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
95 * written twice), we add another two writes to ensure there must be at
96 * least two writes happen in the same one 32kHz clock period. We save
97 * the target check here, since the writes shouldn't be a huge burden
98 * for other platforms.
99 */
100 regmap_write(wdev->regmap, 0, wcr_enable);
101 regmap_write(wdev->regmap, 0, wcr_enable);
102
103 /* wait for reset to assert... */
104 mdelay(500);
105
106 return NOTIFY_DONE;
107}
108
faad5de0 109static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8 110{
faad5de0 111 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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112 u32 val;
113
faad5de0 114 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8 115
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116 /* Suspend timer in low power mode, write once-only */
117 val |= IMX2_WDT_WCR_WDZST;
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118 /* Strip the old watchdog Time-Out value */
119 val &= ~IMX2_WDT_WCR_WT;
120 /* Generate reset if WDOG times out */
121 val &= ~IMX2_WDT_WCR_WRE;
122 /* Keep Watchdog Disabled */
123 val &= ~IMX2_WDT_WCR_WDE;
124 /* Set the watchdog's Time-Out value */
faad5de0 125 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8 126
faad5de0 127 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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128
129 /* enable the watchdog */
130 val |= IMX2_WDT_WCR_WDE;
faad5de0 131 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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132}
133
faad5de0 134static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8 135{
faad5de0 136 u32 val;
bb2fd8a8 137
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138 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
139
140 return val & IMX2_WDT_WCR_WDE;
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141}
142
faad5de0 143static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8 144{
faad5de0 145 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 146
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147 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
148 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
149 return 0;
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150}
151
faad5de0 152static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8 153{
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154 struct watchdog_device *wdog = (struct watchdog_device *)arg;
155 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
156
157 /* ping it every wdog->timeout / 2 seconds to prevent reboot */
158 imx2_wdt_ping(wdog);
159 mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
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160}
161
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162static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
163 unsigned int new_timeout)
bb2fd8a8 164{
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165 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
166
167 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003 168 WDOG_SEC_TO_COUNT(new_timeout));
faad5de0 169 return 0;
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170}
171
faad5de0 172static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8 173{
faad5de0 174 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 175
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176 if (imx2_wdt_is_running(wdev)) {
177 /* delete the timer that pings the watchdog after close */
178 del_timer_sync(&wdev->timer);
179 imx2_wdt_set_timeout(wdog, wdog->timeout);
180 } else
181 imx2_wdt_setup(wdog);
182
183 return imx2_wdt_ping(wdog);
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184}
185
faad5de0 186static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8 187{
faad5de0
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188 /*
189 * We don't need a clk_disable, it cannot be disabled once started.
190 * We use a timer to ping the watchdog while /dev/watchdog is closed
191 */
192 imx2_wdt_timer_ping((unsigned long)wdog);
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193 return 0;
194}
195
faad5de0 196static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8 197{
faad5de0 198 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 199
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200 if (imx2_wdt_is_running(wdev)) {
201 imx2_wdt_set_timeout(wdog, wdog->timeout);
202 imx2_wdt_timer_ping((unsigned long)wdog);
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203 }
204}
205
faad5de0 206static struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8 207 .owner = THIS_MODULE,
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208 .start = imx2_wdt_start,
209 .stop = imx2_wdt_stop,
210 .ping = imx2_wdt_ping,
211 .set_timeout = imx2_wdt_set_timeout,
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212};
213
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214static struct regmap_config imx2_wdt_regmap_config = {
215 .reg_bits = 16,
216 .reg_stride = 2,
217 .val_bits = 16,
218 .max_register = 0x8,
219};
220
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221static int __init imx2_wdt_probe(struct platform_device *pdev)
222{
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223 struct imx2_wdt_device *wdev;
224 struct watchdog_device *wdog;
bb2fd8a8 225 struct resource *res;
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226 void __iomem *base;
227 int ret;
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228 u32 val;
229
230 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
231 if (!wdev)
232 return -ENOMEM;
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233
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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235 base = devm_ioremap_resource(&pdev->dev, res);
236 if (IS_ERR(base))
237 return PTR_ERR(base);
238
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239 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
240 &imx2_wdt_regmap_config);
241 if (IS_ERR(wdev->regmap)) {
a7977003 242 dev_err(&pdev->dev, "regmap init failed\n");
faad5de0 243 return PTR_ERR(wdev->regmap);
a7977003 244 }
bb2fd8a8 245
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246 wdev->clk = devm_clk_get(&pdev->dev, NULL);
247 if (IS_ERR(wdev->clk)) {
bb2fd8a8 248 dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0 249 return PTR_ERR(wdev->clk);
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250 }
251
faad5de0
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252 wdog = &wdev->wdog;
253 wdog->info = &imx2_wdt_info;
254 wdog->ops = &imx2_wdt_ops;
255 wdog->min_timeout = 1;
256 wdog->max_timeout = IMX2_WDT_MAX_TIME;
bb2fd8a8 257
faad5de0 258 clk_prepare_enable(wdev->clk);
bb2fd8a8 259
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260 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
261 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8 262
faad5de0
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263 wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
264 if (wdog->timeout != timeout)
265 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
266 timeout, wdog->timeout);
267
268 platform_set_drvdata(pdev, wdog);
269 watchdog_set_drvdata(wdog, wdev);
270 watchdog_set_nowayout(wdog, nowayout);
271 watchdog_init_timeout(wdog, timeout, &pdev->dev);
272
273 setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8 274
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275 imx2_wdt_ping_if_active(wdog);
276
277 ret = watchdog_register_device(wdog);
278 if (ret) {
279 dev_err(&pdev->dev, "cannot register watchdog device\n");
280 return ret;
281 }
282
334a9d81
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283 wdev->restart_handler.notifier_call = imx2_restart_handler;
284 wdev->restart_handler.priority = 128;
285 ret = register_restart_handler(&wdev->restart_handler);
286 if (ret)
287 dev_err(&pdev->dev, "cannot register restart handler\n");
288
faad5de0
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289 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
290 wdog->timeout, nowayout);
291
292 return 0;
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293}
294
295static int __exit imx2_wdt_remove(struct platform_device *pdev)
296{
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297 struct watchdog_device *wdog = platform_get_drvdata(pdev);
298 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 299
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300 unregister_restart_handler(&wdev->restart_handler);
301
faad5de0 302 watchdog_unregister_device(wdog);
bb2fd8a8 303
faad5de0
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304 if (imx2_wdt_is_running(wdev)) {
305 del_timer_sync(&wdev->timer);
306 imx2_wdt_ping(wdog);
307 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574 308 }
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309 return 0;
310}
311
312static void imx2_wdt_shutdown(struct platform_device *pdev)
313{
faad5de0
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314 struct watchdog_device *wdog = platform_get_drvdata(pdev);
315 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
316
317 if (imx2_wdt_is_running(wdev)) {
318 /*
319 * We are running, we need to delete the timer but will
320 * give max timeout before reboot will take place
321 */
322 del_timer_sync(&wdev->timer);
323 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
324 imx2_wdt_ping(wdog);
325 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8
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326 }
327}
328
f5a427ee
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329static const struct of_device_id imx2_wdt_dt_ids[] = {
330 { .compatible = "fsl,imx21-wdt", },
331 { /* sentinel */ }
332};
813296a1 333MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee 334
bb2fd8a8 335static struct platform_driver imx2_wdt_driver = {
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336 .remove = __exit_p(imx2_wdt_remove),
337 .shutdown = imx2_wdt_shutdown,
338 .driver = {
339 .name = DRIVER_NAME,
f5a427ee 340 .of_match_table = imx2_wdt_dt_ids,
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341 },
342};
343
1cb9204c 344module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
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345
346MODULE_AUTHOR("Wolfram Sang");
347MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
348MODULE_LICENSE("GPL v2");
bb2fd8a8 349MODULE_ALIAS("platform:" DRIVER_NAME);