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CommitLineData
bb2fd8a8
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1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa 5 * Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8
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6 *
7 * some parts adapted by similar drivers from Darius Augulis and Vladimir
8 * Zapolskiy, additional improvements by Wim Van Sebroeck.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
15 *
16 * MX1: MX2+:
17 * ---- -----
18 * Registers: 32-bit 16-bit
19 * Stopable timer: Yes No
20 * Need to enable clk: No Yes
21 * Halt on suspend: Manual Can be automatic
22 */
23
30cb042a 24#include <linux/clk.h>
334a9d81 25#include <linux/delay.h>
bb2fd8a8 26#include <linux/init.h>
30cb042a
XL
27#include <linux/io.h>
28#include <linux/jiffies.h>
bb2fd8a8 29#include <linux/kernel.h>
bb2fd8a8
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30#include <linux/module.h>
31#include <linux/moduleparam.h>
334a9d81 32#include <linux/notifier.h>
f728f4bf 33#include <linux/of_address.h>
bb2fd8a8 34#include <linux/platform_device.h>
334a9d81 35#include <linux/reboot.h>
a7977003 36#include <linux/regmap.h>
bb2fd8a8 37#include <linux/timer.h>
30cb042a 38#include <linux/watchdog.h>
bb2fd8a8
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39
40#define DRIVER_NAME "imx2-wdt"
41
42#define IMX2_WDT_WCR 0x00 /* Control Register */
43#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
44#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
45#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa 46#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
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47
48#define IMX2_WDT_WSR 0x02 /* Service Register */
49#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
50#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
51
474ef121
OS
52#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
53#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
54
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55#define IMX2_WDT_WMCR 0x08 /* Misc Register */
56
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57#define IMX2_WDT_MAX_TIME 128
58#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
59
60#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
61
faad5de0 62struct imx2_wdt_device {
bb2fd8a8 63 struct clk *clk;
a7977003 64 struct regmap *regmap;
bb2fd8a8 65 struct timer_list timer; /* Pings the watchdog when closed */
faad5de0 66 struct watchdog_device wdog;
334a9d81 67 struct notifier_block restart_handler;
faad5de0 68};
bb2fd8a8 69
86a1e189
WVS
70static bool nowayout = WATCHDOG_NOWAYOUT;
71module_param(nowayout, bool, 0);
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72MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75
76static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
77module_param(timeout, uint, 0);
78MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
79 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
80
81static const struct watchdog_info imx2_wdt_info = {
82 .identity = "imx2+ watchdog",
83 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
84};
85
334a9d81
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86static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
87 void *cmd)
88{
89 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
90 struct imx2_wdt_device *wdev = container_of(this,
91 struct imx2_wdt_device,
92 restart_handler);
93 /* Assert SRS signal */
94 regmap_write(wdev->regmap, 0, wcr_enable);
95 /*
96 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
97 * written twice), we add another two writes to ensure there must be at
98 * least two writes happen in the same one 32kHz clock period. We save
99 * the target check here, since the writes shouldn't be a huge burden
100 * for other platforms.
101 */
102 regmap_write(wdev->regmap, 0, wcr_enable);
103 regmap_write(wdev->regmap, 0, wcr_enable);
104
105 /* wait for reset to assert... */
106 mdelay(500);
107
108 return NOTIFY_DONE;
109}
110
faad5de0 111static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8 112{
faad5de0 113 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003
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114 u32 val;
115
faad5de0 116 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8 117
1a9c5efa
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118 /* Suspend timer in low power mode, write once-only */
119 val |= IMX2_WDT_WCR_WDZST;
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120 /* Strip the old watchdog Time-Out value */
121 val &= ~IMX2_WDT_WCR_WT;
122 /* Generate reset if WDOG times out */
123 val &= ~IMX2_WDT_WCR_WRE;
124 /* Keep Watchdog Disabled */
125 val &= ~IMX2_WDT_WCR_WDE;
126 /* Set the watchdog's Time-Out value */
faad5de0 127 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8 128
faad5de0 129 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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130
131 /* enable the watchdog */
132 val |= IMX2_WDT_WCR_WDE;
faad5de0 133 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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134}
135
faad5de0 136static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8 137{
faad5de0 138 u32 val;
bb2fd8a8 139
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140 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
141
142 return val & IMX2_WDT_WCR_WDE;
bb2fd8a8
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143}
144
faad5de0 145static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8 146{
faad5de0 147 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 148
faad5de0
AG
149 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
150 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
151 return 0;
bb2fd8a8
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152}
153
faad5de0 154static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8 155{
faad5de0
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156 struct watchdog_device *wdog = (struct watchdog_device *)arg;
157 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
158
159 /* ping it every wdog->timeout / 2 seconds to prevent reboot */
160 imx2_wdt_ping(wdog);
161 mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8
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162}
163
faad5de0
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164static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
165 unsigned int new_timeout)
bb2fd8a8 166{
faad5de0
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167 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
168
30dd4a8f
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169 wdog->timeout = new_timeout;
170
faad5de0 171 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003 172 WDOG_SEC_TO_COUNT(new_timeout));
faad5de0 173 return 0;
bb2fd8a8
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174}
175
faad5de0 176static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8 177{
faad5de0 178 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 179
faad5de0
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180 if (imx2_wdt_is_running(wdev)) {
181 /* delete the timer that pings the watchdog after close */
182 del_timer_sync(&wdev->timer);
183 imx2_wdt_set_timeout(wdog, wdog->timeout);
184 } else
185 imx2_wdt_setup(wdog);
186
187 return imx2_wdt_ping(wdog);
bb2fd8a8
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188}
189
faad5de0 190static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8 191{
faad5de0
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192 /*
193 * We don't need a clk_disable, it cannot be disabled once started.
194 * We use a timer to ping the watchdog while /dev/watchdog is closed
195 */
196 imx2_wdt_timer_ping((unsigned long)wdog);
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197 return 0;
198}
199
faad5de0 200static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8 201{
faad5de0 202 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 203
faad5de0
AG
204 if (imx2_wdt_is_running(wdev)) {
205 imx2_wdt_set_timeout(wdog, wdog->timeout);
206 imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8
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207 }
208}
209
4bd8ce33 210static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8 211 .owner = THIS_MODULE,
faad5de0
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212 .start = imx2_wdt_start,
213 .stop = imx2_wdt_stop,
214 .ping = imx2_wdt_ping,
215 .set_timeout = imx2_wdt_set_timeout,
bb2fd8a8
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216};
217
4bd8ce33 218static const struct regmap_config imx2_wdt_regmap_config = {
a7977003
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219 .reg_bits = 16,
220 .reg_stride = 2,
221 .val_bits = 16,
222 .max_register = 0x8,
223};
224
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225static int __init imx2_wdt_probe(struct platform_device *pdev)
226{
faad5de0
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227 struct imx2_wdt_device *wdev;
228 struct watchdog_device *wdog;
bb2fd8a8 229 struct resource *res;
a7977003
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230 void __iomem *base;
231 int ret;
faad5de0
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232 u32 val;
233
234 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
235 if (!wdev)
236 return -ENOMEM;
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237
238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003
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239 base = devm_ioremap_resource(&pdev->dev, res);
240 if (IS_ERR(base))
241 return PTR_ERR(base);
242
faad5de0
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243 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
244 &imx2_wdt_regmap_config);
245 if (IS_ERR(wdev->regmap)) {
a7977003 246 dev_err(&pdev->dev, "regmap init failed\n");
faad5de0 247 return PTR_ERR(wdev->regmap);
a7977003 248 }
bb2fd8a8 249
faad5de0
AG
250 wdev->clk = devm_clk_get(&pdev->dev, NULL);
251 if (IS_ERR(wdev->clk)) {
bb2fd8a8 252 dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0 253 return PTR_ERR(wdev->clk);
bb2fd8a8
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254 }
255
faad5de0
AG
256 wdog = &wdev->wdog;
257 wdog->info = &imx2_wdt_info;
258 wdog->ops = &imx2_wdt_ops;
259 wdog->min_timeout = 1;
260 wdog->max_timeout = IMX2_WDT_MAX_TIME;
8135193c 261 wdog->parent = &pdev->dev;
bb2fd8a8 262
faad5de0 263 clk_prepare_enable(wdev->clk);
bb2fd8a8 264
faad5de0
AG
265 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
266 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8 267
faad5de0
AG
268 wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
269 if (wdog->timeout != timeout)
270 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
271 timeout, wdog->timeout);
272
273 platform_set_drvdata(pdev, wdog);
274 watchdog_set_drvdata(wdog, wdev);
275 watchdog_set_nowayout(wdog, nowayout);
276 watchdog_init_timeout(wdog, timeout, &pdev->dev);
277
278 setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8 279
faad5de0
AG
280 imx2_wdt_ping_if_active(wdog);
281
5fe65ce7
MP
282 /*
283 * Disable the watchdog power down counter at boot. Otherwise the power
284 * down counter will pull down the #WDOG interrupt line for one clock
285 * cycle.
286 */
287 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
288
faad5de0
AG
289 ret = watchdog_register_device(wdog);
290 if (ret) {
291 dev_err(&pdev->dev, "cannot register watchdog device\n");
292 return ret;
293 }
294
334a9d81
JL
295 wdev->restart_handler.notifier_call = imx2_restart_handler;
296 wdev->restart_handler.priority = 128;
297 ret = register_restart_handler(&wdev->restart_handler);
298 if (ret)
299 dev_err(&pdev->dev, "cannot register restart handler\n");
300
faad5de0
AG
301 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
302 wdog->timeout, nowayout);
303
304 return 0;
bb2fd8a8
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305}
306
307static int __exit imx2_wdt_remove(struct platform_device *pdev)
308{
faad5de0
AG
309 struct watchdog_device *wdog = platform_get_drvdata(pdev);
310 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8 311
334a9d81
JL
312 unregister_restart_handler(&wdev->restart_handler);
313
faad5de0 314 watchdog_unregister_device(wdog);
bb2fd8a8 315
faad5de0
AG
316 if (imx2_wdt_is_running(wdev)) {
317 del_timer_sync(&wdev->timer);
318 imx2_wdt_ping(wdog);
319 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574 320 }
bb2fd8a8
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321 return 0;
322}
323
324static void imx2_wdt_shutdown(struct platform_device *pdev)
325{
faad5de0
AG
326 struct watchdog_device *wdog = platform_get_drvdata(pdev);
327 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
328
329 if (imx2_wdt_is_running(wdev)) {
330 /*
331 * We are running, we need to delete the timer but will
332 * give max timeout before reboot will take place
333 */
334 del_timer_sync(&wdev->timer);
335 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
336 imx2_wdt_ping(wdog);
337 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8
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338 }
339}
340
aefbaf3a 341#ifdef CONFIG_PM_SLEEP
bbd59009 342/* Disable watchdog if it is active or non-active but still running */
aefbaf3a
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343static int imx2_wdt_suspend(struct device *dev)
344{
345 struct watchdog_device *wdog = dev_get_drvdata(dev);
346 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
347
bbd59009
XL
348 /* The watchdog IP block is running */
349 if (imx2_wdt_is_running(wdev)) {
350 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
351 imx2_wdt_ping(wdog);
aefbaf3a 352
bbd59009
XL
353 /* The watchdog is not active */
354 if (!watchdog_active(wdog))
355 del_timer_sync(&wdev->timer);
356 }
aefbaf3a
XL
357
358 clk_disable_unprepare(wdev->clk);
359
360 return 0;
361}
362
363/* Enable watchdog and configure it if necessary */
364static int imx2_wdt_resume(struct device *dev)
365{
366 struct watchdog_device *wdog = dev_get_drvdata(dev);
367 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
368
369 clk_prepare_enable(wdev->clk);
370
371 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009
XL
372 /*
373 * If the watchdog is still active and resumes
374 * from deep sleep state, need to restart the
375 * watchdog again.
aefbaf3a
XL
376 */
377 imx2_wdt_setup(wdog);
378 imx2_wdt_set_timeout(wdog, wdog->timeout);
379 imx2_wdt_ping(wdog);
380 } else if (imx2_wdt_is_running(wdev)) {
bbd59009
XL
381 /* Resuming from non-deep sleep state. */
382 imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a 383 imx2_wdt_ping(wdog);
bbd59009
XL
384 /*
385 * But the watchdog is not active, then start
386 * the timer again.
387 */
388 if (!watchdog_active(wdog))
389 mod_timer(&wdev->timer,
390 jiffies + wdog->timeout * HZ / 2);
aefbaf3a
XL
391 }
392
393 return 0;
394}
395#endif
396
397static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
398 imx2_wdt_resume);
399
f5a427ee
SG
400static const struct of_device_id imx2_wdt_dt_ids[] = {
401 { .compatible = "fsl,imx21-wdt", },
402 { /* sentinel */ }
403};
813296a1 404MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee 405
bb2fd8a8 406static struct platform_driver imx2_wdt_driver = {
bb2fd8a8
WS
407 .remove = __exit_p(imx2_wdt_remove),
408 .shutdown = imx2_wdt_shutdown,
409 .driver = {
410 .name = DRIVER_NAME,
aefbaf3a 411 .pm = &imx2_wdt_pm_ops,
f5a427ee 412 .of_match_table = imx2_wdt_dt_ids,
bb2fd8a8
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413 },
414};
415
1cb9204c 416module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
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417
418MODULE_AUTHOR("Wolfram Sang");
419MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
420MODULE_LICENSE("GPL v2");
bb2fd8a8 421MODULE_ALIAS("platform:" DRIVER_NAME);