[mirror_ubuntu-jammy-kernel.git] / drivers / watchdog / imx7ulp_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2019 NXP.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/watchdog.h>

#define WDOG_CS			0x0
#define WDOG_CS_CMD32EN		BIT(13)
#define WDOG_CS_ULK		BIT(11)
#define WDOG_CS_RCS		BIT(10)
#define LPO_CLK			0x1
#define LPO_CLK_SHIFT		8
#define WDOG_CS_CLK		(LPO_CLK << LPO_CLK_SHIFT)
#define WDOG_CS_EN		BIT(7)
#define WDOG_CS_UPDATE		BIT(5)

#define WDOG_CNT	0x4
#define WDOG_TOVAL	0x8

#define REFRESH_SEQ0	0xA602
#define REFRESH_SEQ1	0xB480
#define REFRESH		((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)

#define UNLOCK_SEQ0	0xC520
#define UNLOCK_SEQ1	0xD928
#define UNLOCK		((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)

#define DEFAULT_TIMEOUT	60
#define MAX_TIMEOUT	128
#define WDOG_CLOCK_RATE	1000

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0000);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

struct imx7ulp_wdt_device {
	struct watchdog_device wdd;
	void __iomem *base;
	struct clk *clk;
};

static void imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
{
	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);

	u32 val = readl(wdt->base + WDOG_CS);

	writel(UNLOCK, wdt->base + WDOG_CNT);
	if (enable)
		writel(val | WDOG_CS_EN, wdt->base + WDOG_CS);
	else
		writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
}

static bool imx7ulp_wdt_is_enabled(void __iomem *base)
{
	u32 val = readl(base + WDOG_CS);

	return val & WDOG_CS_EN;
}

static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
{
	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);

	writel(REFRESH, wdt->base + WDOG_CNT);

	return 0;
}

static int imx7ulp_wdt_start(struct watchdog_device *wdog)
{

	imx7ulp_wdt_enable(wdog, true);

	return 0;
}

static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
{
	imx7ulp_wdt_enable(wdog, false);

	return 0;
}

static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
				   unsigned int timeout)
{
	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
	u32 val = WDOG_CLOCK_RATE * timeout;

	writel(UNLOCK, wdt->base + WDOG_CNT);
	writel(val, wdt->base + WDOG_TOVAL);

	wdog->timeout = timeout;

	return 0;
}

static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
			       unsigned long action, void *data)
{
	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);

	imx7ulp_wdt_enable(wdog, true);
	imx7ulp_wdt_set_timeout(&wdt->wdd, 1);

	/* wait for wdog to fire */
	while (true)
		;

	return NOTIFY_DONE;
}

static const struct watchdog_ops imx7ulp_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx7ulp_wdt_start,
	.stop  = imx7ulp_wdt_stop,
	.ping  = imx7ulp_wdt_ping,
	.set_timeout = imx7ulp_wdt_set_timeout,
	.restart = imx7ulp_wdt_restart,
};

static const struct watchdog_info imx7ulp_wdt_info = {
	.identity = "i.MX7ULP watchdog timer",
	.options  = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
		    WDIOF_MAGICCLOSE,
};

static void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout)
{
	u32 val;

	/* unlock the wdog for reconfiguration */
	writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
	writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);

	/* set an initial timeout value in TOVAL */
	writel(timeout, base + WDOG_TOVAL);
	/* enable 32bit command sequence and reconfigure */
	val = WDOG_CS_CMD32EN | WDOG_CS_CLK | WDOG_CS_UPDATE;
	writel(val, base + WDOG_CS);
}

static void imx7ulp_wdt_action(void *data)
{
	clk_disable_unprepare(data);
}

static int imx7ulp_wdt_probe(struct platform_device *pdev)
{
	struct imx7ulp_wdt_device *imx7ulp_wdt;
	struct device *dev = &pdev->dev;
	struct watchdog_device *wdog;
	int ret;

	imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
	if (!imx7ulp_wdt)
		return -ENOMEM;

	platform_set_drvdata(pdev, imx7ulp_wdt);

	imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(imx7ulp_wdt->base))
		return PTR_ERR(imx7ulp_wdt->base);

	imx7ulp_wdt->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(imx7ulp_wdt->clk)) {
		dev_err(dev, "Failed to get watchdog clock\n");
		return PTR_ERR(imx7ulp_wdt->clk);
	}

	ret = clk_prepare_enable(imx7ulp_wdt->clk);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk);
	if (ret)
		return ret;

	wdog = &imx7ulp_wdt->wdd;
	wdog->info = &imx7ulp_wdt_info;
	wdog->ops = &imx7ulp_wdt_ops;
	wdog->min_timeout = 1;
	wdog->max_timeout = MAX_TIMEOUT;
	wdog->parent = dev;
	wdog->timeout = DEFAULT_TIMEOUT;

	watchdog_init_timeout(wdog, 0, dev);
	watchdog_stop_on_reboot(wdog);
	watchdog_stop_on_unregister(wdog);
	watchdog_set_drvdata(wdog, imx7ulp_wdt);
	imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE);

	return devm_watchdog_register_device(dev, wdog);
}

static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev)
{
	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);

	if (watchdog_active(&imx7ulp_wdt->wdd))
		imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);

	clk_disable_unprepare(imx7ulp_wdt->clk);

	return 0;
}

static int __maybe_unused imx7ulp_wdt_resume(struct device *dev)
{
	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
	u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
	int ret;

	ret = clk_prepare_enable(imx7ulp_wdt->clk);
	if (ret)
		return ret;

	if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
		imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);

	if (watchdog_active(&imx7ulp_wdt->wdd))
		imx7ulp_wdt_start(&imx7ulp_wdt->wdd);

	return 0;
}

static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend,
			 imx7ulp_wdt_resume);

static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx7ulp-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);

static struct platform_driver imx7ulp_wdt_driver = {
	.probe		= imx7ulp_wdt_probe,
	.driver		= {
		.name	= "imx7ulp-wdt",
		.pm	= &imx7ulp_wdt_pm_ops,
		.of_match_table = imx7ulp_wdt_dt_ids,
	},
};
module_platform_driver(imx7ulp_wdt_driver);

MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
41b630f4 AH	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2019 NXP.
	4	*/
	5
	6	#include <linux/clk.h>
41b630f4 AH	7	#include <linux/io.h>
	8	#include <linux/kernel.h>
	9	#include <linux/module.h>
	10	#include <linux/of.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/reboot.h>
	13	#include <linux/watchdog.h>
	14
	15	#define WDOG_CS 0x0
	16	#define WDOG_CS_CMD32EN BIT(13)
	17	#define WDOG_CS_ULK BIT(11)
	18	#define WDOG_CS_RCS BIT(10)
eccb7fe5 FE	19	#define LPO_CLK 0x1
	20	#define LPO_CLK_SHIFT 8
	21	#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
41b630f4 AH	22	#define WDOG_CS_EN BIT(7)
	23	#define WDOG_CS_UPDATE BIT(5)
	24
	25	#define WDOG_CNT 0x4
	26	#define WDOG_TOVAL 0x8
	27
	28	#define REFRESH_SEQ0 0xA602
	29	#define REFRESH_SEQ1 0xB480
	30	#define REFRESH ((REFRESH_SEQ1 << 16) \| REFRESH_SEQ0)
	31
	32	#define UNLOCK_SEQ0 0xC520
	33	#define UNLOCK_SEQ1 0xD928
	34	#define UNLOCK ((UNLOCK_SEQ1 << 16) \| UNLOCK_SEQ0)
	35
	36	#define DEFAULT_TIMEOUT 60
	37	#define MAX_TIMEOUT 128
	38	#define WDOG_CLOCK_RATE 1000
	39
	40	static bool nowayout = WATCHDOG_NOWAYOUT;
	41	module_param(nowayout, bool, 0000);
	42	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	43	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	44
	45	struct imx7ulp_wdt_device {
41b630f4 AH	46	struct watchdog_device wdd;
	47	void __iomem *base;
	48	struct clk *clk;
	49	};
	50
c37e3581	51	static void imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable)
41b630f4	52	{
747d88a1	53	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
41b630f4	54
747d88a1 FE	55	u32 val = readl(wdt->base + WDOG_CS);
	56
	57	writel(UNLOCK, wdt->base + WDOG_CNT);
41b630f4	58	if (enable)
747d88a1	59	writel(val \| WDOG_CS_EN, wdt->base + WDOG_CS);
41b630f4	60	else
747d88a1	61	writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS);
41b630f4 AH	62	}
41b630f4 AH	63
c37e3581	64	static bool imx7ulp_wdt_is_enabled(void __iomem *base)
41b630f4 AH	65	{
	66	u32 val = readl(base + WDOG_CS);
	67
	68	return val & WDOG_CS_EN;
	69	}
	70
	71	static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
	72	{
	73	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
	74
	75	writel(REFRESH, wdt->base + WDOG_CNT);
	76
	77	return 0;
	78	}
	79
	80	static int imx7ulp_wdt_start(struct watchdog_device *wdog)
	81	{
41b630f4	82
747d88a1	83	imx7ulp_wdt_enable(wdog, true);
41b630f4 AH	84
	85	return 0;
	86	}
	87
	88	static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
	89	{
747d88a1	90	imx7ulp_wdt_enable(wdog, false);
41b630f4 AH	91
	92	return 0;
	93	}
	94
	95	static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
	96	unsigned int timeout)
	97	{
	98	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
	99	u32 val = WDOG_CLOCK_RATE * timeout;
	100
	101	writel(UNLOCK, wdt->base + WDOG_CNT);
	102	writel(val, wdt->base + WDOG_TOVAL);
	103
	104	wdog->timeout = timeout;
	105
	106	return 0;
	107	}
	108
6083ab7b FE	109	static int imx7ulp_wdt_restart(struct watchdog_device *wdog,
	110	unsigned long action, void *data)
	111	{
	112	struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
	113
91ced83c	114	imx7ulp_wdt_enable(wdog, true);
6083ab7b FE	115	imx7ulp_wdt_set_timeout(&wdt->wdd, 1);
	116
	117	/* wait for wdog to fire */
	118	while (true)
	119	;
	120
	121	return NOTIFY_DONE;
	122	}
	123
41b630f4 AH	124	static const struct watchdog_ops imx7ulp_wdt_ops = {
	125	.owner = THIS_MODULE,
	126	.start = imx7ulp_wdt_start,
	127	.stop = imx7ulp_wdt_stop,
	128	.ping = imx7ulp_wdt_ping,
	129	.set_timeout = imx7ulp_wdt_set_timeout,
6083ab7b	130	.restart = imx7ulp_wdt_restart,
41b630f4 AH	131	};
	132
	133	static const struct watchdog_info imx7ulp_wdt_info = {
	134	.identity = "i.MX7ULP watchdog timer",
	135	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
	136	WDIOF_MAGICCLOSE,
	137	};
	138
c37e3581	139	static void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout)
41b630f4 AH	140	{
	141	u32 val;
	142
	143	/* unlock the wdog for reconfiguration */
	144	writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
	145	writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
	146
	147	/* set an initial timeout value in TOVAL */
	148	writel(timeout, base + WDOG_TOVAL);
	149	/* enable 32bit command sequence and reconfigure */
eccb7fe5	150	val = WDOG_CS_CMD32EN \| WDOG_CS_CLK \| WDOG_CS_UPDATE;
41b630f4 AH	151	writel(val, base + WDOG_CS);
	152	}
	153
	154	static void imx7ulp_wdt_action(void *data)
	155	{
	156	clk_disable_unprepare(data);
	157	}
	158
	159	static int imx7ulp_wdt_probe(struct platform_device *pdev)
	160	{
	161	struct imx7ulp_wdt_device *imx7ulp_wdt;
	162	struct device *dev = &pdev->dev;
	163	struct watchdog_device *wdog;
	164	int ret;
	165
	166	imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
	167	if (!imx7ulp_wdt)
	168	return -ENOMEM;
	169
	170	platform_set_drvdata(pdev, imx7ulp_wdt);
	171
	172	imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
	173	if (IS_ERR(imx7ulp_wdt->base))
	174	return PTR_ERR(imx7ulp_wdt->base);
	175
	176	imx7ulp_wdt->clk = devm_clk_get(dev, NULL);
	177	if (IS_ERR(imx7ulp_wdt->clk)) {
	178	dev_err(dev, "Failed to get watchdog clock\n");
	179	return PTR_ERR(imx7ulp_wdt->clk);
	180	}
	181
	182	ret = clk_prepare_enable(imx7ulp_wdt->clk);
	183	if (ret)
	184	return ret;
	185
	186	ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk);
	187	if (ret)
	188	return ret;
	189
	190	wdog = &imx7ulp_wdt->wdd;
	191	wdog->info = &imx7ulp_wdt_info;
	192	wdog->ops = &imx7ulp_wdt_ops;
	193	wdog->min_timeout = 1;
	194	wdog->max_timeout = MAX_TIMEOUT;
	195	wdog->parent = dev;
	196	wdog->timeout = DEFAULT_TIMEOUT;
	197
	198	watchdog_init_timeout(wdog, 0, dev);
	199	watchdog_stop_on_reboot(wdog);
	200	watchdog_stop_on_unregister(wdog);
	201	watchdog_set_drvdata(wdog, imx7ulp_wdt);
	202	imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE);
	203
	204	return devm_watchdog_register_device(dev, wdog);
	205	}
	206
	207	static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev)
	208	{
	209	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
	210
	211	if (watchdog_active(&imx7ulp_wdt->wdd))
	212	imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
	213
	214	clk_disable_unprepare(imx7ulp_wdt->clk);
215
216	return 0;
217	}
218
219	static int __maybe_unused imx7ulp_wdt_resume(struct device *dev)
220	{
221	struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
222	u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
223	int ret;
224
225	ret = clk_prepare_enable(imx7ulp_wdt->clk);
226	if (ret)
227	return ret;
228
229	if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
230	imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
231
232	if (watchdog_active(&imx7ulp_wdt->wdd))
233	imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
234
235	return 0;
236	}
237
238	static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend,
239	imx7ulp_wdt_resume);
240
241	static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
242	{ .compatible = "fsl,imx7ulp-wdt", },
243	{ /* sentinel */ }
244	};
245	MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
246
247	static struct platform_driver imx7ulp_wdt_driver = {
248	.probe = imx7ulp_wdt_probe,
249	.driver = {
250	.name = "imx7ulp-wdt",
251	.pm = &imx7ulp_wdt_pm_ops,
252	.of_match_table = imx7ulp_wdt_dt_ids,
253	},
254	};
255	module_platform_driver(imx7ulp_wdt_driver);
256
257	MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
258	MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
259	MODULE_LICENSE("GPL v2");