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e1fee94f OS |
1 | /* |
2 | * Watchdog Timer Driver | |
3 | * for ITE IT87xx Environment Control - Low Pin Count Input / Output | |
4 | * | |
5 | * (c) Copyright 2007 Oliver Schuster <olivers137@aol.com> | |
6 | * | |
7 | * Based on softdog.c by Alan Cox, | |
8 | * 83977f_wdt.c by Jose Goncalves, | |
9 | * it87.c by Chris Gauthron, Jean Delvare | |
10 | * | |
11 | * Data-sheets: Publicly available at the ITE website | |
12 | * http://www.ite.com.tw/ | |
13 | * | |
14 | * Support of the watchdog timers, which are available on | |
198ca015 DEP |
15 | * IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726 |
16 | * and IT8728. | |
e1fee94f OS |
17 | * |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
31 | */ | |
32 | ||
27c766aa JP |
33 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
34 | ||
e1fee94f OS |
35 | #include <linux/module.h> |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/types.h> | |
38 | #include <linux/kernel.h> | |
39 | #include <linux/fs.h> | |
40 | #include <linux/miscdevice.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/ioport.h> | |
43 | #include <linux/watchdog.h> | |
44 | #include <linux/notifier.h> | |
45 | #include <linux/reboot.h> | |
46 | #include <linux/uaccess.h> | |
47 | #include <linux/io.h> | |
48 | ||
e1fee94f | 49 | |
4bc30272 | 50 | #define WATCHDOG_VERSION "1.14" |
e1fee94f | 51 | #define WATCHDOG_NAME "IT87 WDT" |
e1fee94f OS |
52 | #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" |
53 | #define WD_MAGIC 'V' | |
54 | ||
55 | /* Defaults for Module Parameter */ | |
56 | #define DEFAULT_NOGAMEPORT 0 | |
0bcd0b6a | 57 | #define DEFAULT_NOCIR 0 |
e1fee94f | 58 | #define DEFAULT_EXCLUSIVE 1 |
5f3b2756 | 59 | #define DEFAULT_TIMEOUT 60 |
e1fee94f OS |
60 | #define DEFAULT_TESTMODE 0 |
61 | #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT | |
62 | ||
63 | /* IO Ports */ | |
64 | #define REG 0x2e | |
65 | #define VAL 0x2f | |
66 | ||
67 | /* Logical device Numbers LDN */ | |
68 | #define GPIO 0x07 | |
69 | #define GAMEPORT 0x09 | |
70 | #define CIR 0x0a | |
71 | ||
72 | /* Configuration Registers and Functions */ | |
73 | #define LDNREG 0x07 | |
74 | #define CHIPID 0x20 | |
5f3b2756 | 75 | #define CHIPREV 0x22 |
e1fee94f | 76 | #define ACTREG 0x30 |
5f3b2756 | 77 | #define BASEREG 0x60 |
e1fee94f OS |
78 | |
79 | /* Chip Id numbers */ | |
80 | #define NO_DEV_ID 0xffff | |
dfb0b8ea | 81 | #define IT8702_ID 0x8702 |
e1fee94f OS |
82 | #define IT8705_ID 0x8705 |
83 | #define IT8712_ID 0x8712 | |
84 | #define IT8716_ID 0x8716 | |
85 | #define IT8718_ID 0x8718 | |
ee3e9658 | 86 | #define IT8720_ID 0x8720 |
4bc30272 | 87 | #define IT8721_ID 0x8721 |
e1fee94f | 88 | #define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */ |
198ca015 | 89 | #define IT8728_ID 0x8728 |
e1fee94f OS |
90 | |
91 | /* GPIO Configuration Registers LDN=0x07 */ | |
5f3b2756 | 92 | #define WDTCTRL 0x71 |
e1fee94f OS |
93 | #define WDTCFG 0x72 |
94 | #define WDTVALLSB 0x73 | |
95 | #define WDTVALMSB 0x74 | |
96 | ||
97 | /* GPIO Bits WDTCTRL */ | |
98 | #define WDT_CIRINT 0x80 | |
99 | #define WDT_MOUSEINT 0x40 | |
100 | #define WDT_KYBINT 0x20 | |
198ca015 | 101 | #define WDT_GAMEPORT 0x10 /* not in it8718, it8720, it8721, it8728 */ |
e1fee94f OS |
102 | #define WDT_FORCE 0x02 |
103 | #define WDT_ZERO 0x01 | |
104 | ||
105 | /* GPIO Bits WDTCFG */ | |
106 | #define WDT_TOV1 0x80 | |
107 | #define WDT_KRST 0x40 | |
108 | #define WDT_TOVE 0x20 | |
4bc30272 | 109 | #define WDT_PWROK 0x10 /* not in it8721 */ |
e1fee94f OS |
110 | #define WDT_INT_MASK 0x0f |
111 | ||
112 | /* CIR Configuration Register LDN=0x0a */ | |
5f3b2756 | 113 | #define CIR_ILS 0x70 |
e1fee94f OS |
114 | |
115 | /* The default Base address is not always available, we use this */ | |
116 | #define CIR_BASE 0x0208 | |
117 | ||
118 | /* CIR Controller */ | |
119 | #define CIR_DR(b) (b) | |
120 | #define CIR_IER(b) (b + 1) | |
121 | #define CIR_RCR(b) (b + 2) | |
122 | #define CIR_TCR1(b) (b + 3) | |
123 | #define CIR_TCR2(b) (b + 4) | |
124 | #define CIR_TSR(b) (b + 5) | |
125 | #define CIR_RSR(b) (b + 6) | |
126 | #define CIR_BDLR(b) (b + 5) | |
127 | #define CIR_BDHR(b) (b + 6) | |
128 | #define CIR_IIR(b) (b + 7) | |
129 | ||
130 | /* Default Base address of Game port */ | |
131 | #define GP_BASE_DEFAULT 0x0201 | |
132 | ||
133 | /* wdt_status */ | |
134 | #define WDTS_TIMER_RUN 0 | |
135 | #define WDTS_DEV_OPEN 1 | |
136 | #define WDTS_KEEPALIVE 2 | |
137 | #define WDTS_LOCKED 3 | |
138 | #define WDTS_USE_GP 4 | |
139 | #define WDTS_EXPECTED 5 | |
0bcd0b6a | 140 | #define WDTS_USE_CIR 6 |
e1fee94f | 141 | |
4bc30272 | 142 | static unsigned int base, gpact, ciract, max_units, chip_type; |
e1fee94f | 143 | static unsigned long wdt_status; |
e1fee94f OS |
144 | |
145 | static int nogameport = DEFAULT_NOGAMEPORT; | |
0bcd0b6a | 146 | static int nocir = DEFAULT_NOCIR; |
e1fee94f OS |
147 | static int exclusive = DEFAULT_EXCLUSIVE; |
148 | static int timeout = DEFAULT_TIMEOUT; | |
149 | static int testmode = DEFAULT_TESTMODE; | |
86a1e189 | 150 | static bool nowayout = DEFAULT_NOWAYOUT; |
e1fee94f OS |
151 | |
152 | module_param(nogameport, int, 0); | |
153 | MODULE_PARM_DESC(nogameport, "Forbid the activation of game port, default=" | |
154 | __MODULE_STRING(DEFAULT_NOGAMEPORT)); | |
0bcd0b6a MW |
155 | module_param(nocir, int, 0); |
156 | MODULE_PARM_DESC(nocir, "Forbid the use of Consumer IR interrupts to reset timer, default=" | |
157 | __MODULE_STRING(DEFAULT_NOCIR)); | |
e1fee94f OS |
158 | module_param(exclusive, int, 0); |
159 | MODULE_PARM_DESC(exclusive, "Watchdog exclusive device open, default=" | |
160 | __MODULE_STRING(DEFAULT_EXCLUSIVE)); | |
161 | module_param(timeout, int, 0); | |
162 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default=" | |
163 | __MODULE_STRING(DEFAULT_TIMEOUT)); | |
164 | module_param(testmode, int, 0); | |
165 | MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default=" | |
166 | __MODULE_STRING(DEFAULT_TESTMODE)); | |
86a1e189 | 167 | module_param(nowayout, bool, 0); |
e1fee94f OS |
168 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default=" |
169 | __MODULE_STRING(WATCHDOG_NOWAYOUT)); | |
170 | ||
171 | /* Superio Chip */ | |
172 | ||
a134b825 | 173 | static inline int superio_enter(void) |
e1fee94f | 174 | { |
a134b825 NG |
175 | /* |
176 | * Try to reserve REG and REG + 1 for exclusive access. | |
177 | */ | |
178 | if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) | |
179 | return -EBUSY; | |
180 | ||
e1fee94f OS |
181 | outb(0x87, REG); |
182 | outb(0x01, REG); | |
183 | outb(0x55, REG); | |
184 | outb(0x55, REG); | |
a134b825 | 185 | return 0; |
e1fee94f OS |
186 | } |
187 | ||
188 | static inline void superio_exit(void) | |
189 | { | |
190 | outb(0x02, REG); | |
191 | outb(0x02, VAL); | |
a134b825 | 192 | release_region(REG, 2); |
e1fee94f OS |
193 | } |
194 | ||
195 | static inline void superio_select(int ldn) | |
196 | { | |
197 | outb(LDNREG, REG); | |
198 | outb(ldn, VAL); | |
199 | } | |
200 | ||
201 | static inline int superio_inb(int reg) | |
202 | { | |
203 | outb(reg, REG); | |
204 | return inb(VAL); | |
205 | } | |
206 | ||
207 | static inline void superio_outb(int val, int reg) | |
208 | { | |
143a2e54 WVS |
209 | outb(reg, REG); |
210 | outb(val, VAL); | |
e1fee94f OS |
211 | } |
212 | ||
213 | static inline int superio_inw(int reg) | |
214 | { | |
215 | int val; | |
216 | outb(reg++, REG); | |
217 | val = inb(VAL) << 8; | |
218 | outb(reg, REG); | |
219 | val |= inb(VAL); | |
220 | return val; | |
221 | } | |
222 | ||
223 | static inline void superio_outw(int val, int reg) | |
224 | { | |
143a2e54 WVS |
225 | outb(reg++, REG); |
226 | outb(val >> 8, VAL); | |
227 | outb(reg, REG); | |
228 | outb(val, VAL); | |
e1fee94f OS |
229 | } |
230 | ||
dfb0b8ea OZ |
231 | /* Internal function, should be called after superio_select(GPIO) */ |
232 | static void wdt_update_timeout(void) | |
233 | { | |
4bc30272 | 234 | unsigned char cfg = WDT_KRST; |
dfb0b8ea OZ |
235 | int tm = timeout; |
236 | ||
237 | if (testmode) | |
238 | cfg = 0; | |
239 | ||
240 | if (tm <= max_units) | |
241 | cfg |= WDT_TOV1; | |
242 | else | |
243 | tm /= 60; | |
244 | ||
4bc30272 HT |
245 | if (chip_type != IT8721_ID) |
246 | cfg |= WDT_PWROK; | |
247 | ||
dfb0b8ea OZ |
248 | superio_outb(cfg, WDTCFG); |
249 | superio_outb(tm, WDTVALLSB); | |
250 | if (max_units > 255) | |
251 | superio_outb(tm>>8, WDTVALMSB); | |
252 | } | |
253 | ||
254 | static int wdt_round_time(int t) | |
255 | { | |
256 | t += 59; | |
257 | t -= t % 60; | |
258 | return t; | |
259 | } | |
260 | ||
e1fee94f OS |
261 | /* watchdog timer handling */ |
262 | ||
263 | static void wdt_keepalive(void) | |
264 | { | |
265 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
266 | inb(base); | |
0bcd0b6a | 267 | else if (test_bit(WDTS_USE_CIR, &wdt_status)) |
e1fee94f OS |
268 | /* The timer reloads with around 5 msec delay */ |
269 | outb(0x55, CIR_DR(base)); | |
0bcd0b6a MW |
270 | else { |
271 | if (superio_enter()) | |
272 | return; | |
273 | ||
274 | superio_select(GPIO); | |
275 | wdt_update_timeout(); | |
276 | superio_exit(); | |
277 | } | |
e1fee94f OS |
278 | set_bit(WDTS_KEEPALIVE, &wdt_status); |
279 | } | |
280 | ||
a134b825 | 281 | static int wdt_start(void) |
e1fee94f | 282 | { |
a134b825 NG |
283 | int ret = superio_enter(); |
284 | if (ret) | |
285 | return ret; | |
e1fee94f OS |
286 | |
287 | superio_select(GPIO); | |
288 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
289 | superio_outb(WDT_GAMEPORT, WDTCTRL); | |
0bcd0b6a | 290 | else if (test_bit(WDTS_USE_CIR, &wdt_status)) |
e1fee94f | 291 | superio_outb(WDT_CIRINT, WDTCTRL); |
dfb0b8ea | 292 | wdt_update_timeout(); |
e1fee94f OS |
293 | |
294 | superio_exit(); | |
a134b825 NG |
295 | |
296 | return 0; | |
e1fee94f OS |
297 | } |
298 | ||
a134b825 | 299 | static int wdt_stop(void) |
e1fee94f | 300 | { |
a134b825 NG |
301 | int ret = superio_enter(); |
302 | if (ret) | |
303 | return ret; | |
e1fee94f OS |
304 | |
305 | superio_select(GPIO); | |
306 | superio_outb(0x00, WDTCTRL); | |
307 | superio_outb(WDT_TOV1, WDTCFG); | |
e1fee94f | 308 | superio_outb(0x00, WDTVALLSB); |
dfb0b8ea OZ |
309 | if (max_units > 255) |
310 | superio_outb(0x00, WDTVALMSB); | |
e1fee94f OS |
311 | |
312 | superio_exit(); | |
a134b825 | 313 | return 0; |
e1fee94f OS |
314 | } |
315 | ||
316 | /** | |
317 | * wdt_set_timeout - set a new timeout value with watchdog ioctl | |
318 | * @t: timeout value in seconds | |
319 | * | |
dfb0b8ea OZ |
320 | * The hardware device has a 8 or 16 bit watchdog timer (depends on |
321 | * chip version) that can be configured to count seconds or minutes. | |
e1fee94f OS |
322 | * |
323 | * Used within WDIOC_SETTIMEOUT watchdog device ioctl. | |
324 | */ | |
325 | ||
326 | static int wdt_set_timeout(int t) | |
327 | { | |
dfb0b8ea | 328 | if (t < 1 || t > max_units * 60) |
e1fee94f OS |
329 | return -EINVAL; |
330 | ||
dfb0b8ea OZ |
331 | if (t > max_units) |
332 | timeout = wdt_round_time(t); | |
333 | else | |
334 | timeout = t; | |
e1fee94f | 335 | |
e1fee94f | 336 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { |
a134b825 NG |
337 | int ret = superio_enter(); |
338 | if (ret) | |
339 | return ret; | |
340 | ||
e1fee94f | 341 | superio_select(GPIO); |
dfb0b8ea | 342 | wdt_update_timeout(); |
e1fee94f OS |
343 | superio_exit(); |
344 | } | |
e1fee94f OS |
345 | return 0; |
346 | } | |
347 | ||
348 | /** | |
349 | * wdt_get_status - determines the status supported by watchdog ioctl | |
350 | * @status: status returned to user space | |
351 | * | |
352 | * The status bit of the device does not allow to distinguish | |
353 | * between a regular system reset and a watchdog forced reset. | |
354 | * But, in test mode it is useful, so it is supported through | |
355 | * WDIOC_GETSTATUS watchdog ioctl. Additionally the driver | |
356 | * reports the keepalive signal and the acception of the magic. | |
357 | * | |
358 | * Used within WDIOC_GETSTATUS watchdog device ioctl. | |
359 | */ | |
360 | ||
361 | static int wdt_get_status(int *status) | |
362 | { | |
e1fee94f OS |
363 | *status = 0; |
364 | if (testmode) { | |
a134b825 NG |
365 | int ret = superio_enter(); |
366 | if (ret) | |
367 | return ret; | |
368 | ||
e1fee94f OS |
369 | superio_select(GPIO); |
370 | if (superio_inb(WDTCTRL) & WDT_ZERO) { | |
371 | superio_outb(0x00, WDTCTRL); | |
372 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
373 | *status |= WDIOF_CARDRESET; | |
374 | } | |
375 | ||
376 | superio_exit(); | |
e1fee94f OS |
377 | } |
378 | if (test_and_clear_bit(WDTS_KEEPALIVE, &wdt_status)) | |
379 | *status |= WDIOF_KEEPALIVEPING; | |
380 | if (test_bit(WDTS_EXPECTED, &wdt_status)) | |
381 | *status |= WDIOF_MAGICCLOSE; | |
382 | return 0; | |
383 | } | |
384 | ||
385 | /* /dev/watchdog handling */ | |
386 | ||
387 | /** | |
388 | * wdt_open - watchdog file_operations .open | |
389 | * @inode: inode of the device | |
390 | * @file: file handle to the device | |
391 | * | |
392 | * The watchdog timer starts by opening the device. | |
393 | * | |
394 | * Used within the file operation of the watchdog device. | |
395 | */ | |
396 | ||
397 | static int wdt_open(struct inode *inode, struct file *file) | |
398 | { | |
399 | if (exclusive && test_and_set_bit(WDTS_DEV_OPEN, &wdt_status)) | |
400 | return -EBUSY; | |
401 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
a134b825 | 402 | int ret; |
e1fee94f OS |
403 | if (nowayout && !test_and_set_bit(WDTS_LOCKED, &wdt_status)) |
404 | __module_get(THIS_MODULE); | |
a134b825 NG |
405 | |
406 | ret = wdt_start(); | |
407 | if (ret) { | |
408 | clear_bit(WDTS_LOCKED, &wdt_status); | |
409 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
410 | clear_bit(WDTS_DEV_OPEN, &wdt_status); | |
411 | return ret; | |
412 | } | |
e1fee94f OS |
413 | } |
414 | return nonseekable_open(inode, file); | |
415 | } | |
416 | ||
417 | /** | |
418 | * wdt_release - watchdog file_operations .release | |
419 | * @inode: inode of the device | |
420 | * @file: file handle to the device | |
421 | * | |
422 | * Closing the watchdog device either stops the watchdog timer | |
423 | * or in the case, that nowayout is set or the magic character | |
424 | * wasn't written, a critical warning about an running watchdog | |
425 | * timer is given. | |
426 | * | |
427 | * Used within the file operation of the watchdog device. | |
428 | */ | |
429 | ||
430 | static int wdt_release(struct inode *inode, struct file *file) | |
431 | { | |
432 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
433 | if (test_and_clear_bit(WDTS_EXPECTED, &wdt_status)) { | |
a134b825 NG |
434 | int ret = wdt_stop(); |
435 | if (ret) { | |
436 | /* | |
437 | * Stop failed. Just keep the watchdog alive | |
438 | * and hope nothing bad happens. | |
439 | */ | |
440 | set_bit(WDTS_EXPECTED, &wdt_status); | |
441 | wdt_keepalive(); | |
442 | return ret; | |
443 | } | |
e1fee94f OS |
444 | clear_bit(WDTS_TIMER_RUN, &wdt_status); |
445 | } else { | |
446 | wdt_keepalive(); | |
27c766aa | 447 | pr_crit("unexpected close, not stopping watchdog!\n"); |
e1fee94f OS |
448 | } |
449 | } | |
450 | clear_bit(WDTS_DEV_OPEN, &wdt_status); | |
451 | return 0; | |
452 | } | |
453 | ||
454 | /** | |
455 | * wdt_write - watchdog file_operations .write | |
456 | * @file: file handle to the watchdog | |
457 | * @buf: buffer to write | |
458 | * @count: count of bytes | |
459 | * @ppos: pointer to the position to write. No seeks allowed | |
460 | * | |
461 | * A write to a watchdog device is defined as a keepalive signal. Any | |
462 | * write of data will do, as we don't define content meaning. | |
463 | * | |
464 | * Used within the file operation of the watchdog device. | |
465 | */ | |
466 | ||
467 | static ssize_t wdt_write(struct file *file, const char __user *buf, | |
468 | size_t count, loff_t *ppos) | |
469 | { | |
470 | if (count) { | |
471 | clear_bit(WDTS_EXPECTED, &wdt_status); | |
472 | wdt_keepalive(); | |
473 | } | |
474 | if (!nowayout) { | |
475 | size_t ofs; | |
476 | ||
477 | /* note: just in case someone wrote the magic character long ago */ | |
478 | for (ofs = 0; ofs != count; ofs++) { | |
479 | char c; | |
480 | if (get_user(c, buf + ofs)) | |
481 | return -EFAULT; | |
482 | if (c == WD_MAGIC) | |
483 | set_bit(WDTS_EXPECTED, &wdt_status); | |
484 | } | |
485 | } | |
486 | return count; | |
487 | } | |
488 | ||
42747d71 | 489 | static const struct watchdog_info ident = { |
e1fee94f OS |
490 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
491 | .firmware_version = 1, | |
492 | .identity = WATCHDOG_NAME, | |
493 | }; | |
494 | ||
495 | /** | |
496 | * wdt_ioctl - watchdog file_operations .unlocked_ioctl | |
497 | * @file: file handle to the device | |
498 | * @cmd: watchdog command | |
499 | * @arg: argument pointer | |
500 | * | |
501 | * The watchdog API defines a common set of functions for all watchdogs | |
502 | * according to their available features. | |
503 | * | |
504 | * Used within the file operation of the watchdog device. | |
505 | */ | |
506 | ||
507 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
508 | { | |
509 | int rc = 0, status, new_options, new_timeout; | |
510 | union { | |
511 | struct watchdog_info __user *ident; | |
512 | int __user *i; | |
513 | } uarg; | |
514 | ||
515 | uarg.i = (int __user *)arg; | |
516 | ||
517 | switch (cmd) { | |
518 | case WDIOC_GETSUPPORT: | |
519 | return copy_to_user(uarg.ident, | |
520 | &ident, sizeof(ident)) ? -EFAULT : 0; | |
521 | ||
522 | case WDIOC_GETSTATUS: | |
a134b825 NG |
523 | rc = wdt_get_status(&status); |
524 | if (rc) | |
525 | return rc; | |
e1fee94f OS |
526 | return put_user(status, uarg.i); |
527 | ||
528 | case WDIOC_GETBOOTSTATUS: | |
529 | return put_user(0, uarg.i); | |
530 | ||
531 | case WDIOC_KEEPALIVE: | |
532 | wdt_keepalive(); | |
533 | return 0; | |
534 | ||
535 | case WDIOC_SETOPTIONS: | |
536 | if (get_user(new_options, uarg.i)) | |
537 | return -EFAULT; | |
538 | ||
539 | switch (new_options) { | |
540 | case WDIOS_DISABLECARD: | |
a134b825 NG |
541 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { |
542 | rc = wdt_stop(); | |
543 | if (rc) | |
544 | return rc; | |
545 | } | |
e1fee94f OS |
546 | clear_bit(WDTS_TIMER_RUN, &wdt_status); |
547 | return 0; | |
548 | ||
549 | case WDIOS_ENABLECARD: | |
a134b825 NG |
550 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { |
551 | rc = wdt_start(); | |
552 | if (rc) { | |
553 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
554 | return rc; | |
555 | } | |
556 | } | |
e1fee94f OS |
557 | return 0; |
558 | ||
559 | default: | |
560 | return -EFAULT; | |
561 | } | |
562 | ||
563 | case WDIOC_SETTIMEOUT: | |
564 | if (get_user(new_timeout, uarg.i)) | |
565 | return -EFAULT; | |
566 | rc = wdt_set_timeout(new_timeout); | |
567 | case WDIOC_GETTIMEOUT: | |
568 | if (put_user(timeout, uarg.i)) | |
569 | return -EFAULT; | |
570 | return rc; | |
571 | ||
572 | default: | |
573 | return -ENOTTY; | |
574 | } | |
575 | } | |
576 | ||
577 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |
578 | void *unused) | |
579 | { | |
580 | if (code == SYS_DOWN || code == SYS_HALT) | |
581 | wdt_stop(); | |
582 | return NOTIFY_DONE; | |
583 | } | |
584 | ||
585 | static const struct file_operations wdt_fops = { | |
586 | .owner = THIS_MODULE, | |
587 | .llseek = no_llseek, | |
588 | .write = wdt_write, | |
589 | .unlocked_ioctl = wdt_ioctl, | |
590 | .open = wdt_open, | |
591 | .release = wdt_release, | |
592 | }; | |
593 | ||
594 | static struct miscdevice wdt_miscdev = { | |
595 | .minor = WATCHDOG_MINOR, | |
596 | .name = "watchdog", | |
597 | .fops = &wdt_fops, | |
598 | }; | |
599 | ||
600 | static struct notifier_block wdt_notifier = { | |
601 | .notifier_call = wdt_notify_sys, | |
602 | }; | |
603 | ||
604 | static int __init it87_wdt_init(void) | |
605 | { | |
606 | int rc = 0; | |
ee3e9658 | 607 | int try_gameport = !nogameport; |
e1fee94f | 608 | u8 chip_rev; |
a134b825 | 609 | int gp_rreq_fail = 0; |
e1fee94f | 610 | |
dfb0b8ea OZ |
611 | wdt_status = 0; |
612 | ||
a134b825 NG |
613 | rc = superio_enter(); |
614 | if (rc) | |
615 | return rc; | |
616 | ||
e1fee94f OS |
617 | chip_type = superio_inw(CHIPID); |
618 | chip_rev = superio_inb(CHIPREV) & 0x0f; | |
619 | superio_exit(); | |
e1fee94f OS |
620 | |
621 | switch (chip_type) { | |
dfb0b8ea OZ |
622 | case IT8702_ID: |
623 | max_units = 255; | |
624 | break; | |
625 | case IT8712_ID: | |
626 | max_units = (chip_rev < 8) ? 255 : 65535; | |
627 | break; | |
e1fee94f | 628 | case IT8716_ID: |
e1fee94f | 629 | case IT8726_ID: |
dfb0b8ea | 630 | max_units = 65535; |
e1fee94f | 631 | break; |
ee3e9658 OZ |
632 | case IT8718_ID: |
633 | case IT8720_ID: | |
4bc30272 | 634 | case IT8721_ID: |
198ca015 | 635 | case IT8728_ID: |
dfb0b8ea | 636 | max_units = 65535; |
ee3e9658 OZ |
637 | try_gameport = 0; |
638 | break; | |
e1fee94f | 639 | case IT8705_ID: |
27c766aa | 640 | pr_err("Unsupported Chip found, Chip %04x Revision %02x\n", |
e1fee94f OS |
641 | chip_type, chip_rev); |
642 | return -ENODEV; | |
643 | case NO_DEV_ID: | |
27c766aa | 644 | pr_err("no device\n"); |
e1fee94f OS |
645 | return -ENODEV; |
646 | default: | |
27c766aa | 647 | pr_err("Unknown Chip found, Chip %04x Revision %04x\n", |
e1fee94f OS |
648 | chip_type, chip_rev); |
649 | return -ENODEV; | |
650 | } | |
651 | ||
a134b825 NG |
652 | rc = superio_enter(); |
653 | if (rc) | |
654 | return rc; | |
e1fee94f OS |
655 | |
656 | superio_select(GPIO); | |
657 | superio_outb(WDT_TOV1, WDTCFG); | |
658 | superio_outb(0x00, WDTCTRL); | |
659 | ||
660 | /* First try to get Gameport support */ | |
ee3e9658 | 661 | if (try_gameport) { |
e1fee94f OS |
662 | superio_select(GAMEPORT); |
663 | base = superio_inw(BASEREG); | |
664 | if (!base) { | |
665 | base = GP_BASE_DEFAULT; | |
666 | superio_outw(base, BASEREG); | |
667 | } | |
668 | gpact = superio_inb(ACTREG); | |
669 | superio_outb(0x01, ACTREG); | |
e1fee94f OS |
670 | if (request_region(base, 1, WATCHDOG_NAME)) |
671 | set_bit(WDTS_USE_GP, &wdt_status); | |
672 | else | |
a134b825 | 673 | gp_rreq_fail = 1; |
e1fee94f OS |
674 | } |
675 | ||
676 | /* If we haven't Gameport support, try to get CIR support */ | |
0bcd0b6a | 677 | if (!nocir && !test_bit(WDTS_USE_GP, &wdt_status)) { |
e1fee94f | 678 | if (!request_region(CIR_BASE, 8, WATCHDOG_NAME)) { |
a134b825 | 679 | if (gp_rreq_fail) |
27c766aa JP |
680 | pr_err("I/O Address 0x%04x and 0x%04x already in use\n", |
681 | base, CIR_BASE); | |
e1fee94f | 682 | else |
27c766aa JP |
683 | pr_err("I/O Address 0x%04x already in use\n", |
684 | CIR_BASE); | |
e1fee94f OS |
685 | rc = -EIO; |
686 | goto err_out; | |
687 | } | |
688 | base = CIR_BASE; | |
e1fee94f OS |
689 | |
690 | superio_select(CIR); | |
691 | superio_outw(base, BASEREG); | |
692 | superio_outb(0x00, CIR_ILS); | |
693 | ciract = superio_inb(ACTREG); | |
694 | superio_outb(0x01, ACTREG); | |
a134b825 | 695 | if (gp_rreq_fail) { |
e1fee94f OS |
696 | superio_select(GAMEPORT); |
697 | superio_outb(gpact, ACTREG); | |
698 | } | |
0bcd0b6a | 699 | set_bit(WDTS_USE_CIR, &wdt_status); |
e1fee94f OS |
700 | } |
701 | ||
dfb0b8ea | 702 | if (timeout < 1 || timeout > max_units * 60) { |
e1fee94f | 703 | timeout = DEFAULT_TIMEOUT; |
27c766aa JP |
704 | pr_warn("Timeout value out of range, use default %d sec\n", |
705 | DEFAULT_TIMEOUT); | |
e1fee94f OS |
706 | } |
707 | ||
dfb0b8ea OZ |
708 | if (timeout > max_units) |
709 | timeout = wdt_round_time(timeout); | |
710 | ||
e1fee94f OS |
711 | rc = register_reboot_notifier(&wdt_notifier); |
712 | if (rc) { | |
27c766aa | 713 | pr_err("Cannot register reboot notifier (err=%d)\n", rc); |
e1fee94f OS |
714 | goto err_out_region; |
715 | } | |
716 | ||
717 | rc = misc_register(&wdt_miscdev); | |
718 | if (rc) { | |
27c766aa JP |
719 | pr_err("Cannot register miscdev on minor=%d (err=%d)\n", |
720 | wdt_miscdev.minor, rc); | |
e1fee94f OS |
721 | goto err_out_reboot; |
722 | } | |
723 | ||
724 | /* Initialize CIR to use it as keepalive source */ | |
0bcd0b6a | 725 | if (test_bit(WDTS_USE_CIR, &wdt_status)) { |
e1fee94f OS |
726 | outb(0x00, CIR_RCR(base)); |
727 | outb(0xc0, CIR_TCR1(base)); | |
728 | outb(0x5c, CIR_TCR2(base)); | |
729 | outb(0x10, CIR_IER(base)); | |
730 | outb(0x00, CIR_BDHR(base)); | |
731 | outb(0x01, CIR_BDLR(base)); | |
732 | outb(0x09, CIR_IER(base)); | |
733 | } | |
734 | ||
0bcd0b6a | 735 | pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d exclusive=%d nogameport=%d nocir=%d)\n", |
27c766aa | 736 | chip_type, chip_rev, timeout, |
0bcd0b6a | 737 | nowayout, testmode, exclusive, nogameport, nocir); |
e1fee94f | 738 | |
a134b825 | 739 | superio_exit(); |
e1fee94f OS |
740 | return 0; |
741 | ||
742 | err_out_reboot: | |
743 | unregister_reboot_notifier(&wdt_notifier); | |
744 | err_out_region: | |
0bcd0b6a MW |
745 | if (test_bit(WDTS_USE_GP, &wdt_status)) |
746 | release_region(base, 1); | |
747 | else if (test_bit(WDTS_USE_CIR, &wdt_status)) { | |
748 | release_region(base, 8); | |
e1fee94f OS |
749 | superio_select(CIR); |
750 | superio_outb(ciract, ACTREG); | |
e1fee94f OS |
751 | } |
752 | err_out: | |
ee3e9658 | 753 | if (try_gameport) { |
e1fee94f OS |
754 | superio_select(GAMEPORT); |
755 | superio_outb(gpact, ACTREG); | |
e1fee94f OS |
756 | } |
757 | ||
a134b825 | 758 | superio_exit(); |
e1fee94f OS |
759 | return rc; |
760 | } | |
761 | ||
762 | static void __exit it87_wdt_exit(void) | |
763 | { | |
a134b825 NG |
764 | if (superio_enter() == 0) { |
765 | superio_select(GPIO); | |
766 | superio_outb(0x00, WDTCTRL); | |
767 | superio_outb(0x00, WDTCFG); | |
768 | superio_outb(0x00, WDTVALLSB); | |
769 | if (max_units > 255) | |
770 | superio_outb(0x00, WDTVALMSB); | |
771 | if (test_bit(WDTS_USE_GP, &wdt_status)) { | |
772 | superio_select(GAMEPORT); | |
773 | superio_outb(gpact, ACTREG); | |
0bcd0b6a | 774 | } else if (test_bit(WDTS_USE_CIR, &wdt_status)) { |
a134b825 NG |
775 | superio_select(CIR); |
776 | superio_outb(ciract, ACTREG); | |
777 | } | |
778 | superio_exit(); | |
e1fee94f | 779 | } |
e1fee94f OS |
780 | |
781 | misc_deregister(&wdt_miscdev); | |
782 | unregister_reboot_notifier(&wdt_notifier); | |
0bcd0b6a MW |
783 | |
784 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
785 | release_region(base, 1); | |
786 | else if (test_bit(WDTS_USE_CIR, &wdt_status)) | |
787 | release_region(base, 8); | |
e1fee94f OS |
788 | } |
789 | ||
790 | module_init(it87_wdt_init); | |
791 | module_exit(it87_wdt_exit); | |
792 | ||
793 | MODULE_AUTHOR("Oliver Schuster"); | |
794 | MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O"); | |
795 | MODULE_LICENSE("GPL"); |