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e1fee94f OS |
1 | /* |
2 | * Watchdog Timer Driver | |
3 | * for ITE IT87xx Environment Control - Low Pin Count Input / Output | |
4 | * | |
5 | * (c) Copyright 2007 Oliver Schuster <olivers137@aol.com> | |
6 | * | |
7 | * Based on softdog.c by Alan Cox, | |
8 | * 83977f_wdt.c by Jose Goncalves, | |
9 | * it87.c by Chris Gauthron, Jean Delvare | |
10 | * | |
11 | * Data-sheets: Publicly available at the ITE website | |
12 | * http://www.ite.com.tw/ | |
13 | * | |
14 | * Support of the watchdog timers, which are available on | |
4bc30272 | 15 | * IT8702, IT8712, IT8716, IT8718, IT8720, IT8721 and IT8726. |
e1fee94f OS |
16 | * |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License | |
19 | * as published by the Free Software Foundation; either version | |
20 | * 2 of the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | */ | |
31 | ||
27c766aa JP |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
e1fee94f OS |
34 | #include <linux/module.h> |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/fs.h> | |
39 | #include <linux/miscdevice.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/watchdog.h> | |
43 | #include <linux/notifier.h> | |
44 | #include <linux/reboot.h> | |
45 | #include <linux/uaccess.h> | |
46 | #include <linux/io.h> | |
47 | ||
e1fee94f | 48 | |
4bc30272 | 49 | #define WATCHDOG_VERSION "1.14" |
e1fee94f | 50 | #define WATCHDOG_NAME "IT87 WDT" |
e1fee94f OS |
51 | #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" |
52 | #define WD_MAGIC 'V' | |
53 | ||
54 | /* Defaults for Module Parameter */ | |
55 | #define DEFAULT_NOGAMEPORT 0 | |
56 | #define DEFAULT_EXCLUSIVE 1 | |
5f3b2756 | 57 | #define DEFAULT_TIMEOUT 60 |
e1fee94f OS |
58 | #define DEFAULT_TESTMODE 0 |
59 | #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT | |
60 | ||
61 | /* IO Ports */ | |
62 | #define REG 0x2e | |
63 | #define VAL 0x2f | |
64 | ||
65 | /* Logical device Numbers LDN */ | |
66 | #define GPIO 0x07 | |
67 | #define GAMEPORT 0x09 | |
68 | #define CIR 0x0a | |
69 | ||
70 | /* Configuration Registers and Functions */ | |
71 | #define LDNREG 0x07 | |
72 | #define CHIPID 0x20 | |
5f3b2756 | 73 | #define CHIPREV 0x22 |
e1fee94f | 74 | #define ACTREG 0x30 |
5f3b2756 | 75 | #define BASEREG 0x60 |
e1fee94f OS |
76 | |
77 | /* Chip Id numbers */ | |
78 | #define NO_DEV_ID 0xffff | |
dfb0b8ea | 79 | #define IT8702_ID 0x8702 |
e1fee94f OS |
80 | #define IT8705_ID 0x8705 |
81 | #define IT8712_ID 0x8712 | |
82 | #define IT8716_ID 0x8716 | |
83 | #define IT8718_ID 0x8718 | |
ee3e9658 | 84 | #define IT8720_ID 0x8720 |
4bc30272 | 85 | #define IT8721_ID 0x8721 |
e1fee94f OS |
86 | #define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */ |
87 | ||
88 | /* GPIO Configuration Registers LDN=0x07 */ | |
5f3b2756 | 89 | #define WDTCTRL 0x71 |
e1fee94f OS |
90 | #define WDTCFG 0x72 |
91 | #define WDTVALLSB 0x73 | |
92 | #define WDTVALMSB 0x74 | |
93 | ||
94 | /* GPIO Bits WDTCTRL */ | |
95 | #define WDT_CIRINT 0x80 | |
96 | #define WDT_MOUSEINT 0x40 | |
97 | #define WDT_KYBINT 0x20 | |
4bc30272 | 98 | #define WDT_GAMEPORT 0x10 /* not in it8718, it8720, it8721 */ |
e1fee94f OS |
99 | #define WDT_FORCE 0x02 |
100 | #define WDT_ZERO 0x01 | |
101 | ||
102 | /* GPIO Bits WDTCFG */ | |
103 | #define WDT_TOV1 0x80 | |
104 | #define WDT_KRST 0x40 | |
105 | #define WDT_TOVE 0x20 | |
4bc30272 | 106 | #define WDT_PWROK 0x10 /* not in it8721 */ |
e1fee94f OS |
107 | #define WDT_INT_MASK 0x0f |
108 | ||
109 | /* CIR Configuration Register LDN=0x0a */ | |
5f3b2756 | 110 | #define CIR_ILS 0x70 |
e1fee94f OS |
111 | |
112 | /* The default Base address is not always available, we use this */ | |
113 | #define CIR_BASE 0x0208 | |
114 | ||
115 | /* CIR Controller */ | |
116 | #define CIR_DR(b) (b) | |
117 | #define CIR_IER(b) (b + 1) | |
118 | #define CIR_RCR(b) (b + 2) | |
119 | #define CIR_TCR1(b) (b + 3) | |
120 | #define CIR_TCR2(b) (b + 4) | |
121 | #define CIR_TSR(b) (b + 5) | |
122 | #define CIR_RSR(b) (b + 6) | |
123 | #define CIR_BDLR(b) (b + 5) | |
124 | #define CIR_BDHR(b) (b + 6) | |
125 | #define CIR_IIR(b) (b + 7) | |
126 | ||
127 | /* Default Base address of Game port */ | |
128 | #define GP_BASE_DEFAULT 0x0201 | |
129 | ||
130 | /* wdt_status */ | |
131 | #define WDTS_TIMER_RUN 0 | |
132 | #define WDTS_DEV_OPEN 1 | |
133 | #define WDTS_KEEPALIVE 2 | |
134 | #define WDTS_LOCKED 3 | |
135 | #define WDTS_USE_GP 4 | |
136 | #define WDTS_EXPECTED 5 | |
137 | ||
4bc30272 | 138 | static unsigned int base, gpact, ciract, max_units, chip_type; |
e1fee94f | 139 | static unsigned long wdt_status; |
e1fee94f OS |
140 | |
141 | static int nogameport = DEFAULT_NOGAMEPORT; | |
142 | static int exclusive = DEFAULT_EXCLUSIVE; | |
143 | static int timeout = DEFAULT_TIMEOUT; | |
144 | static int testmode = DEFAULT_TESTMODE; | |
86a1e189 | 145 | static bool nowayout = DEFAULT_NOWAYOUT; |
e1fee94f OS |
146 | |
147 | module_param(nogameport, int, 0); | |
148 | MODULE_PARM_DESC(nogameport, "Forbid the activation of game port, default=" | |
149 | __MODULE_STRING(DEFAULT_NOGAMEPORT)); | |
150 | module_param(exclusive, int, 0); | |
151 | MODULE_PARM_DESC(exclusive, "Watchdog exclusive device open, default=" | |
152 | __MODULE_STRING(DEFAULT_EXCLUSIVE)); | |
153 | module_param(timeout, int, 0); | |
154 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default=" | |
155 | __MODULE_STRING(DEFAULT_TIMEOUT)); | |
156 | module_param(testmode, int, 0); | |
157 | MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default=" | |
158 | __MODULE_STRING(DEFAULT_TESTMODE)); | |
86a1e189 | 159 | module_param(nowayout, bool, 0); |
e1fee94f OS |
160 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default=" |
161 | __MODULE_STRING(WATCHDOG_NOWAYOUT)); | |
162 | ||
163 | /* Superio Chip */ | |
164 | ||
a134b825 | 165 | static inline int superio_enter(void) |
e1fee94f | 166 | { |
a134b825 NG |
167 | /* |
168 | * Try to reserve REG and REG + 1 for exclusive access. | |
169 | */ | |
170 | if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) | |
171 | return -EBUSY; | |
172 | ||
e1fee94f OS |
173 | outb(0x87, REG); |
174 | outb(0x01, REG); | |
175 | outb(0x55, REG); | |
176 | outb(0x55, REG); | |
a134b825 | 177 | return 0; |
e1fee94f OS |
178 | } |
179 | ||
180 | static inline void superio_exit(void) | |
181 | { | |
182 | outb(0x02, REG); | |
183 | outb(0x02, VAL); | |
a134b825 | 184 | release_region(REG, 2); |
e1fee94f OS |
185 | } |
186 | ||
187 | static inline void superio_select(int ldn) | |
188 | { | |
189 | outb(LDNREG, REG); | |
190 | outb(ldn, VAL); | |
191 | } | |
192 | ||
193 | static inline int superio_inb(int reg) | |
194 | { | |
195 | outb(reg, REG); | |
196 | return inb(VAL); | |
197 | } | |
198 | ||
199 | static inline void superio_outb(int val, int reg) | |
200 | { | |
143a2e54 WVS |
201 | outb(reg, REG); |
202 | outb(val, VAL); | |
e1fee94f OS |
203 | } |
204 | ||
205 | static inline int superio_inw(int reg) | |
206 | { | |
207 | int val; | |
208 | outb(reg++, REG); | |
209 | val = inb(VAL) << 8; | |
210 | outb(reg, REG); | |
211 | val |= inb(VAL); | |
212 | return val; | |
213 | } | |
214 | ||
215 | static inline void superio_outw(int val, int reg) | |
216 | { | |
143a2e54 WVS |
217 | outb(reg++, REG); |
218 | outb(val >> 8, VAL); | |
219 | outb(reg, REG); | |
220 | outb(val, VAL); | |
e1fee94f OS |
221 | } |
222 | ||
dfb0b8ea OZ |
223 | /* Internal function, should be called after superio_select(GPIO) */ |
224 | static void wdt_update_timeout(void) | |
225 | { | |
4bc30272 | 226 | unsigned char cfg = WDT_KRST; |
dfb0b8ea OZ |
227 | int tm = timeout; |
228 | ||
229 | if (testmode) | |
230 | cfg = 0; | |
231 | ||
232 | if (tm <= max_units) | |
233 | cfg |= WDT_TOV1; | |
234 | else | |
235 | tm /= 60; | |
236 | ||
4bc30272 HT |
237 | if (chip_type != IT8721_ID) |
238 | cfg |= WDT_PWROK; | |
239 | ||
dfb0b8ea OZ |
240 | superio_outb(cfg, WDTCFG); |
241 | superio_outb(tm, WDTVALLSB); | |
242 | if (max_units > 255) | |
243 | superio_outb(tm>>8, WDTVALMSB); | |
244 | } | |
245 | ||
246 | static int wdt_round_time(int t) | |
247 | { | |
248 | t += 59; | |
249 | t -= t % 60; | |
250 | return t; | |
251 | } | |
252 | ||
e1fee94f OS |
253 | /* watchdog timer handling */ |
254 | ||
255 | static void wdt_keepalive(void) | |
256 | { | |
257 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
258 | inb(base); | |
259 | else | |
260 | /* The timer reloads with around 5 msec delay */ | |
261 | outb(0x55, CIR_DR(base)); | |
262 | set_bit(WDTS_KEEPALIVE, &wdt_status); | |
263 | } | |
264 | ||
a134b825 | 265 | static int wdt_start(void) |
e1fee94f | 266 | { |
a134b825 NG |
267 | int ret = superio_enter(); |
268 | if (ret) | |
269 | return ret; | |
e1fee94f OS |
270 | |
271 | superio_select(GPIO); | |
272 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
273 | superio_outb(WDT_GAMEPORT, WDTCTRL); | |
274 | else | |
275 | superio_outb(WDT_CIRINT, WDTCTRL); | |
dfb0b8ea | 276 | wdt_update_timeout(); |
e1fee94f OS |
277 | |
278 | superio_exit(); | |
a134b825 NG |
279 | |
280 | return 0; | |
e1fee94f OS |
281 | } |
282 | ||
a134b825 | 283 | static int wdt_stop(void) |
e1fee94f | 284 | { |
a134b825 NG |
285 | int ret = superio_enter(); |
286 | if (ret) | |
287 | return ret; | |
e1fee94f OS |
288 | |
289 | superio_select(GPIO); | |
290 | superio_outb(0x00, WDTCTRL); | |
291 | superio_outb(WDT_TOV1, WDTCFG); | |
e1fee94f | 292 | superio_outb(0x00, WDTVALLSB); |
dfb0b8ea OZ |
293 | if (max_units > 255) |
294 | superio_outb(0x00, WDTVALMSB); | |
e1fee94f OS |
295 | |
296 | superio_exit(); | |
a134b825 | 297 | return 0; |
e1fee94f OS |
298 | } |
299 | ||
300 | /** | |
301 | * wdt_set_timeout - set a new timeout value with watchdog ioctl | |
302 | * @t: timeout value in seconds | |
303 | * | |
dfb0b8ea OZ |
304 | * The hardware device has a 8 or 16 bit watchdog timer (depends on |
305 | * chip version) that can be configured to count seconds or minutes. | |
e1fee94f OS |
306 | * |
307 | * Used within WDIOC_SETTIMEOUT watchdog device ioctl. | |
308 | */ | |
309 | ||
310 | static int wdt_set_timeout(int t) | |
311 | { | |
dfb0b8ea | 312 | if (t < 1 || t > max_units * 60) |
e1fee94f OS |
313 | return -EINVAL; |
314 | ||
dfb0b8ea OZ |
315 | if (t > max_units) |
316 | timeout = wdt_round_time(t); | |
317 | else | |
318 | timeout = t; | |
e1fee94f | 319 | |
e1fee94f | 320 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { |
a134b825 NG |
321 | int ret = superio_enter(); |
322 | if (ret) | |
323 | return ret; | |
324 | ||
e1fee94f | 325 | superio_select(GPIO); |
dfb0b8ea | 326 | wdt_update_timeout(); |
e1fee94f OS |
327 | superio_exit(); |
328 | } | |
e1fee94f OS |
329 | return 0; |
330 | } | |
331 | ||
332 | /** | |
333 | * wdt_get_status - determines the status supported by watchdog ioctl | |
334 | * @status: status returned to user space | |
335 | * | |
336 | * The status bit of the device does not allow to distinguish | |
337 | * between a regular system reset and a watchdog forced reset. | |
338 | * But, in test mode it is useful, so it is supported through | |
339 | * WDIOC_GETSTATUS watchdog ioctl. Additionally the driver | |
340 | * reports the keepalive signal and the acception of the magic. | |
341 | * | |
342 | * Used within WDIOC_GETSTATUS watchdog device ioctl. | |
343 | */ | |
344 | ||
345 | static int wdt_get_status(int *status) | |
346 | { | |
e1fee94f OS |
347 | *status = 0; |
348 | if (testmode) { | |
a134b825 NG |
349 | int ret = superio_enter(); |
350 | if (ret) | |
351 | return ret; | |
352 | ||
e1fee94f OS |
353 | superio_select(GPIO); |
354 | if (superio_inb(WDTCTRL) & WDT_ZERO) { | |
355 | superio_outb(0x00, WDTCTRL); | |
356 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
357 | *status |= WDIOF_CARDRESET; | |
358 | } | |
359 | ||
360 | superio_exit(); | |
e1fee94f OS |
361 | } |
362 | if (test_and_clear_bit(WDTS_KEEPALIVE, &wdt_status)) | |
363 | *status |= WDIOF_KEEPALIVEPING; | |
364 | if (test_bit(WDTS_EXPECTED, &wdt_status)) | |
365 | *status |= WDIOF_MAGICCLOSE; | |
366 | return 0; | |
367 | } | |
368 | ||
369 | /* /dev/watchdog handling */ | |
370 | ||
371 | /** | |
372 | * wdt_open - watchdog file_operations .open | |
373 | * @inode: inode of the device | |
374 | * @file: file handle to the device | |
375 | * | |
376 | * The watchdog timer starts by opening the device. | |
377 | * | |
378 | * Used within the file operation of the watchdog device. | |
379 | */ | |
380 | ||
381 | static int wdt_open(struct inode *inode, struct file *file) | |
382 | { | |
383 | if (exclusive && test_and_set_bit(WDTS_DEV_OPEN, &wdt_status)) | |
384 | return -EBUSY; | |
385 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
a134b825 | 386 | int ret; |
e1fee94f OS |
387 | if (nowayout && !test_and_set_bit(WDTS_LOCKED, &wdt_status)) |
388 | __module_get(THIS_MODULE); | |
a134b825 NG |
389 | |
390 | ret = wdt_start(); | |
391 | if (ret) { | |
392 | clear_bit(WDTS_LOCKED, &wdt_status); | |
393 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
394 | clear_bit(WDTS_DEV_OPEN, &wdt_status); | |
395 | return ret; | |
396 | } | |
e1fee94f OS |
397 | } |
398 | return nonseekable_open(inode, file); | |
399 | } | |
400 | ||
401 | /** | |
402 | * wdt_release - watchdog file_operations .release | |
403 | * @inode: inode of the device | |
404 | * @file: file handle to the device | |
405 | * | |
406 | * Closing the watchdog device either stops the watchdog timer | |
407 | * or in the case, that nowayout is set or the magic character | |
408 | * wasn't written, a critical warning about an running watchdog | |
409 | * timer is given. | |
410 | * | |
411 | * Used within the file operation of the watchdog device. | |
412 | */ | |
413 | ||
414 | static int wdt_release(struct inode *inode, struct file *file) | |
415 | { | |
416 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
417 | if (test_and_clear_bit(WDTS_EXPECTED, &wdt_status)) { | |
a134b825 NG |
418 | int ret = wdt_stop(); |
419 | if (ret) { | |
420 | /* | |
421 | * Stop failed. Just keep the watchdog alive | |
422 | * and hope nothing bad happens. | |
423 | */ | |
424 | set_bit(WDTS_EXPECTED, &wdt_status); | |
425 | wdt_keepalive(); | |
426 | return ret; | |
427 | } | |
e1fee94f OS |
428 | clear_bit(WDTS_TIMER_RUN, &wdt_status); |
429 | } else { | |
430 | wdt_keepalive(); | |
27c766aa | 431 | pr_crit("unexpected close, not stopping watchdog!\n"); |
e1fee94f OS |
432 | } |
433 | } | |
434 | clear_bit(WDTS_DEV_OPEN, &wdt_status); | |
435 | return 0; | |
436 | } | |
437 | ||
438 | /** | |
439 | * wdt_write - watchdog file_operations .write | |
440 | * @file: file handle to the watchdog | |
441 | * @buf: buffer to write | |
442 | * @count: count of bytes | |
443 | * @ppos: pointer to the position to write. No seeks allowed | |
444 | * | |
445 | * A write to a watchdog device is defined as a keepalive signal. Any | |
446 | * write of data will do, as we don't define content meaning. | |
447 | * | |
448 | * Used within the file operation of the watchdog device. | |
449 | */ | |
450 | ||
451 | static ssize_t wdt_write(struct file *file, const char __user *buf, | |
452 | size_t count, loff_t *ppos) | |
453 | { | |
454 | if (count) { | |
455 | clear_bit(WDTS_EXPECTED, &wdt_status); | |
456 | wdt_keepalive(); | |
457 | } | |
458 | if (!nowayout) { | |
459 | size_t ofs; | |
460 | ||
461 | /* note: just in case someone wrote the magic character long ago */ | |
462 | for (ofs = 0; ofs != count; ofs++) { | |
463 | char c; | |
464 | if (get_user(c, buf + ofs)) | |
465 | return -EFAULT; | |
466 | if (c == WD_MAGIC) | |
467 | set_bit(WDTS_EXPECTED, &wdt_status); | |
468 | } | |
469 | } | |
470 | return count; | |
471 | } | |
472 | ||
42747d71 | 473 | static const struct watchdog_info ident = { |
e1fee94f OS |
474 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
475 | .firmware_version = 1, | |
476 | .identity = WATCHDOG_NAME, | |
477 | }; | |
478 | ||
479 | /** | |
480 | * wdt_ioctl - watchdog file_operations .unlocked_ioctl | |
481 | * @file: file handle to the device | |
482 | * @cmd: watchdog command | |
483 | * @arg: argument pointer | |
484 | * | |
485 | * The watchdog API defines a common set of functions for all watchdogs | |
486 | * according to their available features. | |
487 | * | |
488 | * Used within the file operation of the watchdog device. | |
489 | */ | |
490 | ||
491 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
492 | { | |
493 | int rc = 0, status, new_options, new_timeout; | |
494 | union { | |
495 | struct watchdog_info __user *ident; | |
496 | int __user *i; | |
497 | } uarg; | |
498 | ||
499 | uarg.i = (int __user *)arg; | |
500 | ||
501 | switch (cmd) { | |
502 | case WDIOC_GETSUPPORT: | |
503 | return copy_to_user(uarg.ident, | |
504 | &ident, sizeof(ident)) ? -EFAULT : 0; | |
505 | ||
506 | case WDIOC_GETSTATUS: | |
a134b825 NG |
507 | rc = wdt_get_status(&status); |
508 | if (rc) | |
509 | return rc; | |
e1fee94f OS |
510 | return put_user(status, uarg.i); |
511 | ||
512 | case WDIOC_GETBOOTSTATUS: | |
513 | return put_user(0, uarg.i); | |
514 | ||
515 | case WDIOC_KEEPALIVE: | |
516 | wdt_keepalive(); | |
517 | return 0; | |
518 | ||
519 | case WDIOC_SETOPTIONS: | |
520 | if (get_user(new_options, uarg.i)) | |
521 | return -EFAULT; | |
522 | ||
523 | switch (new_options) { | |
524 | case WDIOS_DISABLECARD: | |
a134b825 NG |
525 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { |
526 | rc = wdt_stop(); | |
527 | if (rc) | |
528 | return rc; | |
529 | } | |
e1fee94f OS |
530 | clear_bit(WDTS_TIMER_RUN, &wdt_status); |
531 | return 0; | |
532 | ||
533 | case WDIOS_ENABLECARD: | |
a134b825 NG |
534 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { |
535 | rc = wdt_start(); | |
536 | if (rc) { | |
537 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
538 | return rc; | |
539 | } | |
540 | } | |
e1fee94f OS |
541 | return 0; |
542 | ||
543 | default: | |
544 | return -EFAULT; | |
545 | } | |
546 | ||
547 | case WDIOC_SETTIMEOUT: | |
548 | if (get_user(new_timeout, uarg.i)) | |
549 | return -EFAULT; | |
550 | rc = wdt_set_timeout(new_timeout); | |
551 | case WDIOC_GETTIMEOUT: | |
552 | if (put_user(timeout, uarg.i)) | |
553 | return -EFAULT; | |
554 | return rc; | |
555 | ||
556 | default: | |
557 | return -ENOTTY; | |
558 | } | |
559 | } | |
560 | ||
561 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |
562 | void *unused) | |
563 | { | |
564 | if (code == SYS_DOWN || code == SYS_HALT) | |
565 | wdt_stop(); | |
566 | return NOTIFY_DONE; | |
567 | } | |
568 | ||
569 | static const struct file_operations wdt_fops = { | |
570 | .owner = THIS_MODULE, | |
571 | .llseek = no_llseek, | |
572 | .write = wdt_write, | |
573 | .unlocked_ioctl = wdt_ioctl, | |
574 | .open = wdt_open, | |
575 | .release = wdt_release, | |
576 | }; | |
577 | ||
578 | static struct miscdevice wdt_miscdev = { | |
579 | .minor = WATCHDOG_MINOR, | |
580 | .name = "watchdog", | |
581 | .fops = &wdt_fops, | |
582 | }; | |
583 | ||
584 | static struct notifier_block wdt_notifier = { | |
585 | .notifier_call = wdt_notify_sys, | |
586 | }; | |
587 | ||
588 | static int __init it87_wdt_init(void) | |
589 | { | |
590 | int rc = 0; | |
ee3e9658 | 591 | int try_gameport = !nogameport; |
e1fee94f | 592 | u8 chip_rev; |
a134b825 | 593 | int gp_rreq_fail = 0; |
e1fee94f | 594 | |
dfb0b8ea OZ |
595 | wdt_status = 0; |
596 | ||
a134b825 NG |
597 | rc = superio_enter(); |
598 | if (rc) | |
599 | return rc; | |
600 | ||
e1fee94f OS |
601 | chip_type = superio_inw(CHIPID); |
602 | chip_rev = superio_inb(CHIPREV) & 0x0f; | |
603 | superio_exit(); | |
e1fee94f OS |
604 | |
605 | switch (chip_type) { | |
dfb0b8ea OZ |
606 | case IT8702_ID: |
607 | max_units = 255; | |
608 | break; | |
609 | case IT8712_ID: | |
610 | max_units = (chip_rev < 8) ? 255 : 65535; | |
611 | break; | |
e1fee94f | 612 | case IT8716_ID: |
e1fee94f | 613 | case IT8726_ID: |
dfb0b8ea | 614 | max_units = 65535; |
e1fee94f | 615 | break; |
ee3e9658 OZ |
616 | case IT8718_ID: |
617 | case IT8720_ID: | |
4bc30272 | 618 | case IT8721_ID: |
dfb0b8ea | 619 | max_units = 65535; |
ee3e9658 OZ |
620 | try_gameport = 0; |
621 | break; | |
e1fee94f | 622 | case IT8705_ID: |
27c766aa | 623 | pr_err("Unsupported Chip found, Chip %04x Revision %02x\n", |
e1fee94f OS |
624 | chip_type, chip_rev); |
625 | return -ENODEV; | |
626 | case NO_DEV_ID: | |
27c766aa | 627 | pr_err("no device\n"); |
e1fee94f OS |
628 | return -ENODEV; |
629 | default: | |
27c766aa | 630 | pr_err("Unknown Chip found, Chip %04x Revision %04x\n", |
e1fee94f OS |
631 | chip_type, chip_rev); |
632 | return -ENODEV; | |
633 | } | |
634 | ||
a134b825 NG |
635 | rc = superio_enter(); |
636 | if (rc) | |
637 | return rc; | |
e1fee94f OS |
638 | |
639 | superio_select(GPIO); | |
640 | superio_outb(WDT_TOV1, WDTCFG); | |
641 | superio_outb(0x00, WDTCTRL); | |
642 | ||
643 | /* First try to get Gameport support */ | |
ee3e9658 | 644 | if (try_gameport) { |
e1fee94f OS |
645 | superio_select(GAMEPORT); |
646 | base = superio_inw(BASEREG); | |
647 | if (!base) { | |
648 | base = GP_BASE_DEFAULT; | |
649 | superio_outw(base, BASEREG); | |
650 | } | |
651 | gpact = superio_inb(ACTREG); | |
652 | superio_outb(0x01, ACTREG); | |
e1fee94f OS |
653 | if (request_region(base, 1, WATCHDOG_NAME)) |
654 | set_bit(WDTS_USE_GP, &wdt_status); | |
655 | else | |
a134b825 | 656 | gp_rreq_fail = 1; |
e1fee94f OS |
657 | } |
658 | ||
659 | /* If we haven't Gameport support, try to get CIR support */ | |
660 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
661 | if (!request_region(CIR_BASE, 8, WATCHDOG_NAME)) { | |
a134b825 | 662 | if (gp_rreq_fail) |
27c766aa JP |
663 | pr_err("I/O Address 0x%04x and 0x%04x already in use\n", |
664 | base, CIR_BASE); | |
e1fee94f | 665 | else |
27c766aa JP |
666 | pr_err("I/O Address 0x%04x already in use\n", |
667 | CIR_BASE); | |
e1fee94f OS |
668 | rc = -EIO; |
669 | goto err_out; | |
670 | } | |
671 | base = CIR_BASE; | |
e1fee94f OS |
672 | |
673 | superio_select(CIR); | |
674 | superio_outw(base, BASEREG); | |
675 | superio_outb(0x00, CIR_ILS); | |
676 | ciract = superio_inb(ACTREG); | |
677 | superio_outb(0x01, ACTREG); | |
a134b825 | 678 | if (gp_rreq_fail) { |
e1fee94f OS |
679 | superio_select(GAMEPORT); |
680 | superio_outb(gpact, ACTREG); | |
681 | } | |
e1fee94f OS |
682 | } |
683 | ||
dfb0b8ea | 684 | if (timeout < 1 || timeout > max_units * 60) { |
e1fee94f | 685 | timeout = DEFAULT_TIMEOUT; |
27c766aa JP |
686 | pr_warn("Timeout value out of range, use default %d sec\n", |
687 | DEFAULT_TIMEOUT); | |
e1fee94f OS |
688 | } |
689 | ||
dfb0b8ea OZ |
690 | if (timeout > max_units) |
691 | timeout = wdt_round_time(timeout); | |
692 | ||
e1fee94f OS |
693 | rc = register_reboot_notifier(&wdt_notifier); |
694 | if (rc) { | |
27c766aa | 695 | pr_err("Cannot register reboot notifier (err=%d)\n", rc); |
e1fee94f OS |
696 | goto err_out_region; |
697 | } | |
698 | ||
699 | rc = misc_register(&wdt_miscdev); | |
700 | if (rc) { | |
27c766aa JP |
701 | pr_err("Cannot register miscdev on minor=%d (err=%d)\n", |
702 | wdt_miscdev.minor, rc); | |
e1fee94f OS |
703 | goto err_out_reboot; |
704 | } | |
705 | ||
706 | /* Initialize CIR to use it as keepalive source */ | |
707 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
708 | outb(0x00, CIR_RCR(base)); | |
709 | outb(0xc0, CIR_TCR1(base)); | |
710 | outb(0x5c, CIR_TCR2(base)); | |
711 | outb(0x10, CIR_IER(base)); | |
712 | outb(0x00, CIR_BDHR(base)); | |
713 | outb(0x01, CIR_BDLR(base)); | |
714 | outb(0x09, CIR_IER(base)); | |
715 | } | |
716 | ||
27c766aa JP |
717 | pr_info("Chip IT%04x revision %d initialized. timeout=%d sec (nowayout=%d testmode=%d exclusive=%d nogameport=%d)\n", |
718 | chip_type, chip_rev, timeout, | |
e1fee94f OS |
719 | nowayout, testmode, exclusive, nogameport); |
720 | ||
a134b825 | 721 | superio_exit(); |
e1fee94f OS |
722 | return 0; |
723 | ||
724 | err_out_reboot: | |
725 | unregister_reboot_notifier(&wdt_notifier); | |
726 | err_out_region: | |
727 | release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8); | |
728 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
e1fee94f OS |
729 | superio_select(CIR); |
730 | superio_outb(ciract, ACTREG); | |
e1fee94f OS |
731 | } |
732 | err_out: | |
ee3e9658 | 733 | if (try_gameport) { |
e1fee94f OS |
734 | superio_select(GAMEPORT); |
735 | superio_outb(gpact, ACTREG); | |
e1fee94f OS |
736 | } |
737 | ||
a134b825 | 738 | superio_exit(); |
e1fee94f OS |
739 | return rc; |
740 | } | |
741 | ||
742 | static void __exit it87_wdt_exit(void) | |
743 | { | |
a134b825 NG |
744 | if (superio_enter() == 0) { |
745 | superio_select(GPIO); | |
746 | superio_outb(0x00, WDTCTRL); | |
747 | superio_outb(0x00, WDTCFG); | |
748 | superio_outb(0x00, WDTVALLSB); | |
749 | if (max_units > 255) | |
750 | superio_outb(0x00, WDTVALMSB); | |
751 | if (test_bit(WDTS_USE_GP, &wdt_status)) { | |
752 | superio_select(GAMEPORT); | |
753 | superio_outb(gpact, ACTREG); | |
754 | } else { | |
755 | superio_select(CIR); | |
756 | superio_outb(ciract, ACTREG); | |
757 | } | |
758 | superio_exit(); | |
e1fee94f | 759 | } |
e1fee94f OS |
760 | |
761 | misc_deregister(&wdt_miscdev); | |
762 | unregister_reboot_notifier(&wdt_notifier); | |
763 | release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8); | |
764 | } | |
765 | ||
766 | module_init(it87_wdt_init); | |
767 | module_exit(it87_wdt_exit); | |
768 | ||
769 | MODULE_AUTHOR("Oliver Schuster"); | |
770 | MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O"); | |
771 | MODULE_LICENSE("GPL"); | |
772 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |