[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / lantiq_wdt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 *  Copyright (C) 2010 John Crispin <john@phrozen.org>
 *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
 *  Based on EP93xx wdt driver
 */

#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/watchdog.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <lantiq_soc.h>

#define LTQ_XRX_RCU_RST_STAT		0x0014
#define LTQ_XRX_RCU_RST_STAT_WDT	BIT(31)

/* CPU0 Reset Source Register */
#define LTQ_FALCON_SYS1_CPU0RS		0x0060
/* reset cause mask */
#define LTQ_FALCON_SYS1_CPU0RS_MASK	0x0007
#define LTQ_FALCON_SYS1_CPU0RS_WDT	0x02

/*
 * Section 3.4 of the datasheet
 * The password sequence protects the WDT control register from unintended
 * write actions, which might cause malfunction of the WDT.
 *
 * essentially the following two magic passwords need to be written to allow
 * IO access to the WDT core
 */
#define LTQ_WDT_CR_PW1		0x00BE0000
#define LTQ_WDT_CR_PW2		0x00DC0000

#define LTQ_WDT_CR		0x0		/* watchdog control register */
#define  LTQ_WDT_CR_GEN		BIT(31)		/* enable bit */
/* Pre-warning limit set to 1/16 of max WDT period */
#define  LTQ_WDT_CR_PWL		(0x3 << 26)
/* set clock divider to 0x40000 */
#define  LTQ_WDT_CR_CLKDIV	(0x3 << 24)
#define  LTQ_WDT_CR_PW_MASK	GENMASK(23, 16)	/* Password field */
#define  LTQ_WDT_CR_MAX_TIMEOUT	((1 << 16) - 1)	/* The reload field is 16 bit */
#define LTQ_WDT_SR		0x8		/* watchdog status register */
#define  LTQ_WDT_SR_EN		BIT(31)		/* Enable */
#define  LTQ_WDT_SR_VALUE_MASK	GENMASK(15, 0)	/* Timer value */

#define LTQ_WDT_DIVIDER		0x40000

static bool nowayout = WATCHDOG_NOWAYOUT;

struct ltq_wdt_hw {
	int (*bootstatus_get)(struct device *dev);
};

struct ltq_wdt_priv {
	struct watchdog_device wdt;
	void __iomem *membase;
	unsigned long clk_rate;
};

static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
{
	return __raw_readl(priv->membase + offset);
}

static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
{
	__raw_writel(val, priv->membase + offset);
}

static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
			 u32 offset)
{
	u32 val = ltq_wdt_r32(priv, offset);

	val &= ~(clear);
	val |= set;
	ltq_wdt_w32(priv, val, offset);
}

static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
{
	return container_of(wdt, struct ltq_wdt_priv, wdt);
}

static struct watchdog_info ltq_wdt_info = {
	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
		   WDIOF_CARDRESET,
	.identity = "ltq_wdt",
};

static int ltq_wdt_start(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u32 timeout;

	timeout = wdt->timeout * priv->clk_rate;

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	/* write the second magic plus the configuration and new timeout */
	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
		     LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
		     LTQ_WDT_CR_PW2 | timeout,
		     LTQ_WDT_CR);

	return 0;
}

static int ltq_wdt_stop(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
		     LTQ_WDT_CR_PW2, LTQ_WDT_CR);

	return 0;
}

static int ltq_wdt_ping(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u32 timeout;

	timeout = wdt->timeout * priv->clk_rate;

	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	/* write the second magic plus the configuration and new timeout */
	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
		     LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);

	return 0;
}

static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
{
	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	u64 timeout;

	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
	return do_div(timeout, priv->clk_rate);
}

static const struct watchdog_ops ltq_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= ltq_wdt_start,
	.stop		= ltq_wdt_stop,
	.ping		= ltq_wdt_ping,
	.get_timeleft	= ltq_wdt_get_timeleft,
};

static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
{
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	if (err)
		return err;

	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
		return WDIOF_CARDRESET;

	return 0;
}

static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
{
	struct regmap *rcu_regmap;
	u32 val;
	int err;

	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
						     "lantiq,rcu");
	if (IS_ERR(rcu_regmap))
		return PTR_ERR(rcu_regmap);

	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	if (err)
		return err;

	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
		return WDIOF_CARDRESET;

	return 0;
}

static int ltq_wdt_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ltq_wdt_priv *priv;
	struct watchdog_device *wdt;
	struct clk *clk;
	const struct ltq_wdt_hw *ltq_wdt_hw;
	int ret;
	u32 status;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->membase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->membase))
		return PTR_ERR(priv->membase);

	/* we do not need to enable the clock as it is always running */
	clk = clk_get_io();
	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
	if (!priv->clk_rate) {
		dev_err(dev, "clock rate less than divider %i\n",
			LTQ_WDT_DIVIDER);
		return -EINVAL;
	}

	wdt = &priv->wdt;
	wdt->info		= &ltq_wdt_info;
	wdt->ops		= &ltq_wdt_ops;
	wdt->min_timeout	= 1;
	wdt->max_timeout	= LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
	wdt->timeout		= wdt->max_timeout;
	wdt->parent		= dev;

	ltq_wdt_hw = of_device_get_match_data(dev);
	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
		ret = ltq_wdt_hw->bootstatus_get(dev);
		if (ret >= 0)
			wdt->bootstatus = ret;
	}

	watchdog_set_nowayout(wdt, nowayout);
	watchdog_init_timeout(wdt, 0, dev);

	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
	if (status & LTQ_WDT_SR_EN) {
		/*
		 * If the watchdog is already running overwrite it with our
		 * new settings. Stop is not needed as the start call will
		 * replace all settings anyway.
		 */
		ltq_wdt_start(wdt);
		set_bit(WDOG_HW_RUNNING, &wdt->status);
	}

	return devm_watchdog_register_device(dev, wdt);
}

static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
};

static const struct ltq_wdt_hw ltq_wdt_falcon = {
	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
};

static const struct of_device_id ltq_wdt_match[] = {
	{ .compatible = "lantiq,wdt", .data = NULL },
	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
	{},
};
MODULE_DEVICE_TABLE(of, ltq_wdt_match);

static struct platform_driver ltq_wdt_driver = {
	.probe = ltq_wdt_probe,
	.driver = {
		.name = "wdt",
		.of_match_table = ltq_wdt_match,
	},
};

module_platform_driver(ltq_wdt_driver);

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
MODULE_AUTHOR("John Crispin <john@phrozen.org>");
MODULE_DESCRIPTION("Lantiq SoC Watchdog");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
2f58b8d0	2	/*
2f58b8d0	3	*
f3519a66	4	* Copyright (C) 2010 John Crispin <john@phrozen.org>
710322ba	5	* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
2f58b8d0 JC	6	* Based on EP93xx wdt driver
	7	*/
	8
	9	#include <linux/module.h>
1f59f8af	10	#include <linux/bitops.h>
2f58b8d0	11	#include <linux/watchdog.h>
cdb86121	12	#include <linux/of_platform.h>
2f58b8d0 JC	13	#include <linux/uaccess.h>
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
710322ba HM	16	#include <linux/regmap.h>
710322ba HM	17	#include <linux/mfd/syscon.h>
2f58b8d0	18
cdb86121	19	#include <lantiq_soc.h>
2f58b8d0	20
710322ba HM	21	#define LTQ_XRX_RCU_RST_STAT 0x0014
	22	#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
	23
	24	/* CPU0 Reset Source Register */
	25	#define LTQ_FALCON_SYS1_CPU0RS 0x0060
	26	/* reset cause mask */
	27	#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
	28	#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
	29
cdb86121 JC	30	/*
cdb86121 JC	31	* Section 3.4 of the datasheet
2f58b8d0 JC	32	* The password sequence protects the WDT control register from unintended
	33	* write actions, which might cause malfunction of the WDT.
	34	*
	35	* essentially the following two magic passwords need to be written to allow
	36	* IO access to the WDT core
	37	*/
1f59f8af HM	38	#define LTQ_WDT_CR_PW1 0x00BE0000
	39	#define LTQ_WDT_CR_PW2 0x00DC0000
	40
	41	#define LTQ_WDT_CR 0x0 /* watchdog control register */
	42	#define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
	43	/* Pre-warning limit set to 1/16 of max WDT period */
	44	#define LTQ_WDT_CR_PWL (0x3 << 26)
	45	/* set clock divider to 0x40000 */
	46	#define LTQ_WDT_CR_CLKDIV (0x3 << 24)
	47	#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
	48	#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
dcd7e04e HM	49	#define LTQ_WDT_SR 0x8 /* watchdog status register */
dcd7e04e HM	50	#define LTQ_WDT_SR_EN BIT(31) /* Enable */
c99d9df1	51	#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
2f58b8d0	52
2f58b8d0	53	#define LTQ_WDT_DIVIDER 0x40000
2f58b8d0	54
86a1e189	55	static bool nowayout = WATCHDOG_NOWAYOUT;
2f58b8d0	56
dcd7e04e HM	57	struct ltq_wdt_hw {
	58	int (bootstatus_get)(struct device dev);
	59	};
2f58b8d0	60
dcd7e04e HM	61	struct ltq_wdt_priv {
	62	struct watchdog_device wdt;
	63	void __iomem *membase;
	64	unsigned long clk_rate;
	65	};
2f58b8d0	66
dcd7e04e	67	static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
2f58b8d0	68	{
dcd7e04e	69	return __raw_readl(priv->membase + offset);
2f58b8d0 JC	70	}
2f58b8d0 JC	71
dcd7e04e	72	static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
2f58b8d0	73	{
dcd7e04e	74	__raw_writel(val, priv->membase + offset);
2f58b8d0 JC	75	}
2f58b8d0 JC	76
dcd7e04e HM	77	static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
dcd7e04e HM	78	u32 offset)
2f58b8d0	79	{
dcd7e04e HM	80	u32 val = ltq_wdt_r32(priv, offset);
	81
	82	val &= ~(clear);
	83	val \|= set;
	84	ltq_wdt_w32(priv, val, offset);
	85	}
2f58b8d0	86
dcd7e04e HM	87	static struct ltq_wdt_priv ltq_wdt_get_priv(struct watchdog_device wdt)
	88	{
	89	return container_of(wdt, struct ltq_wdt_priv, wdt);
2f58b8d0 JC	90	}
2f58b8d0 JC	91
dcd7e04e	92	static struct watchdog_info ltq_wdt_info = {
2f58b8d0	93	.options = WDIOF_MAGICCLOSE \| WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \|
dcd7e04e	94	WDIOF_CARDRESET,
2f58b8d0 JC	95	.identity = "ltq_wdt",
	96	};
	97
dcd7e04e	98	static int ltq_wdt_start(struct watchdog_device *wdt)
2f58b8d0	99	{
dcd7e04e HM	100	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	101	u32 timeout;
	102
	103	timeout = wdt->timeout * priv->clk_rate;
	104
	105	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	106	/* write the second magic plus the configuration and new timeout */
	107	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK \| LTQ_WDT_CR_MAX_TIMEOUT,
	108	LTQ_WDT_CR_GEN \| LTQ_WDT_CR_PWL \| LTQ_WDT_CR_CLKDIV \|
	109	LTQ_WDT_CR_PW2 \| timeout,
	110	LTQ_WDT_CR);
	111
	112	return 0;
2f58b8d0 JC	113	}
2f58b8d0 JC	114
dcd7e04e	115	static int ltq_wdt_stop(struct watchdog_device *wdt)
2f58b8d0	116	{
dcd7e04e HM	117	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	118
	119	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	120	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN \| LTQ_WDT_CR_PW_MASK,
	121	LTQ_WDT_CR_PW2, LTQ_WDT_CR);
2f58b8d0	122
dcd7e04e	123	return 0;
2f58b8d0 JC	124	}
2f58b8d0 JC	125
dcd7e04e	126	static int ltq_wdt_ping(struct watchdog_device *wdt)
2f58b8d0	127	{
dcd7e04e HM	128	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	129	u32 timeout;
	130
	131	timeout = wdt->timeout * priv->clk_rate;
	132
	133	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
	134	/* write the second magic plus the configuration and new timeout */
	135	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK \| LTQ_WDT_CR_MAX_TIMEOUT,
	136	LTQ_WDT_CR_PW2 \| timeout, LTQ_WDT_CR);
2f58b8d0 JC	137
	138	return 0;
	139	}
	140
c99d9df1 HM	141	static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
	142	{
	143	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
	144	u64 timeout;
	145
	146	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
	147	return do_div(timeout, priv->clk_rate);
	148	}
	149
dcd7e04e	150	static const struct watchdog_ops ltq_wdt_ops = {
2f58b8d0	151	.owner = THIS_MODULE,
dcd7e04e HM	152	.start = ltq_wdt_start,
	153	.stop = ltq_wdt_stop,
	154	.ping = ltq_wdt_ping,
c99d9df1	155	.get_timeleft = ltq_wdt_get_timeleft,
2f58b8d0 JC	156	};
2f58b8d0 JC	157
dcd7e04e	158	static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
710322ba	159	{
710322ba HM	160	struct regmap *rcu_regmap;
	161	u32 val;
	162	int err;
	163
	164	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
	165	if (IS_ERR(rcu_regmap))
	166	return PTR_ERR(rcu_regmap);
	167
	168	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
	169	if (err)
	170	return err;
	171
	172	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
dcd7e04e	173	return WDIOF_CARDRESET;
710322ba HM	174
	175	return 0;
	176	}
	177
dcd7e04e	178	static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
710322ba	179	{
710322ba HM	180	struct regmap *rcu_regmap;
	181	u32 val;
	182	int err;
	183
	184	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
	185	"lantiq,rcu");
	186	if (IS_ERR(rcu_regmap))
	187	return PTR_ERR(rcu_regmap);
	188
	189	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
	190	if (err)
	191	return err;
	192
	193	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
dcd7e04e	194	return WDIOF_CARDRESET;
710322ba HM	195
	196	return 0;
	197	}
	198
dcd7e04e	199	static int ltq_wdt_probe(struct platform_device *pdev)
2f58b8d0	200	{
dcd7e04e HM	201	struct device *dev = &pdev->dev;
	202	struct ltq_wdt_priv *priv;
	203	struct watchdog_device *wdt;
2f58b8d0	204	struct clk *clk;
dcd7e04e	205	const struct ltq_wdt_hw *ltq_wdt_hw;
710322ba	206	int ret;
dcd7e04e	207	u32 status;
2f58b8d0	208
dcd7e04e HM	209	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	210	if (!priv)
	211	return -ENOMEM;
2f58b8d0	212
0f0a6a28	213	priv->membase = devm_platform_ioremap_resource(pdev, 0);
dcd7e04e HM	214	if (IS_ERR(priv->membase))
dcd7e04e HM	215	return PTR_ERR(priv->membase);
710322ba	216
2f58b8d0	217	/* we do not need to enable the clock as it is always running */
cdb86121	218	clk = clk_get_io();
dcd7e04e HM	219	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
	220	if (!priv->clk_rate) {
	221	dev_err(dev, "clock rate less than divider %i\n",
	222	LTQ_WDT_DIVIDER);
	223	return -EINVAL;
cdb86121	224	}
2f58b8d0	225
dcd7e04e HM	226	wdt = &priv->wdt;
	227	wdt->info = &ltq_wdt_info;
	228	wdt->ops = &ltq_wdt_ops;
	229	wdt->min_timeout = 1;
	230	wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
	231	wdt->timeout = wdt->max_timeout;
	232	wdt->parent = dev;
	233
	234	ltq_wdt_hw = of_device_get_match_data(dev);
	235	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
	236	ret = ltq_wdt_hw->bootstatus_get(dev);
	237	if (ret >= 0)
	238	wdt->bootstatus = ret;
	239	}
2f58b8d0	240
dcd7e04e HM	241	watchdog_set_nowayout(wdt, nowayout);
	242	watchdog_init_timeout(wdt, 0, dev);
	243
	244	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
	245	if (status & LTQ_WDT_SR_EN) {
	246	/*
	247	* If the watchdog is already running overwrite it with our
	248	* new settings. Stop is not needed as the start call will
	249	* replace all settings anyway.
	250	*/
	251	ltq_wdt_start(wdt);
	252	set_bit(WDOG_HW_RUNNING, &wdt->status);
	253	}
2f58b8d0	254
dcd7e04e	255	return devm_watchdog_register_device(dev, wdt);
2f58b8d0 JC	256	}
2f58b8d0 JC	257
dcd7e04e HM	258	static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
	259	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
	260	};
	261
	262	static const struct ltq_wdt_hw ltq_wdt_falcon = {
	263	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
	264	};
	265
cdb86121	266	static const struct of_device_id ltq_wdt_match[] = {
dcd7e04e HM	267	{ .compatible = "lantiq,wdt", .data = NULL },
	268	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
	269	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
cdb86121 JC	270	{},
	271	};
	272	MODULE_DEVICE_TABLE(of, ltq_wdt_match);
2f58b8d0 JC	273
2f58b8d0 JC	274	static struct platform_driver ltq_wdt_driver = {
cdb86121	275	.probe = ltq_wdt_probe,
2f58b8d0	276	.driver = {
cdb86121	277	.name = "wdt",
cdb86121	278	.of_match_table = ltq_wdt_match,
2f58b8d0 JC	279	},
	280	};
	281
cdb86121	282	module_platform_driver(ltq_wdt_driver);
2f58b8d0	283
86a1e189	284	module_param(nowayout, bool, 0);
2f58b8d0	285	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
f3519a66	286	MODULE_AUTHOR("John Crispin <john@phrozen.org>");
2f58b8d0 JC	287	MODULE_DESCRIPTION("Lantiq SoC Watchdog");
2f58b8d0 JC	288	MODULE_LICENSE("GPL");