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1/*
2 * drivers/char/watchdog/max63xx_wdt.c
3 *
4 * Driver for max63{69,70,71,72,73,74} watchdog timers
5 *
6 * Copyright (C) 2009 Marc Zyngier <maz@misterjones.org>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * This driver assumes the watchdog pins are memory mapped (as it is
13 * the case for the Arcom Zeus). Should it be connected over GPIOs or
14 * another interface, some abstraction will have to be introduced.
15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
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21#include <linux/miscdevice.h>
22#include <linux/watchdog.h>
23#include <linux/init.h>
24#include <linux/bitops.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
66aaa7a5 27#include <linux/io.h>
5a0e3ad6 28#include <linux/slab.h>
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29
30#define DEFAULT_HEARTBEAT 60
31#define MAX_HEARTBEAT 60
32
a0f36833 33static unsigned int heartbeat = DEFAULT_HEARTBEAT;
86a1e189 34static bool nowayout = WATCHDOG_NOWAYOUT;
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35
36/*
37 * Memory mapping: a single byte, 3 first lower bits to select bit 3
38 * to ping the watchdog.
39 */
40#define MAX6369_WDSET (7 << 0)
5f3b2756 41#define MAX6369_WDI (1 << 3)
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42
43static DEFINE_SPINLOCK(io_lock);
44
66aaa7a5 45static int nodelay;
66aaa7a5 46static void __iomem *wdt_base;
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47
48/*
49 * The timeout values used are actually the absolute minimum the chip
50 * offers. Typical values on my board are slightly over twice as long
51 * (10s setting ends up with a 25s timeout), and can be up to 3 times
52 * the nominal setting (according to the datasheet). So please take
53 * these values with a grain of salt. Same goes for the initial delay
54 * "feature". Only max6373/74 have a few settings without this initial
55 * delay (selected with the "nodelay" parameter).
56 *
57 * I also decided to remove from the tables any timeout smaller than a
58 * second, as it looked completly overkill...
59 */
60
61/* Timeouts in second */
62struct max63xx_timeout {
63 u8 wdset;
64 u8 tdelay;
65 u8 twd;
66};
67
68static struct max63xx_timeout max6369_table[] = {
69 { 5, 1, 1 },
70 { 6, 10, 10 },
71 { 7, 60, 60 },
72 { },
73};
74
75static struct max63xx_timeout max6371_table[] = {
76 { 6, 60, 3 },
77 { 7, 60, 60 },
78 { },
79};
80
81static struct max63xx_timeout max6373_table[] = {
82 { 2, 60, 1 },
83 { 5, 0, 1 },
84 { 1, 3, 3 },
85 { 7, 60, 10 },
86 { 6, 0, 10 },
87 { },
88};
89
90static struct max63xx_timeout *current_timeout;
91
92static struct max63xx_timeout *
93max63xx_select_timeout(struct max63xx_timeout *table, int value)
94{
95 while (table->twd) {
96 if (value <= table->twd) {
97 if (nodelay && table->tdelay == 0)
98 return table;
99
100 if (!nodelay)
101 return table;
102 }
103
104 table++;
105 }
106
107 return NULL;
108}
109
a0f36833 110static int max63xx_wdt_ping(struct watchdog_device *wdd)
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111{
112 u8 val;
113
114 spin_lock(&io_lock);
115
116 val = __raw_readb(wdt_base);
117
118 __raw_writeb(val | MAX6369_WDI, wdt_base);
119 __raw_writeb(val & ~MAX6369_WDI, wdt_base);
120
121 spin_unlock(&io_lock);
a0f36833 122 return 0;
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123}
124
a0f36833 125static int max63xx_wdt_start(struct watchdog_device *wdd)
66aaa7a5 126{
a0f36833 127 struct max63xx_timeout *entry = watchdog_get_drvdata(wdd);
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128 u8 val;
129
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130 spin_lock(&io_lock);
131
132 val = __raw_readb(wdt_base);
133 val &= ~MAX6369_WDSET;
134 val |= entry->wdset;
135 __raw_writeb(val, wdt_base);
136
137 spin_unlock(&io_lock);
138
139 /* check for a edge triggered startup */
140 if (entry->tdelay == 0)
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141 max63xx_wdt_ping(wdd);
142 return 0;
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143}
144
a0f36833 145static int max63xx_wdt_stop(struct watchdog_device *wdd)
66aaa7a5 146{
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147 u8 val;
148
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149 spin_lock(&io_lock);
150
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151 val = __raw_readb(wdt_base);
152 val &= ~MAX6369_WDSET;
153 val |= 3;
154 __raw_writeb(val, wdt_base);
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155
156 spin_unlock(&io_lock);
a0f36833 157 return 0;
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158}
159
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160static const struct watchdog_info max63xx_wdt_info = {
161 .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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162 .identity = "max63xx Watchdog",
163};
164
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165static const struct watchdog_ops max63xx_wdt_ops = {
166 .owner = THIS_MODULE,
167 .start = max63xx_wdt_start,
168 .stop = max63xx_wdt_stop,
169 .ping = max63xx_wdt_ping,
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170};
171
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172static struct watchdog_device max63xx_wdt_dev = {
173 .info = &max63xx_wdt_info,
174 .ops = &max63xx_wdt_ops,
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175};
176
177static int __devinit max63xx_wdt_probe(struct platform_device *pdev)
178{
a0f36833 179 struct resource *wdt_mem;
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180 struct max63xx_timeout *table;
181
182 table = (struct max63xx_timeout *)pdev->id_entry->driver_data;
183
184 if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
185 heartbeat = DEFAULT_HEARTBEAT;
186
a0f36833 187 dev_info(&pdev->dev, "requesting %ds heartbeat\n", heartbeat);
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188 current_timeout = max63xx_select_timeout(table, heartbeat);
189
190 if (!current_timeout) {
a0f36833 191 dev_err(&pdev->dev, "unable to satisfy heartbeat request\n");
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192 return -EINVAL;
193 }
194
a0f36833 195 dev_info(&pdev->dev, "using %ds heartbeat with %ds initial delay\n",
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196 current_timeout->twd, current_timeout->tdelay);
197
198 heartbeat = current_timeout->twd;
199
f712eacf 200 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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201 wdt_base = devm_request_and_ioremap(&pdev->dev, wdt_mem);
202 if (!wdt_base)
203 return -ENOMEM;
66aaa7a5 204
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205 max63xx_wdt_dev.timeout = heartbeat;
206 watchdog_set_nowayout(&max63xx_wdt_dev, nowayout);
207 watchdog_set_drvdata(&max63xx_wdt_dev, current_timeout);
66aaa7a5 208
a0f36833 209 return watchdog_register_device(&max63xx_wdt_dev);
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210}
211
212static int __devexit max63xx_wdt_remove(struct platform_device *pdev)
213{
a0f36833 214 watchdog_unregister_device(&max63xx_wdt_dev);
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215 return 0;
216}
217
218static struct platform_device_id max63xx_id_table[] = {
219 { "max6369_wdt", (kernel_ulong_t)max6369_table, },
220 { "max6370_wdt", (kernel_ulong_t)max6369_table, },
221 { "max6371_wdt", (kernel_ulong_t)max6371_table, },
222 { "max6372_wdt", (kernel_ulong_t)max6371_table, },
223 { "max6373_wdt", (kernel_ulong_t)max6373_table, },
224 { "max6374_wdt", (kernel_ulong_t)max6373_table, },
225 { },
226};
227MODULE_DEVICE_TABLE(platform, max63xx_id_table);
228
229static struct platform_driver max63xx_wdt_driver = {
230 .probe = max63xx_wdt_probe,
231 .remove = __devexit_p(max63xx_wdt_remove),
232 .id_table = max63xx_id_table,
233 .driver = {
234 .name = "max63xx_wdt",
235 .owner = THIS_MODULE,
236 },
237};
238
b8ec6118 239module_platform_driver(max63xx_wdt_driver);
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240
241MODULE_AUTHOR("Marc Zyngier <maz@misterjones.org>");
242MODULE_DESCRIPTION("max63xx Watchdog Driver");
243
244module_param(heartbeat, int, 0);
245MODULE_PARM_DESC(heartbeat,
246 "Watchdog heartbeat period in seconds from 1 to "
247 __MODULE_STRING(MAX_HEARTBEAT) ", default "
248 __MODULE_STRING(DEFAULT_HEARTBEAT));
249
86a1e189 250module_param(nowayout, bool, 0);
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251MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
252 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
253
254module_param(nodelay, int, 0);
255MODULE_PARM_DESC(nodelay,
256 "Force selection of a timeout setting without initial delay "
257 "(max6373/74 only, default=0)");
258
259MODULE_LICENSE("GPL");
260MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);