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Commit | Line | Data |
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fabbfb9e | 1 | /* |
0d7b1014 | 2 | * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface |
fabbfb9e KG |
3 | * |
4 | * Authors: Dave Updegraff <dave@cray.org> | |
5f3b2756 WVS |
5 | * Kumar Gala <galak@kernel.crashing.org> |
6 | * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org> | |
7 | * ..and from sc520_wdt | |
500c919e AV |
8 | * Copyright (c) 2008 MontaVista Software, Inc. |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
fabbfb9e KG |
10 | * |
11 | * Note: it appears that you can only actually ENABLE or DISABLE the thing | |
12 | * once after POR. Once enabled, you cannot disable, and vice versa. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of the GNU General Public License as published by the | |
16 | * Free Software Foundation; either version 2 of the License, or (at your | |
17 | * option) any later version. | |
18 | */ | |
19 | ||
27c766aa JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
fabbfb9e KG |
22 | #include <linux/fs.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
500c919e | 25 | #include <linux/timer.h> |
fabbfb9e | 26 | #include <linux/miscdevice.h> |
5af50730 | 27 | #include <linux/of_address.h> |
ef8ab12e | 28 | #include <linux/of_platform.h> |
fabbfb9e KG |
29 | #include <linux/module.h> |
30 | #include <linux/watchdog.h> | |
f26ef3dc AC |
31 | #include <linux/io.h> |
32 | #include <linux/uaccess.h> | |
ef8ab12e | 33 | #include <sysdev/fsl_soc.h> |
fabbfb9e | 34 | |
59ca1b0d | 35 | struct mpc8xxx_wdt { |
fabbfb9e KG |
36 | __be32 res0; |
37 | __be32 swcrr; /* System watchdog control register */ | |
38 | #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ | |
39 | #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ | |
40 | #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ | |
41 | #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ | |
42 | __be32 swcnr; /* System watchdog count register */ | |
43 | u8 res1[2]; | |
44 | __be16 swsrr; /* System watchdog service register */ | |
45 | u8 res2[0xF0]; | |
46 | }; | |
47 | ||
59ca1b0d | 48 | struct mpc8xxx_wdt_type { |
500c919e AV |
49 | int prescaler; |
50 | bool hw_enabled; | |
51 | }; | |
52 | ||
59ca1b0d | 53 | static struct mpc8xxx_wdt __iomem *wd_base; |
593fc178 | 54 | static int mpc8xxx_wdt_init_late(void); |
fabbfb9e KG |
55 | |
56 | static u16 timeout = 0xffff; | |
57 | module_param(timeout, ushort, 0); | |
f26ef3dc | 58 | MODULE_PARM_DESC(timeout, |
76550d32 | 59 | "Watchdog timeout in ticks. (0<timeout<65536, default=65535)"); |
fabbfb9e | 60 | |
90ab5ee9 | 61 | static bool reset = 1; |
fabbfb9e | 62 | module_param(reset, bool, 0); |
f26ef3dc AC |
63 | MODULE_PARM_DESC(reset, |
64 | "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset"); | |
fabbfb9e | 65 | |
86a1e189 WVS |
66 | static bool nowayout = WATCHDOG_NOWAYOUT; |
67 | module_param(nowayout, bool, 0); | |
500c919e AV |
68 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
69 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
70 | ||
c7dfd0cc | 71 | static DEFINE_SPINLOCK(wdt_spinlock); |
fabbfb9e | 72 | |
59ca1b0d | 73 | static void mpc8xxx_wdt_keepalive(void) |
fabbfb9e KG |
74 | { |
75 | /* Ping the WDT */ | |
76 | spin_lock(&wdt_spinlock); | |
77 | out_be16(&wd_base->swsrr, 0x556c); | |
78 | out_be16(&wd_base->swsrr, 0xaa39); | |
79 | spin_unlock(&wdt_spinlock); | |
80 | } | |
81 | ||
d5cfaf0a | 82 | static struct watchdog_device mpc8xxx_wdt_dev; |
59ca1b0d | 83 | static void mpc8xxx_wdt_timer_ping(unsigned long arg); |
d5cfaf0a CL |
84 | static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0, |
85 | (unsigned long)&mpc8xxx_wdt_dev); | |
500c919e | 86 | |
59ca1b0d | 87 | static void mpc8xxx_wdt_timer_ping(unsigned long arg) |
500c919e | 88 | { |
d5cfaf0a CL |
89 | struct watchdog_device *w = (struct watchdog_device *)arg; |
90 | ||
59ca1b0d | 91 | mpc8xxx_wdt_keepalive(); |
500c919e | 92 | /* We're pinging it twice faster than needed, just to be sure. */ |
d5cfaf0a | 93 | mod_timer(&wdt_timer, jiffies + HZ * w->timeout / 2); |
500c919e AV |
94 | } |
95 | ||
d5cfaf0a | 96 | static int mpc8xxx_wdt_start(struct watchdog_device *w) |
fabbfb9e | 97 | { |
a57e06f7 | 98 | u32 tmp = SWCRR_SWEN | SWCRR_SWPR; |
fabbfb9e KG |
99 | |
100 | /* Good, fire up the show */ | |
fabbfb9e KG |
101 | if (reset) |
102 | tmp |= SWCRR_SWRI; | |
103 | ||
104 | tmp |= timeout << 16; | |
105 | ||
106 | out_be32(&wd_base->swcrr, tmp); | |
107 | ||
500c919e AV |
108 | del_timer_sync(&wdt_timer); |
109 | ||
d5cfaf0a | 110 | return 0; |
fabbfb9e KG |
111 | } |
112 | ||
d5cfaf0a | 113 | static int mpc8xxx_wdt_ping(struct watchdog_device *w) |
fabbfb9e | 114 | { |
d5cfaf0a | 115 | mpc8xxx_wdt_keepalive(); |
fabbfb9e KG |
116 | return 0; |
117 | } | |
118 | ||
d5cfaf0a | 119 | static int mpc8xxx_wdt_stop(struct watchdog_device *w) |
fabbfb9e | 120 | { |
d5cfaf0a CL |
121 | mod_timer(&wdt_timer, jiffies); |
122 | return 0; | |
fabbfb9e KG |
123 | } |
124 | ||
d5cfaf0a CL |
125 | static struct watchdog_info mpc8xxx_wdt_info = { |
126 | .options = WDIOF_KEEPALIVEPING, | |
127 | .firmware_version = 1, | |
128 | .identity = "MPC8xxx", | |
fabbfb9e KG |
129 | }; |
130 | ||
d5cfaf0a CL |
131 | static struct watchdog_ops mpc8xxx_wdt_ops = { |
132 | .owner = THIS_MODULE, | |
133 | .start = mpc8xxx_wdt_start, | |
134 | .ping = mpc8xxx_wdt_ping, | |
135 | .stop = mpc8xxx_wdt_stop, | |
136 | }; | |
137 | ||
138 | static struct watchdog_device mpc8xxx_wdt_dev = { | |
139 | .info = &mpc8xxx_wdt_info, | |
140 | .ops = &mpc8xxx_wdt_ops, | |
fabbfb9e KG |
141 | }; |
142 | ||
b1608d69 | 143 | static const struct of_device_id mpc8xxx_wdt_match[]; |
2d991a16 | 144 | static int mpc8xxx_wdt_probe(struct platform_device *ofdev) |
fabbfb9e | 145 | { |
fabbfb9e | 146 | int ret; |
b1608d69 | 147 | const struct of_device_id *match; |
de2b606c | 148 | struct device_node *np = ofdev->dev.of_node; |
639397e4 | 149 | const struct mpc8xxx_wdt_type *wdt_type; |
ef8ab12e | 150 | u32 freq = fsl_get_sys_freq(); |
500c919e | 151 | bool enabled; |
d5cfaf0a | 152 | unsigned int timeout_sec; |
fabbfb9e | 153 | |
b1608d69 GL |
154 | match = of_match_device(mpc8xxx_wdt_match, &ofdev->dev); |
155 | if (!match) | |
1c48a5c9 | 156 | return -EINVAL; |
b1608d69 | 157 | wdt_type = match->data; |
1c48a5c9 | 158 | |
ef8ab12e AV |
159 | if (!freq || freq == -1) |
160 | return -EINVAL; | |
fabbfb9e | 161 | |
500c919e | 162 | wd_base = of_iomap(np, 0); |
ef8ab12e AV |
163 | if (!wd_base) |
164 | return -ENOMEM; | |
fabbfb9e | 165 | |
500c919e AV |
166 | enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; |
167 | if (!enabled && wdt_type->hw_enabled) { | |
27c766aa | 168 | pr_info("could not be enabled in software\n"); |
500c919e AV |
169 | ret = -ENOSYS; |
170 | goto err_unmap; | |
171 | } | |
172 | ||
fabbfb9e | 173 | /* Calculate the timeout in seconds */ |
a57e06f7 | 174 | timeout_sec = (timeout * wdt_type->prescaler) / freq; |
fabbfb9e | 175 | |
d5cfaf0a | 176 | mpc8xxx_wdt_dev.timeout = timeout_sec; |
593fc178 AV |
177 | #ifdef MODULE |
178 | ret = mpc8xxx_wdt_init_late(); | |
179 | if (ret) | |
180 | goto err_unmap; | |
181 | #endif | |
182 | ||
27c766aa JP |
183 | pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d (%d seconds)\n", |
184 | reset ? "reset" : "interrupt", timeout, timeout_sec); | |
500c919e AV |
185 | |
186 | /* | |
187 | * If the watchdog was previously enabled or we're running on | |
59ca1b0d | 188 | * MPC8xxx, we should ping the wdt from the kernel until the |
500c919e AV |
189 | * userspace handles it. |
190 | */ | |
191 | if (enabled) | |
d5cfaf0a | 192 | mod_timer(&wdt_timer, jiffies); |
fabbfb9e | 193 | return 0; |
fabbfb9e KG |
194 | err_unmap: |
195 | iounmap(wd_base); | |
0d7b1014 | 196 | wd_base = NULL; |
fabbfb9e KG |
197 | return ret; |
198 | } | |
199 | ||
4b12b896 | 200 | static int mpc8xxx_wdt_remove(struct platform_device *ofdev) |
fabbfb9e | 201 | { |
d5cfaf0a CL |
202 | pr_crit("Watchdog removed, expect the %s soon!\n", |
203 | reset ? "reset" : "machine check exception"); | |
500c919e | 204 | del_timer_sync(&wdt_timer); |
d5cfaf0a | 205 | watchdog_unregister_device(&mpc8xxx_wdt_dev); |
fabbfb9e KG |
206 | iounmap(wd_base); |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
59ca1b0d | 211 | static const struct of_device_id mpc8xxx_wdt_match[] = { |
ef8ab12e AV |
212 | { |
213 | .compatible = "mpc83xx_wdt", | |
59ca1b0d | 214 | .data = &(struct mpc8xxx_wdt_type) { |
500c919e AV |
215 | .prescaler = 0x10000, |
216 | }, | |
217 | }, | |
218 | { | |
219 | .compatible = "fsl,mpc8610-wdt", | |
59ca1b0d | 220 | .data = &(struct mpc8xxx_wdt_type) { |
500c919e AV |
221 | .prescaler = 0x10000, |
222 | .hw_enabled = true, | |
223 | }, | |
ef8ab12e | 224 | }, |
0d7b1014 AV |
225 | { |
226 | .compatible = "fsl,mpc823-wdt", | |
227 | .data = &(struct mpc8xxx_wdt_type) { | |
228 | .prescaler = 0x800, | |
4af897fa | 229 | .hw_enabled = true, |
0d7b1014 AV |
230 | }, |
231 | }, | |
ef8ab12e AV |
232 | {}, |
233 | }; | |
59ca1b0d | 234 | MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match); |
ef8ab12e | 235 | |
1c48a5c9 | 236 | static struct platform_driver mpc8xxx_wdt_driver = { |
59ca1b0d | 237 | .probe = mpc8xxx_wdt_probe, |
82268714 | 238 | .remove = mpc8xxx_wdt_remove, |
4018294b GL |
239 | .driver = { |
240 | .name = "mpc8xxx_wdt", | |
4018294b | 241 | .of_match_table = mpc8xxx_wdt_match, |
fabbfb9e KG |
242 | }, |
243 | }; | |
244 | ||
0d7b1014 AV |
245 | /* |
246 | * We do wdt initialization in two steps: arch_initcall probes the wdt | |
247 | * very early to start pinging the watchdog (misc devices are not yet | |
248 | * available), and later module_init() just registers the misc device. | |
249 | */ | |
593fc178 | 250 | static int mpc8xxx_wdt_init_late(void) |
0d7b1014 AV |
251 | { |
252 | int ret; | |
253 | ||
254 | if (!wd_base) | |
255 | return -ENODEV; | |
256 | ||
d5cfaf0a CL |
257 | watchdog_set_nowayout(&mpc8xxx_wdt_dev, nowayout); |
258 | ||
259 | ret = watchdog_register_device(&mpc8xxx_wdt_dev); | |
0d7b1014 | 260 | if (ret) { |
d5cfaf0a | 261 | pr_err("cannot register watchdog device (err=%d)\n", ret); |
0d7b1014 AV |
262 | return ret; |
263 | } | |
264 | return 0; | |
265 | } | |
593fc178 | 266 | #ifndef MODULE |
0d7b1014 | 267 | module_init(mpc8xxx_wdt_init_late); |
593fc178 | 268 | #endif |
0d7b1014 | 269 | |
59ca1b0d | 270 | static int __init mpc8xxx_wdt_init(void) |
fabbfb9e | 271 | { |
1c48a5c9 | 272 | return platform_driver_register(&mpc8xxx_wdt_driver); |
fabbfb9e | 273 | } |
0d7b1014 | 274 | arch_initcall(mpc8xxx_wdt_init); |
fabbfb9e | 275 | |
59ca1b0d | 276 | static void __exit mpc8xxx_wdt_exit(void) |
fabbfb9e | 277 | { |
1c48a5c9 | 278 | platform_driver_unregister(&mpc8xxx_wdt_driver); |
fabbfb9e | 279 | } |
59ca1b0d | 280 | module_exit(mpc8xxx_wdt_exit); |
fabbfb9e KG |
281 | |
282 | MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); | |
0d7b1014 AV |
283 | MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx " |
284 | "uProcessors"); | |
fabbfb9e | 285 | MODULE_LICENSE("GPL"); |