[mirror_ubuntu-bionic-kernel.git] / drivers / watchdog / mt7621_wdt.c

/*
 * Ralink MT7621/MT7628 built-in hardware watchdog timer
 *
 * Copyright (C) 2014 John Crispin <john@phrozen.org>
 *
 * This driver was based on: drivers/watchdog/rt2880_wdt.c
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>

#include <asm/mach-ralink/ralink_regs.h>

#define SYSC_RSTSTAT			0x38
#define WDT_RST_CAUSE			BIT(1)

#define RALINK_WDT_TIMEOUT		30

#define TIMER_REG_TMRSTAT		0x00
#define TIMER_REG_TMR1LOAD		0x24
#define TIMER_REG_TMR1CTL		0x20

#define TMR1CTL_ENABLE			BIT(7)
#define TMR1CTL_RESTART			BIT(9)
#define TMR1CTL_PRESCALE_SHIFT		16

static void __iomem *mt7621_wdt_base;
static struct reset_control *mt7621_wdt_reset;

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
		 "Watchdog cannot be stopped once started (default="
		 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static inline void rt_wdt_w32(unsigned reg, u32 val)
{
	iowrite32(val, mt7621_wdt_base + reg);
}

static inline u32 rt_wdt_r32(unsigned reg)
{
	return ioread32(mt7621_wdt_base + reg);
}

static int mt7621_wdt_ping(struct watchdog_device *w)
{
	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);

	return 0;
}

static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
{
	w->timeout = t;
	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
	mt7621_wdt_ping(w);

	return 0;
}

static int mt7621_wdt_start(struct watchdog_device *w)
{
	u32 t;

	/* set the prescaler to 1ms == 1000us */
	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);

	mt7621_wdt_set_timeout(w, w->timeout);

	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
	t |= TMR1CTL_ENABLE;
	rt_wdt_w32(TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_stop(struct watchdog_device *w)
{
	u32 t;

	mt7621_wdt_ping(w);

	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
	t &= ~TMR1CTL_ENABLE;
	rt_wdt_w32(TIMER_REG_TMR1CTL, t);

	return 0;
}

static int mt7621_wdt_bootcause(void)
{
	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
		return WDIOF_CARDRESET;

	return 0;
}

static const struct watchdog_info mt7621_wdt_info = {
	.identity = "Mediatek Watchdog",
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
};

static const struct watchdog_ops mt7621_wdt_ops = {
	.owner = THIS_MODULE,
	.start = mt7621_wdt_start,
	.stop = mt7621_wdt_stop,
	.ping = mt7621_wdt_ping,
	.set_timeout = mt7621_wdt_set_timeout,
};

static struct watchdog_device mt7621_wdt_dev = {
	.info = &mt7621_wdt_info,
	.ops = &mt7621_wdt_ops,
	.min_timeout = 1,
	.max_timeout = 0xfffful / 1000,
};

static int mt7621_wdt_probe(struct platform_device *pdev)
{
	struct resource *res;
	int ret;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mt7621_wdt_base))
		return PTR_ERR(mt7621_wdt_base);

	mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (!IS_ERR(mt7621_wdt_reset))
		reset_control_deassert(mt7621_wdt_reset);

	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();

	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
			      &pdev->dev);
	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);

	ret = watchdog_register_device(&mt7621_wdt_dev);

	return 0;
}

static int mt7621_wdt_remove(struct platform_device *pdev)
{
	watchdog_unregister_device(&mt7621_wdt_dev);

	return 0;
}

static void mt7621_wdt_shutdown(struct platform_device *pdev)
{
	mt7621_wdt_stop(&mt7621_wdt_dev);
}

static const struct of_device_id mt7621_wdt_match[] = {
	{ .compatible = "mediatek,mt7621-wdt" },
	{},
};
MODULE_DEVICE_TABLE(of, mt7621_wdt_match);

static struct platform_driver mt7621_wdt_driver = {
	.probe		= mt7621_wdt_probe,
	.remove		= mt7621_wdt_remove,
	.shutdown	= mt7621_wdt_shutdown,
	.driver		= {
		.name		= KBUILD_MODNAME,
		.of_match_table	= mt7621_wdt_match,
	},
};

module_platform_driver(mt7621_wdt_driver);

MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
MODULE_AUTHOR("John Crispin <john@phrozen.org");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ab3f09fe JC	1	/*
	2	* Ralink MT7621/MT7628 built-in hardware watchdog timer
	3	*
f3519a66	4	* Copyright (C) 2014 John Crispin <john@phrozen.org>
ab3f09fe JC	5	*
	6	* This driver was based on: drivers/watchdog/rt2880_wdt.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License version 2 as published
	10	* by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/reset.h>
	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/watchdog.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/platform_device.h>
5228390f	20	#include <linux/mod_devicetable.h>
ab3f09fe JC	21
	22	#include <asm/mach-ralink/ralink_regs.h>
	23
	24	#define SYSC_RSTSTAT 0x38
	25	#define WDT_RST_CAUSE BIT(1)
	26
	27	#define RALINK_WDT_TIMEOUT 30
	28
	29	#define TIMER_REG_TMRSTAT 0x00
	30	#define TIMER_REG_TMR1LOAD 0x24
	31	#define TIMER_REG_TMR1CTL 0x20
	32
	33	#define TMR1CTL_ENABLE BIT(7)
	34	#define TMR1CTL_RESTART BIT(9)
	35	#define TMR1CTL_PRESCALE_SHIFT 16
	36
	37	static void __iomem *mt7621_wdt_base;
	38	static struct reset_control *mt7621_wdt_reset;
	39
	40	static bool nowayout = WATCHDOG_NOWAYOUT;
	41	module_param(nowayout, bool, 0);
	42	MODULE_PARM_DESC(nowayout,
	43	"Watchdog cannot be stopped once started (default="
	44	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	45
	46	static inline void rt_wdt_w32(unsigned reg, u32 val)
	47	{
	48	iowrite32(val, mt7621_wdt_base + reg);
	49	}
	50
	51	static inline u32 rt_wdt_r32(unsigned reg)
	52	{
	53	return ioread32(mt7621_wdt_base + reg);
	54	}
	55
	56	static int mt7621_wdt_ping(struct watchdog_device *w)
	57	{
	58	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
	59
	60	return 0;
	61	}
	62
	63	static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
	64	{
	65	w->timeout = t;
	66	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
	67	mt7621_wdt_ping(w);
	68
	69	return 0;
	70	}
	71
	72	static int mt7621_wdt_start(struct watchdog_device *w)
	73	{
	74	u32 t;
	75
	76	/* set the prescaler to 1ms == 1000us */
	77	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
	78
	79	mt7621_wdt_set_timeout(w, w->timeout);
	80
	81	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
	82	t \|= TMR1CTL_ENABLE;
	83	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
	84
85	return 0;
86	}
87
88	static int mt7621_wdt_stop(struct watchdog_device *w)
89	{
90	u32 t;
91
92	mt7621_wdt_ping(w);
93
94	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
95	t &= ~TMR1CTL_ENABLE;
96	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
97
98	return 0;
99	}
100
101	static int mt7621_wdt_bootcause(void)
102	{
103	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
104	return WDIOF_CARDRESET;
105
106	return 0;
107	}
108
323edb2e	109	static const struct watchdog_info mt7621_wdt_info = {
ab3f09fe JC	110	.identity = "Mediatek Watchdog",
	111	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING \| WDIOF_MAGICCLOSE,
	112	};
	113
b893e344	114	static const struct watchdog_ops mt7621_wdt_ops = {
ab3f09fe JC	115	.owner = THIS_MODULE,
	116	.start = mt7621_wdt_start,
	117	.stop = mt7621_wdt_stop,
	118	.ping = mt7621_wdt_ping,
	119	.set_timeout = mt7621_wdt_set_timeout,
	120	};
	121
	122	static struct watchdog_device mt7621_wdt_dev = {
	123	.info = &mt7621_wdt_info,
	124	.ops = &mt7621_wdt_ops,
	125	.min_timeout = 1,
	126	.max_timeout = 0xfffful / 1000,
	127	};
	128
	129	static int mt7621_wdt_probe(struct platform_device *pdev)
	130	{
	131	struct resource *res;
	132	int ret;
	133
	134	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	135	mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res);
	136	if (IS_ERR(mt7621_wdt_base))
	137	return PTR_ERR(mt7621_wdt_base);
	138
0bade021	139	mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
ab3f09fe JC	140	if (!IS_ERR(mt7621_wdt_reset))
	141	reset_control_deassert(mt7621_wdt_reset);
	142
ab3f09fe JC	143	mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
	144
	145	watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
	146	&pdev->dev);
	147	watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
	148
	149	ret = watchdog_register_device(&mt7621_wdt_dev);
	150
	151	return 0;
	152	}
	153
	154	static int mt7621_wdt_remove(struct platform_device *pdev)
	155	{
	156	watchdog_unregister_device(&mt7621_wdt_dev);
	157
	158	return 0;
	159	}
	160
	161	static void mt7621_wdt_shutdown(struct platform_device *pdev)
	162	{
	163	mt7621_wdt_stop(&mt7621_wdt_dev);
	164	}
	165
	166	static const struct of_device_id mt7621_wdt_match[] = {
	167	{ .compatible = "mediatek,mt7621-wdt" },
	168	{},
	169	};
	170	MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
	171
	172	static struct platform_driver mt7621_wdt_driver = {
	173	.probe = mt7621_wdt_probe,
	174	.remove = mt7621_wdt_remove,
	175	.shutdown = mt7621_wdt_shutdown,
	176	.driver = {
	177	.name = KBUILD_MODNAME,
	178	.of_match_table = mt7621_wdt_match,
	179	},
	180	};
	181
	182	module_platform_driver(mt7621_wdt_driver);
	183
	184	MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
f3519a66	185	MODULE_AUTHOR("John Crispin <john@phrozen.org");
ab3f09fe	186	MODULE_LICENSE("GPL v2");