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ab3f09fe JC |
1 | /* |
2 | * Ralink MT7621/MT7628 built-in hardware watchdog timer | |
3 | * | |
f3519a66 | 4 | * Copyright (C) 2014 John Crispin <john@phrozen.org> |
ab3f09fe JC |
5 | * |
6 | * This driver was based on: drivers/watchdog/rt2880_wdt.c | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published | |
10 | * by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/reset.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/watchdog.h> | |
18 | #include <linux/moduleparam.h> | |
19 | #include <linux/platform_device.h> | |
20 | ||
21 | #include <asm/mach-ralink/ralink_regs.h> | |
22 | ||
23 | #define SYSC_RSTSTAT 0x38 | |
24 | #define WDT_RST_CAUSE BIT(1) | |
25 | ||
26 | #define RALINK_WDT_TIMEOUT 30 | |
27 | ||
28 | #define TIMER_REG_TMRSTAT 0x00 | |
29 | #define TIMER_REG_TMR1LOAD 0x24 | |
30 | #define TIMER_REG_TMR1CTL 0x20 | |
31 | ||
32 | #define TMR1CTL_ENABLE BIT(7) | |
33 | #define TMR1CTL_RESTART BIT(9) | |
34 | #define TMR1CTL_PRESCALE_SHIFT 16 | |
35 | ||
36 | static void __iomem *mt7621_wdt_base; | |
37 | static struct reset_control *mt7621_wdt_reset; | |
38 | ||
39 | static bool nowayout = WATCHDOG_NOWAYOUT; | |
40 | module_param(nowayout, bool, 0); | |
41 | MODULE_PARM_DESC(nowayout, | |
42 | "Watchdog cannot be stopped once started (default=" | |
43 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
44 | ||
45 | static inline void rt_wdt_w32(unsigned reg, u32 val) | |
46 | { | |
47 | iowrite32(val, mt7621_wdt_base + reg); | |
48 | } | |
49 | ||
50 | static inline u32 rt_wdt_r32(unsigned reg) | |
51 | { | |
52 | return ioread32(mt7621_wdt_base + reg); | |
53 | } | |
54 | ||
55 | static int mt7621_wdt_ping(struct watchdog_device *w) | |
56 | { | |
57 | rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART); | |
58 | ||
59 | return 0; | |
60 | } | |
61 | ||
62 | static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t) | |
63 | { | |
64 | w->timeout = t; | |
65 | rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000); | |
66 | mt7621_wdt_ping(w); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | static int mt7621_wdt_start(struct watchdog_device *w) | |
72 | { | |
73 | u32 t; | |
74 | ||
75 | /* set the prescaler to 1ms == 1000us */ | |
76 | rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); | |
77 | ||
78 | mt7621_wdt_set_timeout(w, w->timeout); | |
79 | ||
80 | t = rt_wdt_r32(TIMER_REG_TMR1CTL); | |
81 | t |= TMR1CTL_ENABLE; | |
82 | rt_wdt_w32(TIMER_REG_TMR1CTL, t); | |
83 | ||
84 | return 0; | |
85 | } | |
86 | ||
87 | static int mt7621_wdt_stop(struct watchdog_device *w) | |
88 | { | |
89 | u32 t; | |
90 | ||
91 | mt7621_wdt_ping(w); | |
92 | ||
93 | t = rt_wdt_r32(TIMER_REG_TMR1CTL); | |
94 | t &= ~TMR1CTL_ENABLE; | |
95 | rt_wdt_w32(TIMER_REG_TMR1CTL, t); | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int mt7621_wdt_bootcause(void) | |
101 | { | |
102 | if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) | |
103 | return WDIOF_CARDRESET; | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
108 | static struct watchdog_info mt7621_wdt_info = { | |
109 | .identity = "Mediatek Watchdog", | |
110 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
111 | }; | |
112 | ||
b893e344 | 113 | static const struct watchdog_ops mt7621_wdt_ops = { |
ab3f09fe JC |
114 | .owner = THIS_MODULE, |
115 | .start = mt7621_wdt_start, | |
116 | .stop = mt7621_wdt_stop, | |
117 | .ping = mt7621_wdt_ping, | |
118 | .set_timeout = mt7621_wdt_set_timeout, | |
119 | }; | |
120 | ||
121 | static struct watchdog_device mt7621_wdt_dev = { | |
122 | .info = &mt7621_wdt_info, | |
123 | .ops = &mt7621_wdt_ops, | |
124 | .min_timeout = 1, | |
125 | .max_timeout = 0xfffful / 1000, | |
126 | }; | |
127 | ||
128 | static int mt7621_wdt_probe(struct platform_device *pdev) | |
129 | { | |
130 | struct resource *res; | |
131 | int ret; | |
132 | ||
133 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
134 | mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res); | |
135 | if (IS_ERR(mt7621_wdt_base)) | |
136 | return PTR_ERR(mt7621_wdt_base); | |
137 | ||
138 | mt7621_wdt_reset = devm_reset_control_get(&pdev->dev, NULL); | |
139 | if (!IS_ERR(mt7621_wdt_reset)) | |
140 | reset_control_deassert(mt7621_wdt_reset); | |
141 | ||
ab3f09fe JC |
142 | mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause(); |
143 | ||
144 | watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout, | |
145 | &pdev->dev); | |
146 | watchdog_set_nowayout(&mt7621_wdt_dev, nowayout); | |
147 | ||
148 | ret = watchdog_register_device(&mt7621_wdt_dev); | |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | static int mt7621_wdt_remove(struct platform_device *pdev) | |
154 | { | |
155 | watchdog_unregister_device(&mt7621_wdt_dev); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | static void mt7621_wdt_shutdown(struct platform_device *pdev) | |
161 | { | |
162 | mt7621_wdt_stop(&mt7621_wdt_dev); | |
163 | } | |
164 | ||
165 | static const struct of_device_id mt7621_wdt_match[] = { | |
166 | { .compatible = "mediatek,mt7621-wdt" }, | |
167 | {}, | |
168 | }; | |
169 | MODULE_DEVICE_TABLE(of, mt7621_wdt_match); | |
170 | ||
171 | static struct platform_driver mt7621_wdt_driver = { | |
172 | .probe = mt7621_wdt_probe, | |
173 | .remove = mt7621_wdt_remove, | |
174 | .shutdown = mt7621_wdt_shutdown, | |
175 | .driver = { | |
176 | .name = KBUILD_MODNAME, | |
177 | .of_match_table = mt7621_wdt_match, | |
178 | }, | |
179 | }; | |
180 | ||
181 | module_platform_driver(mt7621_wdt_driver); | |
182 | ||
183 | MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver"); | |
f3519a66 | 184 | MODULE_AUTHOR("John Crispin <john@phrozen.org"); |
ab3f09fe | 185 | MODULE_LICENSE("GPL v2"); |