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Commit | Line | Data |
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e9659e69 | 1 | /* |
9419c07c MS |
2 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
3 | * | |
d14fd964 | 4 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c MS |
5 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
e9659e69 | 12 | |
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
e9659e69 AC |
15 | #include <linux/module.h> |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
e9659e69 AC |
18 | #include <linux/ioport.h> |
19 | #include <linux/watchdog.h> | |
20 | #include <linux/io.h> | |
e9659e69 AC |
21 | #include <linux/of.h> |
22 | #include <linux/of_device.h> | |
23 | #include <linux/of_address.h> | |
24 | ||
25 | /* Register offsets for the Wdt device */ | |
26 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
27 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
28 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
29 | ||
30 | /* Control/Status Register Masks */ | |
31 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
32 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
33 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
34 | ||
35 | /* Control/Status Register 0/1 bits */ | |
36 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
37 | ||
38 | /* SelfTest constants */ | |
39 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
40 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
41 | ||
42 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
43 | #define PFX WATCHDOG_NAME ": " | |
44 | ||
45 | struct xwdt_device { | |
46 | struct resource res; | |
47 | void __iomem *base; | |
e9659e69 | 48 | u32 wdt_interval; |
e9659e69 AC |
49 | }; |
50 | ||
51 | static struct xwdt_device xdev; | |
52 | ||
53 | static u32 timeout; | |
e9659e69 | 54 | static u8 no_timeout; |
e9659e69 AC |
55 | |
56 | static DEFINE_SPINLOCK(spinlock); | |
57 | ||
d14fd964 | 58 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 59 | { |
5cf4e69d MS |
60 | u32 control_status_reg; |
61 | ||
e9659e69 AC |
62 | spin_lock(&spinlock); |
63 | ||
64 | /* Clean previous status and enable the watchdog timer */ | |
65 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
66 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); | |
67 | ||
68 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
69 | xdev.base + XWT_TWCSR0_OFFSET); | |
70 | ||
71 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET); | |
72 | ||
73 | spin_unlock(&spinlock); | |
d14fd964 MS |
74 | |
75 | return 0; | |
e9659e69 AC |
76 | } |
77 | ||
d14fd964 | 78 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 79 | { |
5cf4e69d MS |
80 | u32 control_status_reg; |
81 | ||
e9659e69 AC |
82 | spin_lock(&spinlock); |
83 | ||
84 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
85 | ||
86 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
87 | xdev.base + XWT_TWCSR0_OFFSET); | |
88 | ||
89 | iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET); | |
90 | ||
91 | spin_unlock(&spinlock); | |
27c766aa | 92 | pr_info("Stopped!\n"); |
d14fd964 MS |
93 | |
94 | return 0; | |
e9659e69 AC |
95 | } |
96 | ||
d14fd964 | 97 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 98 | { |
5cf4e69d MS |
99 | u32 control_status_reg; |
100 | ||
e9659e69 AC |
101 | spin_lock(&spinlock); |
102 | ||
103 | control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET); | |
104 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); | |
105 | iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET); | |
106 | ||
107 | spin_unlock(&spinlock); | |
e9659e69 | 108 | |
d14fd964 MS |
109 | return 0; |
110 | } | |
e9659e69 | 111 | |
d14fd964 MS |
112 | static const struct watchdog_info xilinx_wdt_ident = { |
113 | .options = WDIOF_MAGICCLOSE | | |
114 | WDIOF_KEEPALIVEPING, | |
115 | .firmware_version = 1, | |
116 | .identity = WATCHDOG_NAME, | |
117 | }; | |
e9659e69 | 118 | |
d14fd964 MS |
119 | static const struct watchdog_ops xilinx_wdt_ops = { |
120 | .owner = THIS_MODULE, | |
121 | .start = xilinx_wdt_start, | |
122 | .stop = xilinx_wdt_stop, | |
123 | .ping = xilinx_wdt_keepalive, | |
124 | }; | |
e9659e69 | 125 | |
d14fd964 MS |
126 | static struct watchdog_device xilinx_wdt_wdd = { |
127 | .info = &xilinx_wdt_ident, | |
128 | .ops = &xilinx_wdt_ops, | |
129 | }; | |
e9659e69 AC |
130 | |
131 | static u32 xwdt_selftest(void) | |
132 | { | |
133 | int i; | |
134 | u32 timer_value1; | |
135 | u32 timer_value2; | |
136 | ||
137 | spin_lock(&spinlock); | |
138 | ||
139 | timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
140 | timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
141 | ||
142 | for (i = 0; | |
143 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
144 | (timer_value2 == timer_value1)); i++) { | |
145 | timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET); | |
146 | } | |
147 | ||
148 | spin_unlock(&spinlock); | |
149 | ||
150 | if (timer_value2 != timer_value1) | |
151 | return ~XWT_TIMER_FAILED; | |
152 | else | |
153 | return XWT_TIMER_FAILED; | |
154 | } | |
155 | ||
2d991a16 | 156 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 AC |
157 | { |
158 | int rc; | |
159 | u32 *tmptr; | |
160 | u32 *pfreq; | |
161 | ||
162 | no_timeout = 0; | |
163 | ||
90fe6c60 | 164 | pfreq = (u32 *)of_get_property(pdev->dev.of_node, |
e9659e69 AC |
165 | "clock-frequency", NULL); |
166 | ||
167 | if (pfreq == NULL) { | |
27c766aa | 168 | pr_warn("The watchdog clock frequency cannot be obtained!\n"); |
e9659e69 AC |
169 | no_timeout = 1; |
170 | } | |
171 | ||
172 | rc = of_address_to_resource(pdev->dev.of_node, 0, &xdev.res); | |
173 | if (rc) { | |
27c766aa | 174 | pr_warn("invalid address!\n"); |
e9659e69 AC |
175 | return rc; |
176 | } | |
177 | ||
178 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, | |
179 | "xlnx,wdt-interval", NULL); | |
180 | if (tmptr == NULL) { | |
27c766aa | 181 | pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n"); |
e9659e69 AC |
182 | no_timeout = 1; |
183 | } else { | |
184 | xdev.wdt_interval = *tmptr; | |
185 | } | |
186 | ||
187 | tmptr = (u32 *)of_get_property(pdev->dev.of_node, | |
188 | "xlnx,wdt-enable-once", NULL); | |
189 | if (tmptr == NULL) { | |
27c766aa | 190 | pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n"); |
d14fd964 | 191 | watchdog_set_nowayout(&xilinx_wdt_wdd, true); |
e9659e69 AC |
192 | } |
193 | ||
194 | /* | |
195 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
196 | * ignored (interrupt), reset is only generated at second wdt overflow | |
197 | */ | |
198 | if (!no_timeout) | |
199 | timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq); | |
200 | ||
201 | if (!request_mem_region(xdev.res.start, | |
202 | xdev.res.end - xdev.res.start + 1, WATCHDOG_NAME)) { | |
203 | rc = -ENXIO; | |
27c766aa | 204 | pr_err("memory request failure!\n"); |
e9659e69 AC |
205 | goto err_out; |
206 | } | |
207 | ||
208 | xdev.base = ioremap(xdev.res.start, xdev.res.end - xdev.res.start + 1); | |
209 | if (xdev.base == NULL) { | |
210 | rc = -ENOMEM; | |
27c766aa | 211 | pr_err("ioremap failure!\n"); |
e9659e69 AC |
212 | goto release_mem; |
213 | } | |
214 | ||
215 | rc = xwdt_selftest(); | |
216 | if (rc == XWT_TIMER_FAILED) { | |
27c766aa | 217 | pr_err("SelfTest routine error!\n"); |
e9659e69 AC |
218 | goto unmap_io; |
219 | } | |
220 | ||
d14fd964 | 221 | rc = watchdog_register_device(&xilinx_wdt_wdd); |
e9659e69 | 222 | if (rc) { |
d14fd964 | 223 | pr_err("cannot register watchdog (err=%d)\n", rc); |
e9659e69 AC |
224 | goto unmap_io; |
225 | } | |
226 | ||
d14fd964 MS |
227 | dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", |
228 | xdev.base, timeout); | |
e9659e69 AC |
229 | |
230 | return 0; | |
231 | ||
232 | unmap_io: | |
233 | iounmap(xdev.base); | |
234 | release_mem: | |
235 | release_mem_region(xdev.res.start, resource_size(&xdev.res)); | |
236 | err_out: | |
237 | return rc; | |
238 | } | |
239 | ||
4b12b896 | 240 | static int xwdt_remove(struct platform_device *dev) |
e9659e69 | 241 | { |
d14fd964 | 242 | watchdog_unregister_device(&xilinx_wdt_wdd); |
e9659e69 AC |
243 | iounmap(xdev.base); |
244 | release_mem_region(xdev.res.start, resource_size(&xdev.res)); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | /* Match table for of_platform binding */ | |
1d131368 | 250 | static struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 251 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
252 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
253 | {}, | |
254 | }; | |
255 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
256 | ||
257 | static struct platform_driver xwdt_driver = { | |
258 | .probe = xwdt_probe, | |
82268714 | 259 | .remove = xwdt_remove, |
e9659e69 AC |
260 | .driver = { |
261 | .owner = THIS_MODULE, | |
262 | .name = WATCHDOG_NAME, | |
263 | .of_match_table = xwdt_of_match, | |
264 | }, | |
265 | }; | |
266 | ||
b8ec6118 | 267 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
268 | |
269 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
270 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
9419c07c | 271 | MODULE_LICENSE("GPL v2"); |