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2e62c498 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
e9659e69 | 2 | /* |
9419c07c MS |
3 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
4 | * | |
d14fd964 | 5 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c | 6 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
9419c07c | 7 | */ |
e9659e69 | 8 | |
9d6b4efc | 9 | #include <linux/clk.h> |
f06cdfd1 | 10 | #include <linux/err.h> |
e9659e69 AC |
11 | #include <linux/module.h> |
12 | #include <linux/types.h> | |
13 | #include <linux/kernel.h> | |
e9659e69 AC |
14 | #include <linux/ioport.h> |
15 | #include <linux/watchdog.h> | |
16 | #include <linux/io.h> | |
e9659e69 AC |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
19 | #include <linux/of_address.h> | |
20 | ||
21 | /* Register offsets for the Wdt device */ | |
22 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
23 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
24 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
25 | ||
26 | /* Control/Status Register Masks */ | |
27 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
28 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
29 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
30 | ||
31 | /* Control/Status Register 0/1 bits */ | |
32 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
33 | ||
34 | /* SelfTest constants */ | |
35 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
36 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
37 | ||
38 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
e9659e69 AC |
39 | |
40 | struct xwdt_device { | |
e9659e69 | 41 | void __iomem *base; |
e9659e69 | 42 | u32 wdt_interval; |
90663171 MS |
43 | spinlock_t spinlock; |
44 | struct watchdog_device xilinx_wdt_wdd; | |
9d6b4efc | 45 | struct clk *clk; |
e9659e69 AC |
46 | }; |
47 | ||
d14fd964 | 48 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 49 | { |
b6bc4164 | 50 | int ret; |
5cf4e69d | 51 | u32 control_status_reg; |
90663171 | 52 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 53 | |
b6bc4164 MJ |
54 | ret = clk_enable(xdev->clk); |
55 | if (ret) { | |
56 | dev_err(wdd->parent, "Failed to enable clock\n"); | |
57 | return ret; | |
58 | } | |
59 | ||
90663171 | 60 | spin_lock(&xdev->spinlock); |
e9659e69 AC |
61 | |
62 | /* Clean previous status and enable the watchdog timer */ | |
90663171 | 63 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
64 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
65 | ||
66 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
90663171 | 67 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 68 | |
90663171 | 69 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 70 | |
90663171 | 71 | spin_unlock(&xdev->spinlock); |
d14fd964 MS |
72 | |
73 | return 0; | |
e9659e69 AC |
74 | } |
75 | ||
d14fd964 | 76 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 77 | { |
5cf4e69d | 78 | u32 control_status_reg; |
90663171 | 79 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 80 | |
90663171 | 81 | spin_lock(&xdev->spinlock); |
e9659e69 | 82 | |
90663171 | 83 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
84 | |
85 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
90663171 | 86 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 87 | |
90663171 | 88 | iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 89 | |
90663171 | 90 | spin_unlock(&xdev->spinlock); |
b6bc4164 MJ |
91 | |
92 | clk_disable(xdev->clk); | |
93 | ||
27c766aa | 94 | pr_info("Stopped!\n"); |
d14fd964 MS |
95 | |
96 | return 0; | |
e9659e69 AC |
97 | } |
98 | ||
d14fd964 | 99 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 100 | { |
5cf4e69d | 101 | u32 control_status_reg; |
90663171 | 102 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 103 | |
90663171 | 104 | spin_lock(&xdev->spinlock); |
e9659e69 | 105 | |
90663171 | 106 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 107 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
90663171 | 108 | iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 109 | |
90663171 | 110 | spin_unlock(&xdev->spinlock); |
e9659e69 | 111 | |
d14fd964 MS |
112 | return 0; |
113 | } | |
e9659e69 | 114 | |
d14fd964 MS |
115 | static const struct watchdog_info xilinx_wdt_ident = { |
116 | .options = WDIOF_MAGICCLOSE | | |
117 | WDIOF_KEEPALIVEPING, | |
118 | .firmware_version = 1, | |
119 | .identity = WATCHDOG_NAME, | |
120 | }; | |
e9659e69 | 121 | |
d14fd964 MS |
122 | static const struct watchdog_ops xilinx_wdt_ops = { |
123 | .owner = THIS_MODULE, | |
124 | .start = xilinx_wdt_start, | |
125 | .stop = xilinx_wdt_stop, | |
126 | .ping = xilinx_wdt_keepalive, | |
127 | }; | |
e9659e69 | 128 | |
90663171 | 129 | static u32 xwdt_selftest(struct xwdt_device *xdev) |
e9659e69 AC |
130 | { |
131 | int i; | |
132 | u32 timer_value1; | |
133 | u32 timer_value2; | |
134 | ||
90663171 | 135 | spin_lock(&xdev->spinlock); |
e9659e69 | 136 | |
90663171 MS |
137 | timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); |
138 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); | |
e9659e69 AC |
139 | |
140 | for (i = 0; | |
141 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
142 | (timer_value2 == timer_value1)); i++) { | |
90663171 | 143 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
e9659e69 AC |
144 | } |
145 | ||
90663171 | 146 | spin_unlock(&xdev->spinlock); |
e9659e69 AC |
147 | |
148 | if (timer_value2 != timer_value1) | |
149 | return ~XWT_TIMER_FAILED; | |
150 | else | |
151 | return XWT_TIMER_FAILED; | |
152 | } | |
153 | ||
801cdffe GR |
154 | static void xwdt_clk_disable_unprepare(void *data) |
155 | { | |
156 | clk_disable_unprepare(data); | |
157 | } | |
158 | ||
2d991a16 | 159 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 | 160 | { |
801cdffe | 161 | struct device *dev = &pdev->dev; |
e9659e69 | 162 | int rc; |
8d6a140b | 163 | u32 pfreq = 0, enable_once = 0; |
90663171 | 164 | struct xwdt_device *xdev; |
90663171 MS |
165 | struct watchdog_device *xilinx_wdt_wdd; |
166 | ||
801cdffe | 167 | xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL); |
90663171 MS |
168 | if (!xdev) |
169 | return -ENOMEM; | |
170 | ||
171 | xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; | |
172 | xilinx_wdt_wdd->info = &xilinx_wdt_ident; | |
173 | xilinx_wdt_wdd->ops = &xilinx_wdt_ops; | |
801cdffe | 174 | xilinx_wdt_wdd->parent = dev; |
e9659e69 | 175 | |
0f0a6a28 | 176 | xdev->base = devm_platform_ioremap_resource(pdev, 0); |
90663171 MS |
177 | if (IS_ERR(xdev->base)) |
178 | return PTR_ERR(xdev->base); | |
f06cdfd1 | 179 | |
801cdffe | 180 | rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval", |
2e79a368 | 181 | &xdev->wdt_interval); |
8d6a140b | 182 | if (rc) |
801cdffe | 183 | dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found\n"); |
e9659e69 | 184 | |
801cdffe | 185 | rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once", |
2e79a368 MS |
186 | &enable_once); |
187 | if (rc) | |
801cdffe | 188 | dev_warn(dev, |
4c7fbbc4 | 189 | "Parameter \"xlnx,wdt-enable-once\" not found\n"); |
2e79a368 MS |
190 | |
191 | watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); | |
e9659e69 | 192 | |
801cdffe | 193 | xdev->clk = devm_clk_get(dev, NULL); |
b6bc4164 MJ |
194 | if (IS_ERR(xdev->clk)) { |
195 | if (PTR_ERR(xdev->clk) != -ENOENT) | |
196 | return PTR_ERR(xdev->clk); | |
197 | ||
198 | /* | |
199 | * Clock framework support is optional, continue on | |
200 | * anyways if we don't find a matching clock. | |
201 | */ | |
202 | xdev->clk = NULL; | |
203 | ||
801cdffe | 204 | rc = of_property_read_u32(dev->of_node, "clock-frequency", |
b6bc4164 MJ |
205 | &pfreq); |
206 | if (rc) | |
801cdffe | 207 | dev_warn(dev, |
b6bc4164 MJ |
208 | "The watchdog clock freq cannot be obtained\n"); |
209 | } else { | |
210 | pfreq = clk_get_rate(xdev->clk); | |
211 | } | |
212 | ||
75b3c5a8 MS |
213 | /* |
214 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
215 | * ignored (interrupt), reset is only generated at second wdt overflow | |
216 | */ | |
8d6a140b | 217 | if (pfreq && xdev->wdt_interval) |
90663171 | 218 | xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
2e79a368 | 219 | pfreq); |
90663171 MS |
220 | |
221 | spin_lock_init(&xdev->spinlock); | |
222 | watchdog_set_drvdata(xilinx_wdt_wdd, xdev); | |
e9659e69 | 223 | |
9d6b4efc SD |
224 | rc = clk_prepare_enable(xdev->clk); |
225 | if (rc) { | |
801cdffe | 226 | dev_err(dev, "unable to enable clock\n"); |
9d6b4efc SD |
227 | return rc; |
228 | } | |
801cdffe GR |
229 | rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare, |
230 | xdev->clk); | |
231 | if (rc) | |
232 | return rc; | |
9d6b4efc | 233 | |
90663171 | 234 | rc = xwdt_selftest(xdev); |
e9659e69 | 235 | if (rc == XWT_TIMER_FAILED) { |
801cdffe GR |
236 | dev_err(dev, "SelfTest routine error\n"); |
237 | return rc; | |
e9659e69 AC |
238 | } |
239 | ||
801cdffe | 240 | rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd); |
e9659e69 | 241 | if (rc) { |
801cdffe GR |
242 | dev_err(dev, "Cannot register watchdog (err=%d)\n", rc); |
243 | return rc; | |
e9659e69 AC |
244 | } |
245 | ||
b6bc4164 MJ |
246 | clk_disable(xdev->clk); |
247 | ||
801cdffe | 248 | dev_info(dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", |
90663171 MS |
249 | xdev->base, xilinx_wdt_wdd->timeout); |
250 | ||
251 | platform_set_drvdata(pdev, xdev); | |
e9659e69 | 252 | |
e9659e69 AC |
253 | return 0; |
254 | } | |
255 | ||
6f671c6b MS |
256 | /** |
257 | * xwdt_suspend - Suspend the device. | |
258 | * | |
259 | * @dev: handle to the device structure. | |
260 | * Return: 0 always. | |
261 | */ | |
262 | static int __maybe_unused xwdt_suspend(struct device *dev) | |
263 | { | |
20745634 | 264 | struct xwdt_device *xdev = dev_get_drvdata(dev); |
6f671c6b MS |
265 | |
266 | if (watchdog_active(&xdev->xilinx_wdt_wdd)) | |
267 | xilinx_wdt_stop(&xdev->xilinx_wdt_wdd); | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | /** | |
273 | * xwdt_resume - Resume the device. | |
274 | * | |
275 | * @dev: handle to the device structure. | |
276 | * Return: 0 on success, errno otherwise. | |
277 | */ | |
278 | static int __maybe_unused xwdt_resume(struct device *dev) | |
279 | { | |
20745634 | 280 | struct xwdt_device *xdev = dev_get_drvdata(dev); |
6f671c6b MS |
281 | int ret = 0; |
282 | ||
283 | if (watchdog_active(&xdev->xilinx_wdt_wdd)) | |
284 | ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd); | |
285 | ||
286 | return ret; | |
287 | } | |
288 | ||
289 | static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume); | |
290 | ||
e9659e69 | 291 | /* Match table for of_platform binding */ |
9ebf1855 | 292 | static const struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 293 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
294 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
295 | {}, | |
296 | }; | |
297 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
298 | ||
299 | static struct platform_driver xwdt_driver = { | |
300 | .probe = xwdt_probe, | |
e9659e69 | 301 | .driver = { |
e9659e69 AC |
302 | .name = WATCHDOG_NAME, |
303 | .of_match_table = xwdt_of_match, | |
6f671c6b | 304 | .pm = &xwdt_pm_ops, |
e9659e69 AC |
305 | }, |
306 | }; | |
307 | ||
b8ec6118 | 308 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
309 | |
310 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
311 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
2e62c498 | 312 | MODULE_LICENSE("GPL"); |