[mirror_ubuntu-artful-kernel.git] / drivers / watchdog / of_xilinx_wdt.c

/*
 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
 *
 * (C) Copyright 2013 - 2014 Xilinx, Inc.
 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/err.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/watchdog.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>

/* Register offsets for the Wdt device */
#define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
#define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
#define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */

/* Control/Status Register Masks  */
#define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
#define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */

/* Control/Status Register 0/1 bits  */
#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */

/* SelfTest constants */
#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
#define XWT_TIMER_FAILED            0xFFFFFFFF

#define WATCHDOG_NAME     "Xilinx Watchdog"
#define PFX WATCHDOG_NAME ": "

struct xwdt_device {
	void __iomem *base;
	u32 wdt_interval;
};

static struct xwdt_device xdev;

static  u32 timeout;

static  DEFINE_SPINLOCK(spinlock);

static int xilinx_wdt_start(struct watchdog_device *wdd)
{
	u32 control_status_reg;

	spin_lock(&spinlock);

	/* Clean previous status and enable the watchdog timer */
	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);

	iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
				xdev.base + XWT_TWCSR0_OFFSET);

	iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);

	spin_unlock(&spinlock);

	return 0;
}

static int xilinx_wdt_stop(struct watchdog_device *wdd)
{
	u32 control_status_reg;

	spin_lock(&spinlock);

	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);

	iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
				xdev.base + XWT_TWCSR0_OFFSET);

	iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);

	spin_unlock(&spinlock);
	pr_info("Stopped!\n");

	return 0;
}

static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
{
	u32 control_status_reg;

	spin_lock(&spinlock);

	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
	iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);

	spin_unlock(&spinlock);

	return 0;
}

static const struct watchdog_info xilinx_wdt_ident = {
	.options =  WDIOF_MAGICCLOSE |
		    WDIOF_KEEPALIVEPING,
	.firmware_version =	1,
	.identity =	WATCHDOG_NAME,
};

static const struct watchdog_ops xilinx_wdt_ops = {
	.owner = THIS_MODULE,
	.start = xilinx_wdt_start,
	.stop = xilinx_wdt_stop,
	.ping = xilinx_wdt_keepalive,
};

static struct watchdog_device xilinx_wdt_wdd = {
	.info = &xilinx_wdt_ident,
	.ops = &xilinx_wdt_ops,
};

static u32 xwdt_selftest(void)
{
	int i;
	u32 timer_value1;
	u32 timer_value2;

	spin_lock(&spinlock);

	timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET);
	timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);

	for (i = 0;
		((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
			(timer_value2 == timer_value1)); i++) {
		timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
	}

	spin_unlock(&spinlock);

	if (timer_value2 != timer_value1)
		return ~XWT_TIMER_FAILED;
	else
		return XWT_TIMER_FAILED;
}

static int xwdt_probe(struct platform_device *pdev)
{
	int rc;
	u32 *tmptr;
	u32 *pfreq;
	struct resource *res;
	bool no_timeout = false;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	xdev.base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(xdev.base))
		return PTR_ERR(xdev.base);

	pfreq = (u32 *)of_get_property(pdev->dev.of_node,
					"clock-frequency", NULL);

	if (pfreq == NULL) {
		pr_warn("The watchdog clock frequency cannot be obtained!\n");
		no_timeout = true;
	}

	tmptr = (u32 *)of_get_property(pdev->dev.of_node,
					"xlnx,wdt-interval", NULL);
	if (tmptr == NULL) {
		pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
		no_timeout = true;
	} else {
		xdev.wdt_interval = *tmptr;
	}

	tmptr = (u32 *)of_get_property(pdev->dev.of_node,
					"xlnx,wdt-enable-once", NULL);
	if (tmptr == NULL) {
		pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
		watchdog_set_nowayout(&xilinx_wdt_wdd, true);
	}

/*
 *  Twice of the 2^wdt_interval / freq  because the first wdt overflow is
 *  ignored (interrupt), reset is only generated at second wdt overflow
 */
	if (!no_timeout)
		timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);

	rc = xwdt_selftest();
	if (rc == XWT_TIMER_FAILED) {
		pr_err("SelfTest routine error!\n");
		return rc;
	}

	rc = watchdog_register_device(&xilinx_wdt_wdd);
	if (rc) {
		pr_err("cannot register watchdog (err=%d)\n", rc);
		return rc;
	}

	dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
		 xdev.base, timeout);

	return 0;
}

static int xwdt_remove(struct platform_device *dev)
{
	watchdog_unregister_device(&xilinx_wdt_wdd);

	return 0;
}

/* Match table for of_platform binding */
static struct of_device_id xwdt_of_match[] = {
	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
	{},
};
MODULE_DEVICE_TABLE(of, xwdt_of_match);

static struct platform_driver xwdt_driver = {
	.probe       = xwdt_probe,
	.remove      = xwdt_remove,
	.driver = {
		.owner = THIS_MODULE,
		.name  = WATCHDOG_NAME,
		.of_match_table = xwdt_of_match,
	},
};

module_platform_driver(xwdt_driver);

MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
MODULE_DESCRIPTION("Xilinx Watchdog driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
e9659e69	1	/*
9419c07c MS	2	* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
9419c07c MS	3	*
d14fd964	4	* (C) Copyright 2013 - 2014 Xilinx, Inc.
9419c07c MS	5	* (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*/
e9659e69	12
27c766aa JP	13	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	14
f06cdfd1	15	#include <linux/err.h>
e9659e69 AC	16	#include <linux/module.h>
	17	#include <linux/types.h>
	18	#include <linux/kernel.h>
e9659e69 AC	19	#include <linux/ioport.h>
	20	#include <linux/watchdog.h>
	21	#include <linux/io.h>
e9659e69 AC	22	#include <linux/of.h>
	23	#include <linux/of_device.h>
	24	#include <linux/of_address.h>
	25
	26	/* Register offsets for the Wdt device */
	27	#define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
	28	#define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
	29	#define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
	30
	31	/* Control/Status Register Masks */
	32	#define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
	33	#define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
	34	#define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
	35
	36	/* Control/Status Register 0/1 bits */
	37	#define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
	38
	39	/* SelfTest constants */
	40	#define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
	41	#define XWT_TIMER_FAILED 0xFFFFFFFF
	42
	43	#define WATCHDOG_NAME "Xilinx Watchdog"
	44	#define PFX WATCHDOG_NAME ": "
	45
	46	struct xwdt_device {
e9659e69	47	void __iomem *base;
e9659e69	48	u32 wdt_interval;
e9659e69 AC	49	};
	50
	51	static struct xwdt_device xdev;
	52
	53	static u32 timeout;
e9659e69 AC	54
	55	static DEFINE_SPINLOCK(spinlock);
	56
d14fd964	57	static int xilinx_wdt_start(struct watchdog_device *wdd)
e9659e69	58	{
5cf4e69d MS	59	u32 control_status_reg;
5cf4e69d MS	60
e9659e69 AC	61	spin_lock(&spinlock);
	62
	63	/* Clean previous status and enable the watchdog timer */
	64	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
	65	control_status_reg \|= (XWT_CSR0_WRS_MASK \| XWT_CSR0_WDS_MASK);
	66
	67	iowrite32((control_status_reg \| XWT_CSR0_EWDT1_MASK),
	68	xdev.base + XWT_TWCSR0_OFFSET);
	69
	70	iowrite32(XWT_CSRX_EWDT2_MASK, xdev.base + XWT_TWCSR1_OFFSET);
	71
	72	spin_unlock(&spinlock);
d14fd964 MS	73
d14fd964 MS	74	return 0;
e9659e69 AC	75	}
e9659e69 AC	76
d14fd964	77	static int xilinx_wdt_stop(struct watchdog_device *wdd)
e9659e69	78	{
5cf4e69d MS	79	u32 control_status_reg;
5cf4e69d MS	80
e9659e69 AC	81	spin_lock(&spinlock);
	82
	83	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
	84
	85	iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
	86	xdev.base + XWT_TWCSR0_OFFSET);
	87
	88	iowrite32(0, xdev.base + XWT_TWCSR1_OFFSET);
	89
	90	spin_unlock(&spinlock);
27c766aa	91	pr_info("Stopped!\n");
d14fd964 MS	92
d14fd964 MS	93	return 0;
e9659e69 AC	94	}
e9659e69 AC	95
d14fd964	96	static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
e9659e69	97	{
5cf4e69d MS	98	u32 control_status_reg;
5cf4e69d MS	99
e9659e69 AC	100	spin_lock(&spinlock);
	101
	102	control_status_reg = ioread32(xdev.base + XWT_TWCSR0_OFFSET);
	103	control_status_reg \|= (XWT_CSR0_WRS_MASK \| XWT_CSR0_WDS_MASK);
	104	iowrite32(control_status_reg, xdev.base + XWT_TWCSR0_OFFSET);
	105
	106	spin_unlock(&spinlock);
e9659e69	107
d14fd964 MS	108	return 0;
d14fd964 MS	109	}
e9659e69	110
d14fd964 MS	111	static const struct watchdog_info xilinx_wdt_ident = {
	112	.options = WDIOF_MAGICCLOSE \|
	113	WDIOF_KEEPALIVEPING,
	114	.firmware_version = 1,
	115	.identity = WATCHDOG_NAME,
	116	};
e9659e69	117
d14fd964 MS	118	static const struct watchdog_ops xilinx_wdt_ops = {
	119	.owner = THIS_MODULE,
	120	.start = xilinx_wdt_start,
	121	.stop = xilinx_wdt_stop,
	122	.ping = xilinx_wdt_keepalive,
	123	};
e9659e69	124
d14fd964 MS	125	static struct watchdog_device xilinx_wdt_wdd = {
	126	.info = &xilinx_wdt_ident,
	127	.ops = &xilinx_wdt_ops,
	128	};
e9659e69 AC	129
	130	static u32 xwdt_selftest(void)
	131	{
	132	int i;
	133	u32 timer_value1;
	134	u32 timer_value2;
	135
	136	spin_lock(&spinlock);
	137
	138	timer_value1 = ioread32(xdev.base + XWT_TBR_OFFSET);
	139	timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
	140
	141	for (i = 0;
	142	((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
	143	(timer_value2 == timer_value1)); i++) {
	144	timer_value2 = ioread32(xdev.base + XWT_TBR_OFFSET);
	145	}
	146
	147	spin_unlock(&spinlock);
	148
	149	if (timer_value2 != timer_value1)
	150	return ~XWT_TIMER_FAILED;
	151	else
	152	return XWT_TIMER_FAILED;
	153	}
	154
2d991a16	155	static int xwdt_probe(struct platform_device *pdev)
e9659e69 AC	156	{
	157	int rc;
	158	u32 *tmptr;
	159	u32 *pfreq;
f06cdfd1	160	struct resource *res;
ffb8eee4	161	bool no_timeout = false;
e9659e69	162
f06cdfd1 MS	163	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	164	xdev.base = devm_ioremap_resource(&pdev->dev, res);
	165	if (IS_ERR(xdev.base))
	166	return PTR_ERR(xdev.base);
	167
90fe6c60	168	pfreq = (u32 *)of_get_property(pdev->dev.of_node,
e9659e69 AC	169	"clock-frequency", NULL);
	170
	171	if (pfreq == NULL) {
27c766aa	172	pr_warn("The watchdog clock frequency cannot be obtained!\n");
ffb8eee4	173	no_timeout = true;
e9659e69 AC	174	}
e9659e69 AC	175
e9659e69 AC	176	tmptr = (u32 *)of_get_property(pdev->dev.of_node,
	177	"xlnx,wdt-interval", NULL);
	178	if (tmptr == NULL) {
27c766aa	179	pr_warn("Parameter \"xlnx,wdt-interval\" not found in device tree!\n");
ffb8eee4	180	no_timeout = true;
e9659e69 AC	181	} else {
	182	xdev.wdt_interval = *tmptr;
	183	}
	184
	185	tmptr = (u32 *)of_get_property(pdev->dev.of_node,
	186	"xlnx,wdt-enable-once", NULL);
	187	if (tmptr == NULL) {
27c766aa	188	pr_warn("Parameter \"xlnx,wdt-enable-once\" not found in device tree!\n");
d14fd964	189	watchdog_set_nowayout(&xilinx_wdt_wdd, true);
e9659e69 AC	190	}
	191
	192	/*
	193	* Twice of the 2^wdt_interval / freq because the first wdt overflow is
	194	* ignored (interrupt), reset is only generated at second wdt overflow
	195	*/
	196	if (!no_timeout)
	197	timeout = 2 * ((1<<xdev.wdt_interval) / *pfreq);
	198
e9659e69 AC	199	rc = xwdt_selftest();
e9659e69 AC	200	if (rc == XWT_TIMER_FAILED) {
27c766aa	201	pr_err("SelfTest routine error!\n");
f06cdfd1	202	return rc;
e9659e69 AC	203	}
e9659e69 AC	204
d14fd964	205	rc = watchdog_register_device(&xilinx_wdt_wdd);
e9659e69	206	if (rc) {
d14fd964	207	pr_err("cannot register watchdog (err=%d)\n", rc);
f06cdfd1	208	return rc;
e9659e69 AC	209	}
e9659e69 AC	210
d14fd964 MS	211	dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
d14fd964 MS	212	xdev.base, timeout);
e9659e69 AC	213
e9659e69 AC	214	return 0;
e9659e69 AC	215	}
e9659e69 AC	216
4b12b896	217	static int xwdt_remove(struct platform_device *dev)
e9659e69	218	{
d14fd964	219	watchdog_unregister_device(&xilinx_wdt_wdd);
e9659e69 AC	220
	221	return 0;
	222	}
	223
	224	/* Match table for of_platform binding */
1d131368	225	static struct of_device_id xwdt_of_match[] = {
8fce9b36	226	{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
e9659e69 AC	227	{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
	228	{},
	229	};
	230	MODULE_DEVICE_TABLE(of, xwdt_of_match);
	231
	232	static struct platform_driver xwdt_driver = {
	233	.probe = xwdt_probe,
82268714	234	.remove = xwdt_remove,
e9659e69 AC	235	.driver = {
	236	.owner = THIS_MODULE,
	237	.name = WATCHDOG_NAME,
	238	.of_match_table = xwdt_of_match,
	239	},
	240	};
	241
b8ec6118	242	module_platform_driver(xwdt_driver);
e9659e69 AC	243
	244	MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
	245	MODULE_DESCRIPTION("Xilinx Watchdog driver");
9419c07c	246	MODULE_LICENSE("GPL v2");