[mirror_ubuntu-hirsute-kernel.git] / drivers / watchdog / omap_wdt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/omap-wd-timer.h>

#include "omap_wdt.h"

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

#define to_omap_wdt_dev(_wdog)	container_of(_wdog, struct omap_wdt_dev, wdog)

static bool early_enable;
module_param(early_enable, bool, 0);
MODULE_PARM_DESC(early_enable,
	"Watchdog is started on module insertion (default=0)");

struct omap_wdt_dev {
	struct watchdog_device wdog;
	void __iomem    *base;          /* physical */
	struct device   *dev;
	bool		omap_wdt_users;
	int		wdt_trgr_pattern;
	struct mutex	lock;		/* to avoid races with PM */
};

static void omap_wdt_reload(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
				   unsigned int timeout)
{
	u32 pre_margin = GET_WLDR_VAL(timeout);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

static int omap_wdt_start(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;

	mutex_lock(&wdev->lock);

	wdev->omap_wdt_users = true;

	pm_runtime_get_sync(wdev->dev);

	/*
	 * Make sure the watchdog is disabled. This is unfortunately required
	 * because writing to various registers with the watchdog running has no
	 * effect.
	 */
	omap_wdt_disable(wdev);

	/* initialize prescaler */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timer(wdev, wdog->timeout);
	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_stop(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	pm_runtime_put_sync(wdev->dev);
	wdev->omap_wdt_users = false;
	mutex_unlock(&wdev->lock);
	return 0;
}

static int omap_wdt_ping(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_reload(wdev);
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int timeout)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	omap_wdt_set_timer(wdev, timeout);
	omap_wdt_enable(wdev);
	omap_wdt_reload(wdev);
	wdog->timeout = timeout;
	mutex_unlock(&wdev->lock);

	return 0;
}

static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
	void __iomem *base = wdev->base;
	u32 value;

	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	return GET_WCCR_SECS(value);
}

static const struct watchdog_info omap_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
	.identity = "OMAP Watchdog",
};

static const struct watchdog_ops omap_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= omap_wdt_start,
	.stop		= omap_wdt_stop,
	.ping		= omap_wdt_ping,
	.set_timeout	= omap_wdt_set_timeout,
	.get_timeleft	= omap_wdt_get_timeleft,
};

static int omap_wdt_probe(struct platform_device *pdev)
{
	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct omap_wdt_dev *wdev;
	int ret;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	wdev->omap_wdt_users	= false;
	wdev->dev		= &pdev->dev;
	wdev->wdt_trgr_pattern	= 0x1234;
	mutex_init(&wdev->lock);

	/* reserve static register mappings */
	wdev->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdev->base))
		return PTR_ERR(wdev->base);

	wdev->wdog.info = &omap_wdt_info;
	wdev->wdog.ops = &omap_wdt_ops;
	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
	wdev->wdog.parent = &pdev->dev;

	watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);

	watchdog_set_nowayout(&wdev->wdog, nowayout);

	platform_set_drvdata(pdev, wdev);

	pm_runtime_enable(wdev->dev);
	pm_runtime_get_sync(wdev->dev);

	if (pdata && pdata->read_reset_sources) {
		u32 rs = pdata->read_reset_sources();
		if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
			wdev->wdog.bootstatus = WDIOF_CARDRESET;
	}

	if (!early_enable)
		omap_wdt_disable(wdev);

	ret = watchdog_register_device(&wdev->wdog);
	if (ret) {
		pm_runtime_put(wdev->dev);
		pm_runtime_disable(wdev->dev);
		return ret;
	}

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		wdev->wdog.timeout);

	if (early_enable)
		omap_wdt_start(&wdev->wdog);

	pm_runtime_put(wdev->dev);

	return 0;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	pm_runtime_disable(wdev->dev);
	watchdog_unregister_device(&wdev->wdog);

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		pm_runtime_get_sync(wdev->dev);
		omap_wdt_enable(wdev);
		omap_wdt_reload(wdev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static const struct of_device_id omap_wdt_of_match[] = {
	{ .compatible = "ti,omap3-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, omap_wdt_of_match);

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.name	= "omap_wdt",
		.of_match_table = omap_wdt_of_match,
	},
};

module_platform_driver(omap_wdt_driver);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
d0173278	1	// SPDX-License-Identifier: GPL-2.0
7768a13c	2	/*
2817142f	3	* omap_wdt.c
7768a13c	4	*
2817142f	5	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	6	*
	7	* Author: MontaVista Software, Inc.
	8	* <gdavis@mvista.com> or <source@mvista.com>
	9	*
d0173278	10	* 2003 (c) MontaVista Software, Inc.
7768a13c KS	11	*
	12	* History:
	13	*
	14	* 20030527: George G. Davis <gdavis@mvista.com>
	15	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	16	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586	17	* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c KS	18	*
	19	* Copyright (c) 2004 Texas Instruments.
	20	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	21	* 2. Ported to 2.6 kernel
	22	*
	23	* Copyright (c) 2005 David Brownell
	24	* Use the driver model and standard identifiers; handle bigger timeouts.
	25	*/
	26
27c766aa JP	27	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	28
7768a13c	29	#include <linux/module.h>
ac316725	30	#include <linux/mod_devicetable.h>
7768a13c KS	31	#include <linux/types.h>
7768a13c KS	32	#include <linux/kernel.h>
7768a13c	33	#include <linux/mm.h>
7768a13c KS	34	#include <linux/watchdog.h>
7768a13c KS	35	#include <linux/reboot.h>
7768a13c KS	36	#include <linux/err.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/moduleparam.h>
089ab079	39	#include <linux/io.h>
5a0e3ad6	40	#include <linux/slab.h>
7ec5ad0f	41	#include <linux/pm_runtime.h>
129f5577	42	#include <linux/platform_data/omap-wd-timer.h>
7768a13c KS	43
	44	#include "omap_wdt.h"
	45
2dd7b244 PR	46	static bool nowayout = WATCHDOG_NOWAYOUT;
	47	module_param(nowayout, bool, 0);
	48	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	49	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	50
7768a13c KS	51	static unsigned timer_margin;
	52	module_param(timer_margin, uint, 0);
	53	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	54
d2f78268 UKK	55	#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
d2f78268 UKK	56
b2102eb3 LP	57	static bool early_enable;
	58	module_param(early_enable, bool, 0);
	59	MODULE_PARM_DESC(early_enable,
	60	"Watchdog is started on module insertion (default=0)");
	61
2817142f	62	struct omap_wdt_dev {
d2f78268	63	struct watchdog_device wdog;
2817142f FB	64	void __iomem base; / physical */
2817142f FB	65	struct device *dev;
67c0f554	66	bool omap_wdt_users;
67c0f554 AK	67	int wdt_trgr_pattern;
67c0f554 AK	68	struct mutex lock; /* to avoid races with PM */
2817142f FB	69	};
2817142f FB	70
67c0f554	71	static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c	72	{
2817142f	73	void __iomem *base = wdev->base;
b3112180	74
7768a13c	75	/* wait for posted write to complete */
4a7e94a0	76	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	77	cpu_relax();
b3112180	78
67c0f554	79	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0	80	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	81
7768a13c	82	/* wait for posted write to complete */
4a7e94a0	83	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	84	cpu_relax();
	85	/* reloaded WCRR from WLDR */
	86	}
	87
2817142f	88	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	89	{
b3112180 FB	90	void __iomem *base = wdev->base;
b3112180 FB	91
7768a13c	92	/* Sequence to enable the watchdog */
4a7e94a0 VK	93	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	94	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	95	cpu_relax();
b3112180	96
4a7e94a0 VK	97	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	98	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	99	cpu_relax();
	100	}
	101
2817142f	102	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	103	{
b3112180 FB	104	void __iomem *base = wdev->base;
b3112180 FB	105
7768a13c	106	/* sequence required to disable watchdog */
4a7e94a0 VK	107	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	108	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	109	cpu_relax();
b3112180	110
4a7e94a0 VK	111	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	112	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	113	cpu_relax();
	114	}
	115
67c0f554 AK	116	static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
67c0f554 AK	117	unsigned int timeout)
7768a13c	118	{
67c0f554	119	u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180	120	void __iomem *base = wdev->base;
7768a13c KS	121
7768a13c KS	122	/* just count up at 32 KHz */
4a7e94a0	123	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	124	cpu_relax();
b3112180	125
4a7e94a0 VK	126	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
4a7e94a0 VK	127	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	128	cpu_relax();
	129	}
	130
67c0f554	131	static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c	132	{
d2f78268	133	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180 FB	134	void __iomem *base = wdev->base;
b3112180 FB	135
67c0f554 AK	136	mutex_lock(&wdev->lock);
	137
	138	wdev->omap_wdt_users = true;
7768a13c	139
7ec5ad0f	140	pm_runtime_get_sync(wdev->dev);
7768a13c	141
530c11d4 UKK	142	/*
	143	* Make sure the watchdog is disabled. This is unfortunately required
	144	* because writing to various registers with the watchdog running has no
	145	* effect.
	146	*/
	147	omap_wdt_disable(wdev);
	148
7768a13c	149	/* initialize prescaler */
4a7e94a0	150	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	151	cpu_relax();
b3112180	152
4a7e94a0 VK	153	writel_relaxed((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
4a7e94a0 VK	154	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	155	cpu_relax();
7768a13c KS	156
67c0f554 AK	157	omap_wdt_set_timer(wdev, wdog->timeout);
67c0f554 AK	158	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f	159	omap_wdt_enable(wdev);
b3112180	160
67c0f554 AK	161	mutex_unlock(&wdev->lock);
	162
	163	return 0;
7768a13c KS	164	}
7768a13c KS	165
67c0f554	166	static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c	167	{
d2f78268	168	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	169
67c0f554	170	mutex_lock(&wdev->lock);
2817142f	171	omap_wdt_disable(wdev);
7ec5ad0f	172	pm_runtime_put_sync(wdev->dev);
67c0f554 AK	173	wdev->omap_wdt_users = false;
67c0f554 AK	174	mutex_unlock(&wdev->lock);
7768a13c KS	175	return 0;
	176	}
	177
67c0f554	178	static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c	179	{
d2f78268	180	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
b3112180	181
67c0f554 AK	182	mutex_lock(&wdev->lock);
	183	omap_wdt_reload(wdev);
	184	mutex_unlock(&wdev->lock);
	185
	186	return 0;
7768a13c KS	187	}
7768a13c KS	188
67c0f554 AK	189	static int omap_wdt_set_timeout(struct watchdog_device *wdog,
67c0f554 AK	190	unsigned int timeout)
7768a13c	191	{
d2f78268	192	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
7768a13c	193
67c0f554 AK	194	mutex_lock(&wdev->lock);
	195	omap_wdt_disable(wdev);
	196	omap_wdt_set_timer(wdev, timeout);
	197	omap_wdt_enable(wdev);
	198	omap_wdt_reload(wdev);
	199	wdog->timeout = timeout;
	200	mutex_unlock(&wdev->lock);
	201
	202	return 0;
7768a13c KS	203	}
7768a13c KS	204
452fafed LP	205	static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
452fafed LP	206	{
de55acd1	207	struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
452fafed LP	208	void __iomem *base = wdev->base;
	209	u32 value;
	210
	211	value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
	212	return GET_WCCR_SECS(value);
	213	}
	214
67c0f554	215	static const struct watchdog_info omap_wdt_info = {
fb1cbeae	216	.options = WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE \| WDIOF_KEEPALIVEPING,
67c0f554 AK	217	.identity = "OMAP Watchdog",
	218	};
	219
	220	static const struct watchdog_ops omap_wdt_ops = {
	221	.owner = THIS_MODULE,
	222	.start = omap_wdt_start,
	223	.stop = omap_wdt_stop,
	224	.ping = omap_wdt_ping,
	225	.set_timeout = omap_wdt_set_timeout,
452fafed	226	.get_timeleft = omap_wdt_get_timeleft,
7768a13c KS	227	};
7768a13c KS	228
2d991a16	229	static int omap_wdt_probe(struct platform_device *pdev)
7768a13c	230	{
bc8fdfbe	231	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
2817142f	232	struct omap_wdt_dev *wdev;
b3112180	233	int ret;
7768a13c	234
4f4753d9 AK	235	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	236	if (!wdev)
	237	return -ENOMEM;
b3112180	238
67c0f554	239	wdev->omap_wdt_users = false;
67c0f554 AK	240	wdev->dev = &pdev->dev;
	241	wdev->wdt_trgr_pattern = 0x1234;
	242	mutex_init(&wdev->lock);
2817142f	243
6e272061	244	/* reserve static register mappings */
0f0a6a28	245	wdev->base = devm_platform_ioremap_resource(pdev, 0);
6e272061 JH	246	if (IS_ERR(wdev->base))
6e272061 JH	247	return PTR_ERR(wdev->base);
9f69e3b0	248
d2f78268 UKK	249	wdev->wdog.info = &omap_wdt_info;
	250	wdev->wdog.ops = &omap_wdt_ops;
	251	wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
	252	wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
1253730e	253	wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
6551881c	254	wdev->wdog.parent = &pdev->dev;
67c0f554	255
1253730e	256	watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);
67c0f554	257
d2f78268	258	watchdog_set_nowayout(&wdev->wdog, nowayout);
67c0f554	259
d2f78268	260	platform_set_drvdata(pdev, wdev);
7768a13c	261
7ec5ad0f VC	262	pm_runtime_enable(wdev->dev);
7ec5ad0f VC	263	pm_runtime_get_sync(wdev->dev);
789cd470	264
0b3330f3 UKK	265	if (pdata && pdata->read_reset_sources) {
	266	u32 rs = pdata->read_reset_sources();
	267	if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
	268	wdev->wdog.bootstatus = WDIOF_CARDRESET;
	269	}
7768a13c	270
8605fec1 UKK	271	if (!early_enable)
8605fec1 UKK	272	omap_wdt_disable(wdev);
2817142f	273
d2f78268	274	ret = watchdog_register_device(&wdev->wdog);
1ba85387	275	if (ret) {
a2257374	276	pm_runtime_put(wdev->dev);
1ba85387 AK	277	pm_runtime_disable(wdev->dev);
	278	return ret;
	279	}
7768a13c	280
2817142f	281	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0	282	readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
d2f78268	283	wdev->wdog.timeout);
7768a13c	284
b2102eb3 LP	285	if (early_enable)
	286	omap_wdt_start(&wdev->wdog);
	287
a6392490 UKK	288	pm_runtime_put(wdev->dev);
a6392490 UKK	289
7768a13c	290	return 0;
7768a13c KS	291	}
	292
	293	static void omap_wdt_shutdown(struct platform_device *pdev)
	294	{
d2f78268	295	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	296
67c0f554	297	mutex_lock(&wdev->lock);
0503add9	298	if (wdev->omap_wdt_users) {
2817142f	299	omap_wdt_disable(wdev);
0503add9 PW	300	pm_runtime_put_sync(wdev->dev);
0503add9 PW	301	}
67c0f554	302	mutex_unlock(&wdev->lock);
7768a13c KS	303	}
7768a13c KS	304
4b12b896	305	static int omap_wdt_remove(struct platform_device *pdev)
7768a13c	306	{
d2f78268	307	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f	308
12c583d8	309	pm_runtime_disable(wdev->dev);
d2f78268	310	watchdog_unregister_device(&wdev->wdog);
b3112180	311
7768a13c KS	312	return 0;
	313	}
	314
	315	#ifdef CONFIG_PM
	316
	317	/* REVISIT ... not clear this is the best way to handle system suspend; and
	318	* it's very inappropriate for selective device suspend (e.g. suspending this
	319	* through sysfs rather than by stopping the watchdog daemon). Also, this
	320	* may not play well enough with NOWAYOUT...
	321	*/
	322
	323	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	324	{
d2f78268	325	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	326
67c0f554	327	mutex_lock(&wdev->lock);
0503add9	328	if (wdev->omap_wdt_users) {
2817142f	329	omap_wdt_disable(wdev);
0503add9 PW	330	pm_runtime_put_sync(wdev->dev);
0503add9 PW	331	}
67c0f554	332	mutex_unlock(&wdev->lock);
b3112180	333
7768a13c KS	334	return 0;
	335	}
	336
	337	static int omap_wdt_resume(struct platform_device *pdev)
	338	{
d2f78268	339	struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
b3112180	340
67c0f554	341	mutex_lock(&wdev->lock);
2817142f	342	if (wdev->omap_wdt_users) {
0503add9	343	pm_runtime_get_sync(wdev->dev);
2817142f	344	omap_wdt_enable(wdev);
67c0f554	345	omap_wdt_reload(wdev);
7768a13c	346	}
67c0f554	347	mutex_unlock(&wdev->lock);
b3112180	348
7768a13c KS	349	return 0;
	350	}
	351
	352	#else
	353	#define omap_wdt_suspend NULL
	354	#define omap_wdt_resume NULL
	355	#endif
	356
e6ca04ea XJ	357	static const struct of_device_id omap_wdt_of_match[] = {
	358	{ .compatible = "ti,omap3-wdt", },
	359	{},
	360	};
	361	MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
	362
7768a13c KS	363	static struct platform_driver omap_wdt_driver = {
7768a13c KS	364	.probe = omap_wdt_probe,
82268714	365	.remove = omap_wdt_remove,
7768a13c KS	366	.shutdown = omap_wdt_shutdown,
	367	.suspend = omap_wdt_suspend,
	368	.resume = omap_wdt_resume,
	369	.driver = {
7768a13c	370	.name = "omap_wdt",
e6ca04ea	371	.of_match_table = omap_wdt_of_match,
7768a13c KS	372	},
	373	};
	374
b8ec6118	375	module_platform_driver(omap_wdt_driver);
7768a13c KS	376
	377	MODULE_AUTHOR("George G. Davis");
	378	MODULE_LICENSE("GPL");
f37d193c	379	MODULE_ALIAS("platform:omap_wdt");