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7768a13c 1/*
2817142f 2 * omap_wdt.c
7768a13c 3 *
2817142f 4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c
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5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586 19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c
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20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
27c766aa
JP
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
7768a13c 31#include <linux/module.h>
7768a13c
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32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/fs.h>
35#include <linux/mm.h>
36#include <linux/miscdevice.h>
37#include <linux/watchdog.h>
38#include <linux/reboot.h>
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39#include <linux/init.h>
40#include <linux/err.h>
41#include <linux/platform_device.h>
42#include <linux/moduleparam.h>
1977f032 43#include <linux/bitops.h>
089ab079 44#include <linux/io.h>
12b9df7d 45#include <linux/uaccess.h>
5a0e3ad6 46#include <linux/slab.h>
7ec5ad0f 47#include <linux/pm_runtime.h>
129f5577 48#include <linux/platform_data/omap-wd-timer.h>
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49
50#include "omap_wdt.h"
51
2817142f
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52static struct platform_device *omap_wdt_dev;
53
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54static unsigned timer_margin;
55module_param(timer_margin, uint, 0);
56MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
57
7768a13c 58static unsigned int wdt_trgr_pattern = 0x1234;
1334f329 59static DEFINE_SPINLOCK(wdt_lock);
7768a13c 60
2817142f
FB
61struct omap_wdt_dev {
62 void __iomem *base; /* physical */
63 struct device *dev;
64 int omap_wdt_users;
2817142f
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65 struct resource *mem;
66 struct miscdevice omap_wdt_miscdev;
67};
68
69static void omap_wdt_ping(struct omap_wdt_dev *wdev)
7768a13c 70{
2817142f 71 void __iomem *base = wdev->base;
b3112180 72
7768a13c 73 /* wait for posted write to complete */
9f69e3b0 74 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c 75 cpu_relax();
b3112180 76
7768a13c 77 wdt_trgr_pattern = ~wdt_trgr_pattern;
9f69e3b0 78 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180 79
7768a13c 80 /* wait for posted write to complete */
9f69e3b0 81 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
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82 cpu_relax();
83 /* reloaded WCRR from WLDR */
84}
85
2817142f 86static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c 87{
b3112180
FB
88 void __iomem *base = wdev->base;
89
7768a13c 90 /* Sequence to enable the watchdog */
9f69e3b0
FB
91 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
92 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c 93 cpu_relax();
b3112180 94
9f69e3b0
FB
95 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
96 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
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97 cpu_relax();
98}
99
2817142f 100static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c 101{
b3112180
FB
102 void __iomem *base = wdev->base;
103
7768a13c 104 /* sequence required to disable watchdog */
9f69e3b0
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105 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
106 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c 107 cpu_relax();
b3112180 108
9f69e3b0
FB
109 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
110 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
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111 cpu_relax();
112}
113
114static void omap_wdt_adjust_timeout(unsigned new_timeout)
115{
116 if (new_timeout < TIMER_MARGIN_MIN)
117 new_timeout = TIMER_MARGIN_DEFAULT;
118 if (new_timeout > TIMER_MARGIN_MAX)
119 new_timeout = TIMER_MARGIN_MAX;
120 timer_margin = new_timeout;
121}
122
2817142f 123static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
7768a13c
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124{
125 u32 pre_margin = GET_WLDR_VAL(timer_margin);
b3112180 126 void __iomem *base = wdev->base;
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127
128 /* just count up at 32 KHz */
9f69e3b0 129 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c 130 cpu_relax();
b3112180 131
9f69e3b0
FB
132 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
133 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
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134 cpu_relax();
135}
136
137/*
138 * Allow only one task to hold it open
139 */
7768a13c
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140static int omap_wdt_open(struct inode *inode, struct file *file)
141{
b3112180
FB
142 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
143 void __iomem *base = wdev->base;
144
2817142f 145 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
7768a13c
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146 return -EBUSY;
147
7ec5ad0f 148 pm_runtime_get_sync(wdev->dev);
7768a13c
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149
150 /* initialize prescaler */
9f69e3b0 151 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c 152 cpu_relax();
b3112180 153
9f69e3b0
FB
154 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
155 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c
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156 cpu_relax();
157
2817142f
FB
158 file->private_data = (void *) wdev;
159
160 omap_wdt_set_timeout(wdev);
789cd470 161 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
2817142f 162 omap_wdt_enable(wdev);
b3112180 163
ec9505a7 164 return nonseekable_open(inode, file);
7768a13c
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165}
166
167static int omap_wdt_release(struct inode *inode, struct file *file)
168{
b3112180
FB
169 struct omap_wdt_dev *wdev = file->private_data;
170
7768a13c
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171 /*
172 * Shut off the timer unless NOWAYOUT is defined.
173 */
174#ifndef CONFIG_WATCHDOG_NOWAYOUT
2817142f 175 omap_wdt_disable(wdev);
7768a13c 176
7ec5ad0f 177 pm_runtime_put_sync(wdev->dev);
7768a13c 178#else
27c766aa 179 pr_crit("Unexpected close, not stopping!\n");
7768a13c 180#endif
2817142f 181 wdev->omap_wdt_users = 0;
b3112180 182
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183 return 0;
184}
185
12b9df7d 186static ssize_t omap_wdt_write(struct file *file, const char __user *data,
7768a13c
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187 size_t len, loff_t *ppos)
188{
b3112180
FB
189 struct omap_wdt_dev *wdev = file->private_data;
190
7768a13c 191 /* Refresh LOAD_TIME. */
12b9df7d
AC
192 if (len) {
193 spin_lock(&wdt_lock);
2817142f 194 omap_wdt_ping(wdev);
12b9df7d
AC
195 spin_unlock(&wdt_lock);
196 }
7768a13c
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197 return len;
198}
199
12b9df7d
AC
200static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
201 unsigned long arg)
7768a13c 202{
129f5577 203 struct omap_wd_timer_platform_data *pdata;
2817142f 204 struct omap_wdt_dev *wdev;
129f5577
PW
205 u32 rs;
206 int new_margin, bs;
12b9df7d 207 static const struct watchdog_info ident = {
7768a13c
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208 .identity = "OMAP Watchdog",
209 .options = WDIOF_SETTIMEOUT,
210 .firmware_version = 0,
211 };
b3112180 212
2817142f 213 wdev = file->private_data;
129f5577 214 pdata = wdev->dev->platform_data;
7768a13c
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215
216 switch (cmd) {
7768a13c
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217 case WDIOC_GETSUPPORT:
218 return copy_to_user((struct watchdog_info __user *)arg, &ident,
219 sizeof(ident));
220 case WDIOC_GETSTATUS:
221 return put_user(0, (int __user *)arg);
222 case WDIOC_GETBOOTSTATUS:
129f5577
PW
223 if (!pdata || !pdata->read_reset_sources)
224 return put_user(0, (int __user *)arg);
225 rs = pdata->read_reset_sources();
226 bs = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ?
227 WDIOF_CARDRESET : 0;
228 return put_user(bs, (int __user *)arg);
7768a13c 229 case WDIOC_KEEPALIVE:
12b9df7d 230 spin_lock(&wdt_lock);
2817142f 231 omap_wdt_ping(wdev);
12b9df7d 232 spin_unlock(&wdt_lock);
7768a13c
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233 return 0;
234 case WDIOC_SETTIMEOUT:
235 if (get_user(new_margin, (int __user *)arg))
236 return -EFAULT;
237 omap_wdt_adjust_timeout(new_margin);
238
12b9df7d 239 spin_lock(&wdt_lock);
2817142f
FB
240 omap_wdt_disable(wdev);
241 omap_wdt_set_timeout(wdev);
242 omap_wdt_enable(wdev);
7768a13c 243
2817142f 244 omap_wdt_ping(wdev);
12b9df7d 245 spin_unlock(&wdt_lock);
7768a13c
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246 /* Fall */
247 case WDIOC_GETTIMEOUT:
248 return put_user(timer_margin, (int __user *)arg);
0c06090c
WVS
249 default:
250 return -ENOTTY;
7768a13c
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251 }
252}
253
2b8693c0 254static const struct file_operations omap_wdt_fops = {
7768a13c
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255 .owner = THIS_MODULE,
256 .write = omap_wdt_write,
12b9df7d 257 .unlocked_ioctl = omap_wdt_ioctl,
7768a13c
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258 .open = omap_wdt_open,
259 .release = omap_wdt_release,
6038f373 260 .llseek = no_llseek,
7768a13c
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261};
262
2d991a16 263static int omap_wdt_probe(struct platform_device *pdev)
7768a13c
KS
264{
265 struct resource *res, *mem;
2817142f 266 struct omap_wdt_dev *wdev;
b3112180 267 int ret;
7768a13c
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268
269 /* reserve static register mappings */
270 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b3112180
FB
271 if (!res) {
272 ret = -ENOENT;
273 goto err_get_resource;
274 }
7768a13c 275
b3112180
FB
276 if (omap_wdt_dev) {
277 ret = -EBUSY;
278 goto err_busy;
279 }
2817142f 280
b782a563 281 mem = request_mem_region(res->start, resource_size(res), pdev->name);
b3112180
FB
282 if (!mem) {
283 ret = -EBUSY;
284 goto err_busy;
285 }
7768a13c 286
2817142f
FB
287 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
288 if (!wdev) {
289 ret = -ENOMEM;
b3112180 290 goto err_kzalloc;
2817142f 291 }
b3112180 292
2817142f
FB
293 wdev->omap_wdt_users = 0;
294 wdev->mem = mem;
7ec5ad0f 295 wdev->dev = &pdev->dev;
2817142f 296
b782a563 297 wdev->base = ioremap(res->start, resource_size(res));
9f69e3b0
FB
298 if (!wdev->base) {
299 ret = -ENOMEM;
b3112180 300 goto err_ioremap;
9f69e3b0
FB
301 }
302
2817142f 303 platform_set_drvdata(pdev, wdev);
7768a13c 304
7ec5ad0f
VC
305 pm_runtime_enable(wdev->dev);
306 pm_runtime_get_sync(wdev->dev);
789cd470 307
2817142f 308 omap_wdt_disable(wdev);
7768a13c
KS
309 omap_wdt_adjust_timeout(timer_margin);
310
2817142f
FB
311 wdev->omap_wdt_miscdev.parent = &pdev->dev;
312 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
313 wdev->omap_wdt_miscdev.name = "watchdog";
314 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
315
316 ret = misc_register(&(wdev->omap_wdt_miscdev));
7768a13c 317 if (ret)
b3112180 318 goto err_misc;
7768a13c 319
2817142f 320 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
9f69e3b0 321 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
2817142f 322 timer_margin);
7768a13c 323
7ec5ad0f 324 pm_runtime_put_sync(wdev->dev);
789cd470 325
2817142f
FB
326 omap_wdt_dev = pdev;
327
7768a13c
KS
328 return 0;
329
b3112180 330err_misc:
12c583d8 331 pm_runtime_disable(wdev->dev);
b3112180
FB
332 platform_set_drvdata(pdev, NULL);
333 iounmap(wdev->base);
334
335err_ioremap:
336 wdev->base = NULL;
b3112180
FB
337 kfree(wdev);
338
339err_kzalloc:
b782a563 340 release_mem_region(res->start, resource_size(res));
b3112180
FB
341
342err_busy:
343err_get_resource:
344
7768a13c
KS
345 return ret;
346}
347
348static void omap_wdt_shutdown(struct platform_device *pdev)
349{
b3112180 350 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f 351
0503add9 352 if (wdev->omap_wdt_users) {
2817142f 353 omap_wdt_disable(wdev);
0503add9
PW
354 pm_runtime_put_sync(wdev->dev);
355 }
7768a13c
KS
356}
357
4b12b896 358static int omap_wdt_remove(struct platform_device *pdev)
7768a13c 359{
b3112180 360 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f
FB
361 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
362
12c583d8 363 pm_runtime_disable(wdev->dev);
2817142f
FB
364 if (!res)
365 return -ENOENT;
366
367 misc_deregister(&(wdev->omap_wdt_miscdev));
b782a563 368 release_mem_region(res->start, resource_size(res));
2817142f 369 platform_set_drvdata(pdev, NULL);
b3112180 370
9f69e3b0
FB
371 iounmap(wdev->base);
372
2817142f
FB
373 kfree(wdev);
374 omap_wdt_dev = NULL;
b3112180 375
7768a13c
KS
376 return 0;
377}
378
379#ifdef CONFIG_PM
380
381/* REVISIT ... not clear this is the best way to handle system suspend; and
382 * it's very inappropriate for selective device suspend (e.g. suspending this
383 * through sysfs rather than by stopping the watchdog daemon). Also, this
384 * may not play well enough with NOWAYOUT...
385 */
386
387static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
388{
b3112180
FB
389 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
390
0503add9 391 if (wdev->omap_wdt_users) {
2817142f 392 omap_wdt_disable(wdev);
0503add9
PW
393 pm_runtime_put_sync(wdev->dev);
394 }
b3112180 395
7768a13c
KS
396 return 0;
397}
398
399static int omap_wdt_resume(struct platform_device *pdev)
400{
b3112180
FB
401 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
402
2817142f 403 if (wdev->omap_wdt_users) {
0503add9 404 pm_runtime_get_sync(wdev->dev);
2817142f
FB
405 omap_wdt_enable(wdev);
406 omap_wdt_ping(wdev);
7768a13c 407 }
b3112180 408
7768a13c
KS
409 return 0;
410}
411
412#else
413#define omap_wdt_suspend NULL
414#define omap_wdt_resume NULL
415#endif
416
e6ca04ea
XJ
417static const struct of_device_id omap_wdt_of_match[] = {
418 { .compatible = "ti,omap3-wdt", },
419 {},
420};
421MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
422
7768a13c
KS
423static struct platform_driver omap_wdt_driver = {
424 .probe = omap_wdt_probe,
82268714 425 .remove = omap_wdt_remove,
7768a13c
KS
426 .shutdown = omap_wdt_shutdown,
427 .suspend = omap_wdt_suspend,
428 .resume = omap_wdt_resume,
429 .driver = {
430 .owner = THIS_MODULE,
431 .name = "omap_wdt",
e6ca04ea 432 .of_match_table = omap_wdt_of_match,
7768a13c
KS
433 },
434};
435
b8ec6118 436module_platform_driver(omap_wdt_driver);
7768a13c
KS
437
438MODULE_AUTHOR("George G. Davis");
439MODULE_LICENSE("GPL");
440MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 441MODULE_ALIAS("platform:omap_wdt");