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Commit | Line | Data |
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22ac9232 | 1 | /* |
3b937a7d | 2 | * drivers/watchdog/orion_wdt.c |
22ac9232 | 3 | * |
3b937a7d | 4 | * Watchdog driver for Orion/Kirkwood processors |
22ac9232 SB |
5 | * |
6 | * Author: Sylver Bruneau <sylver.bruneau@googlemail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
22ac9232 SB |
15 | #include <linux/module.h> |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
22ac9232 | 19 | #include <linux/miscdevice.h> |
9e058d4f | 20 | #include <linux/platform_device.h> |
22ac9232 SB |
21 | #include <linux/watchdog.h> |
22 | #include <linux/init.h> | |
22ac9232 | 23 | #include <linux/io.h> |
6d0f0dfd | 24 | #include <linux/spinlock.h> |
4f04be62 | 25 | #include <linux/clk.h> |
0dd6e484 | 26 | #include <linux/err.h> |
1e7bad0f | 27 | #include <linux/of.h> |
fdd8b079 | 28 | #include <mach/bridge-regs.h> |
22ac9232 SB |
29 | |
30 | /* | |
31 | * Watchdog timer block registers. | |
32 | */ | |
a855a7ce | 33 | #define TIMER_CTRL 0x0000 |
0dd6e484 | 34 | #define WDT_EN 0x0010 |
a855a7ce | 35 | #define WDT_VAL 0x0024 |
22ac9232 | 36 | |
9e058d4f | 37 | #define WDT_MAX_CYCLE_COUNT 0xffffffff |
22ac9232 SB |
38 | #define WDT_IN_USE 0 |
39 | #define WDT_OK_TO_CLOSE 1 | |
40 | ||
fa142ff5 RK |
41 | #define WDT_RESET_OUT_EN BIT(1) |
42 | #define WDT_INT_REQ BIT(3) | |
43 | ||
86a1e189 | 44 | static bool nowayout = WATCHDOG_NOWAYOUT; |
9e058d4f TR |
45 | static int heartbeat = -1; /* module parameter (seconds) */ |
46 | static unsigned int wdt_max_duration; /* (seconds) */ | |
4f04be62 | 47 | static struct clk *clk; |
9e058d4f | 48 | static unsigned int wdt_tclk; |
a855a7ce | 49 | static void __iomem *wdt_reg; |
1334f329 | 50 | static DEFINE_SPINLOCK(wdt_lock); |
22ac9232 | 51 | |
0dd6e484 | 52 | static int orion_wdt_ping(struct watchdog_device *wdt_dev) |
df6707b2 TR |
53 | { |
54 | spin_lock(&wdt_lock); | |
55 | ||
56 | /* Reload watchdog duration */ | |
0dd6e484 | 57 | writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); |
df6707b2 TR |
58 | |
59 | spin_unlock(&wdt_lock); | |
0dd6e484 | 60 | return 0; |
df6707b2 TR |
61 | } |
62 | ||
0dd6e484 | 63 | static int orion_wdt_start(struct watchdog_device *wdt_dev) |
22ac9232 SB |
64 | { |
65 | u32 reg; | |
66 | ||
6d0f0dfd WVS |
67 | spin_lock(&wdt_lock); |
68 | ||
22ac9232 | 69 | /* Set watchdog duration */ |
0dd6e484 | 70 | writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL); |
22ac9232 SB |
71 | |
72 | /* Clear watchdog timer interrupt */ | |
6910ceb5 | 73 | writel(~WDT_INT_REQ, BRIDGE_CAUSE); |
22ac9232 SB |
74 | |
75 | /* Enable watchdog timer */ | |
a855a7ce | 76 | reg = readl(wdt_reg + TIMER_CTRL); |
22ac9232 | 77 | reg |= WDT_EN; |
a855a7ce | 78 | writel(reg, wdt_reg + TIMER_CTRL); |
22ac9232 SB |
79 | |
80 | /* Enable reset on watchdog */ | |
6462c616 TR |
81 | reg = readl(RSTOUTn_MASK); |
82 | reg |= WDT_RESET_OUT_EN; | |
83 | writel(reg, RSTOUTn_MASK); | |
6d0f0dfd WVS |
84 | |
85 | spin_unlock(&wdt_lock); | |
0dd6e484 | 86 | return 0; |
22ac9232 SB |
87 | } |
88 | ||
0dd6e484 | 89 | static int orion_wdt_stop(struct watchdog_device *wdt_dev) |
22ac9232 SB |
90 | { |
91 | u32 reg; | |
92 | ||
6d0f0dfd WVS |
93 | spin_lock(&wdt_lock); |
94 | ||
22ac9232 | 95 | /* Disable reset on watchdog */ |
6462c616 TR |
96 | reg = readl(RSTOUTn_MASK); |
97 | reg &= ~WDT_RESET_OUT_EN; | |
98 | writel(reg, RSTOUTn_MASK); | |
22ac9232 SB |
99 | |
100 | /* Disable watchdog timer */ | |
a855a7ce | 101 | reg = readl(wdt_reg + TIMER_CTRL); |
22ac9232 | 102 | reg &= ~WDT_EN; |
a855a7ce | 103 | writel(reg, wdt_reg + TIMER_CTRL); |
6d0f0dfd WVS |
104 | |
105 | spin_unlock(&wdt_lock); | |
0dd6e484 | 106 | return 0; |
6d0f0dfd WVS |
107 | } |
108 | ||
0dd6e484 | 109 | static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev) |
6d0f0dfd | 110 | { |
0dd6e484 AL |
111 | unsigned int time_left; |
112 | ||
6d0f0dfd | 113 | spin_lock(&wdt_lock); |
0dd6e484 | 114 | time_left = readl(wdt_reg + WDT_VAL) / wdt_tclk; |
6d0f0dfd | 115 | spin_unlock(&wdt_lock); |
22ac9232 | 116 | |
0dd6e484 | 117 | return time_left; |
22ac9232 SB |
118 | } |
119 | ||
0dd6e484 AL |
120 | static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev, |
121 | unsigned int timeout) | |
22ac9232 | 122 | { |
0dd6e484 | 123 | wdt_dev->timeout = timeout; |
df6707b2 TR |
124 | return 0; |
125 | } | |
126 | ||
0dd6e484 AL |
127 | static const struct watchdog_info orion_wdt_info = { |
128 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
129 | .identity = "Orion Watchdog", | |
22ac9232 SB |
130 | }; |
131 | ||
0dd6e484 AL |
132 | static const struct watchdog_ops orion_wdt_ops = { |
133 | .owner = THIS_MODULE, | |
134 | .start = orion_wdt_start, | |
135 | .stop = orion_wdt_stop, | |
136 | .ping = orion_wdt_ping, | |
137 | .set_timeout = orion_wdt_set_timeout, | |
138 | .get_timeleft = orion_wdt_get_timeleft, | |
22ac9232 SB |
139 | }; |
140 | ||
0dd6e484 AL |
141 | static struct watchdog_device orion_wdt = { |
142 | .info = &orion_wdt_info, | |
143 | .ops = &orion_wdt_ops, | |
c1fd5f64 | 144 | .min_timeout = 1, |
22ac9232 SB |
145 | }; |
146 | ||
2d991a16 | 147 | static int orion_wdt_probe(struct platform_device *pdev) |
22ac9232 | 148 | { |
a855a7ce | 149 | struct resource *res; |
22ac9232 SB |
150 | int ret; |
151 | ||
0dd6e484 | 152 | clk = devm_clk_get(&pdev->dev, NULL); |
4f04be62 | 153 | if (IS_ERR(clk)) { |
0dd6e484 | 154 | dev_err(&pdev->dev, "Orion Watchdog missing clock\n"); |
9e058d4f TR |
155 | return -ENODEV; |
156 | } | |
4f04be62 AL |
157 | clk_prepare_enable(clk); |
158 | wdt_tclk = clk_get_rate(clk); | |
9e058d4f | 159 | |
a855a7ce | 160 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8c4c419c JG |
161 | if (!res) |
162 | return -ENODEV; | |
0dd6e484 AL |
163 | wdt_reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
164 | if (!wdt_reg) | |
165 | return -ENOMEM; | |
9e058d4f TR |
166 | |
167 | wdt_max_duration = WDT_MAX_CYCLE_COUNT / wdt_tclk; | |
0dd6e484 | 168 | |
c1fd5f64 | 169 | orion_wdt.timeout = wdt_max_duration; |
0dd6e484 | 170 | orion_wdt.max_timeout = wdt_max_duration; |
c1fd5f64 | 171 | watchdog_init_timeout(&orion_wdt, heartbeat, &pdev->dev); |
0dd6e484 AL |
172 | |
173 | watchdog_set_nowayout(&orion_wdt, nowayout); | |
174 | ret = watchdog_register_device(&orion_wdt); | |
175 | if (ret) { | |
176 | clk_disable_unprepare(clk); | |
9e058d4f | 177 | return ret; |
0dd6e484 | 178 | } |
9e058d4f | 179 | |
27c766aa | 180 | pr_info("Initial timeout %d sec%s\n", |
c1fd5f64 | 181 | orion_wdt.timeout, nowayout ? ", nowayout" : ""); |
9e058d4f TR |
182 | return 0; |
183 | } | |
184 | ||
4b12b896 | 185 | static int orion_wdt_remove(struct platform_device *pdev) |
9e058d4f | 186 | { |
0dd6e484 | 187 | watchdog_unregister_device(&orion_wdt); |
4f04be62 | 188 | clk_disable_unprepare(clk); |
0dd6e484 | 189 | return 0; |
22ac9232 SB |
190 | } |
191 | ||
3b937a7d | 192 | static void orion_wdt_shutdown(struct platform_device *pdev) |
df6707b2 | 193 | { |
0dd6e484 | 194 | orion_wdt_stop(&orion_wdt); |
df6707b2 TR |
195 | } |
196 | ||
1d131368 | 197 | static const struct of_device_id orion_wdt_of_match_table[] = { |
1e7bad0f AL |
198 | { .compatible = "marvell,orion-wdt", }, |
199 | {}, | |
200 | }; | |
201 | MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table); | |
202 | ||
3b937a7d NP |
203 | static struct platform_driver orion_wdt_driver = { |
204 | .probe = orion_wdt_probe, | |
82268714 | 205 | .remove = orion_wdt_remove, |
3b937a7d | 206 | .shutdown = orion_wdt_shutdown, |
9e058d4f TR |
207 | .driver = { |
208 | .owner = THIS_MODULE, | |
3b937a7d | 209 | .name = "orion_wdt", |
1e7bad0f | 210 | .of_match_table = of_match_ptr(orion_wdt_of_match_table), |
9e058d4f TR |
211 | }, |
212 | }; | |
213 | ||
b8ec6118 | 214 | module_platform_driver(orion_wdt_driver); |
22ac9232 SB |
215 | |
216 | MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>"); | |
3b937a7d | 217 | MODULE_DESCRIPTION("Orion Processor Watchdog"); |
22ac9232 SB |
218 | |
219 | module_param(heartbeat, int, 0); | |
df6707b2 | 220 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); |
22ac9232 | 221 | |
86a1e189 | 222 | module_param(nowayout, bool, 0); |
df6707b2 TR |
223 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
224 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
22ac9232 SB |
225 | |
226 | MODULE_LICENSE("GPL"); | |
f3ea733e | 227 | MODULE_ALIAS("platform:orion_wdt"); |
22ac9232 | 228 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |