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Commit | Line | Data |
---|---|---|
22ac9232 | 1 | /* |
3b937a7d | 2 | * drivers/watchdog/orion_wdt.c |
22ac9232 | 3 | * |
3b937a7d | 4 | * Watchdog driver for Orion/Kirkwood processors |
22ac9232 SB |
5 | * |
6 | * Author: Sylver Bruneau <sylver.bruneau@googlemail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
27c766aa JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
22ac9232 SB |
15 | #include <linux/module.h> |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/kernel.h> | |
9e058d4f | 19 | #include <linux/platform_device.h> |
22ac9232 | 20 | #include <linux/watchdog.h> |
e97662e1 | 21 | #include <linux/interrupt.h> |
22ac9232 | 22 | #include <linux/io.h> |
4f04be62 | 23 | #include <linux/clk.h> |
0dd6e484 | 24 | #include <linux/err.h> |
1e7bad0f | 25 | #include <linux/of.h> |
fc723856 | 26 | #include <linux/of_device.h> |
22ac9232 | 27 | |
868eb616 EG |
28 | /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */ |
29 | #define ORION_RSTOUT_MASK_OFFSET 0x20108 | |
30 | ||
31 | /* Internal registers can be configured at any 1 MiB aligned address */ | |
32 | #define INTERNAL_REGS_MASK ~(SZ_1M - 1) | |
22ac9232 SB |
33 | |
34 | /* | |
35 | * Watchdog timer block registers. | |
36 | */ | |
a855a7ce | 37 | #define TIMER_CTRL 0x0000 |
463f96e0 | 38 | #define TIMER_A370_STATUS 0x04 |
22ac9232 | 39 | |
9e058d4f | 40 | #define WDT_MAX_CYCLE_COUNT 0xffffffff |
22ac9232 | 41 | |
463f96e0 EG |
42 | #define WDT_A370_RATIO_MASK(v) ((v) << 16) |
43 | #define WDT_A370_RATIO_SHIFT 5 | |
44 | #define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT) | |
45 | ||
46 | #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) | |
47 | #define WDT_A370_EXPIRED BIT(31) | |
fa142ff5 | 48 | |
86a1e189 | 49 | static bool nowayout = WATCHDOG_NOWAYOUT; |
9e058d4f | 50 | static int heartbeat = -1; /* module parameter (seconds) */ |
22ac9232 | 51 | |
1924227b EG |
52 | struct orion_watchdog; |
53 | ||
fc723856 EG |
54 | struct orion_watchdog_data { |
55 | int wdt_counter_offset; | |
56 | int wdt_enable_bit; | |
57 | int rstout_enable_bit; | |
1924227b EG |
58 | int (*clock_init)(struct platform_device *, |
59 | struct orion_watchdog *); | |
490d8e3c | 60 | int (*start)(struct watchdog_device *); |
ebf5cf76 | 61 | int (*stop)(struct watchdog_device *); |
fc723856 EG |
62 | }; |
63 | ||
b89a9c40 EG |
64 | struct orion_watchdog { |
65 | struct watchdog_device wdt; | |
66 | void __iomem *reg; | |
67 | void __iomem *rstout; | |
68 | unsigned long clk_rate; | |
69 | struct clk *clk; | |
fc723856 | 70 | const struct orion_watchdog_data *data; |
b89a9c40 | 71 | }; |
22ac9232 | 72 | |
1924227b EG |
73 | static int orion_wdt_clock_init(struct platform_device *pdev, |
74 | struct orion_watchdog *dev) | |
df6707b2 | 75 | { |
1924227b | 76 | int ret; |
df6707b2 | 77 | |
463f96e0 | 78 | dev->clk = clk_get(&pdev->dev, NULL); |
1924227b EG |
79 | if (IS_ERR(dev->clk)) |
80 | return PTR_ERR(dev->clk); | |
81 | ret = clk_prepare_enable(dev->clk); | |
463f96e0 EG |
82 | if (ret) { |
83 | clk_put(dev->clk); | |
1924227b | 84 | return ret; |
463f96e0 | 85 | } |
df6707b2 | 86 | |
463f96e0 | 87 | dev->clk_rate = clk_get_rate(dev->clk); |
0dd6e484 | 88 | return 0; |
df6707b2 TR |
89 | } |
90 | ||
463f96e0 EG |
91 | static int armada370_wdt_clock_init(struct platform_device *pdev, |
92 | struct orion_watchdog *dev) | |
22ac9232 | 93 | { |
463f96e0 | 94 | int ret; |
22ac9232 | 95 | |
463f96e0 EG |
96 | dev->clk = clk_get(&pdev->dev, NULL); |
97 | if (IS_ERR(dev->clk)) | |
98 | return PTR_ERR(dev->clk); | |
99 | ret = clk_prepare_enable(dev->clk); | |
100 | if (ret) { | |
101 | clk_put(dev->clk); | |
102 | return ret; | |
103 | } | |
104 | ||
105 | /* Setup watchdog input clock */ | |
106 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
107 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT), | |
108 | WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT)); | |
109 | ||
110 | dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; | |
111 | return 0; | |
112 | } | |
113 | ||
114 | static int armadaxp_wdt_clock_init(struct platform_device *pdev, | |
115 | struct orion_watchdog *dev) | |
116 | { | |
117 | int ret; | |
118 | ||
119 | dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed"); | |
120 | if (IS_ERR(dev->clk)) | |
121 | return PTR_ERR(dev->clk); | |
122 | ret = clk_prepare_enable(dev->clk); | |
123 | if (ret) { | |
124 | clk_put(dev->clk); | |
125 | return ret; | |
126 | } | |
127 | ||
128 | /* Enable the fixed watchdog clock input */ | |
129 | atomic_io_modify(dev->reg + TIMER_CTRL, | |
130 | WDT_AXP_FIXED_ENABLE_BIT, | |
131 | WDT_AXP_FIXED_ENABLE_BIT); | |
1924227b EG |
132 | |
133 | dev->clk_rate = clk_get_rate(dev->clk); | |
134 | return 0; | |
135 | } | |
136 | ||
0dd6e484 | 137 | static int orion_wdt_ping(struct watchdog_device *wdt_dev) |
df6707b2 | 138 | { |
b89a9c40 | 139 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
df6707b2 | 140 | /* Reload watchdog duration */ |
fc723856 EG |
141 | writel(dev->clk_rate * wdt_dev->timeout, |
142 | dev->reg + dev->data->wdt_counter_offset); | |
0dd6e484 | 143 | return 0; |
df6707b2 TR |
144 | } |
145 | ||
463f96e0 EG |
146 | static int armada370_start(struct watchdog_device *wdt_dev) |
147 | { | |
148 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
eba985e2 | 149 | u32 reg; |
6d0f0dfd | 150 | |
22ac9232 | 151 | /* Set watchdog duration */ |
463f96e0 EG |
152 | writel(dev->clk_rate * wdt_dev->timeout, |
153 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 154 | |
463f96e0 EG |
155 | /* Clear the watchdog expiration bit */ |
156 | atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); | |
22ac9232 SB |
157 | |
158 | /* Enable watchdog timer */ | |
463f96e0 EG |
159 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
160 | dev->data->wdt_enable_bit); | |
161 | ||
eba985e2 EG |
162 | /* Enable reset on watchdog */ |
163 | reg = readl(dev->rstout); | |
164 | reg |= dev->data->rstout_enable_bit; | |
165 | writel(reg, dev->rstout); | |
463f96e0 EG |
166 | return 0; |
167 | } | |
168 | ||
490d8e3c | 169 | static int orion_start(struct watchdog_device *wdt_dev) |
22ac9232 | 170 | { |
b89a9c40 EG |
171 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
172 | ||
22ac9232 | 173 | /* Set watchdog duration */ |
fc723856 EG |
174 | writel(dev->clk_rate * wdt_dev->timeout, |
175 | dev->reg + dev->data->wdt_counter_offset); | |
22ac9232 | 176 | |
22ac9232 | 177 | /* Enable watchdog timer */ |
fc723856 EG |
178 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, |
179 | dev->data->wdt_enable_bit); | |
22ac9232 SB |
180 | |
181 | /* Enable reset on watchdog */ | |
fc723856 EG |
182 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, |
183 | dev->data->rstout_enable_bit); | |
6d0f0dfd | 184 | |
0dd6e484 | 185 | return 0; |
22ac9232 SB |
186 | } |
187 | ||
490d8e3c | 188 | static int orion_wdt_start(struct watchdog_device *wdt_dev) |
22ac9232 | 189 | { |
490d8e3c | 190 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
22ac9232 | 191 | |
490d8e3c EG |
192 | /* There are some per-SoC quirks to handle */ |
193 | return dev->data->start(wdt_dev); | |
194 | } | |
195 | ||
ebf5cf76 | 196 | static int orion_stop(struct watchdog_device *wdt_dev) |
22ac9232 | 197 | { |
b89a9c40 | 198 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
6d0f0dfd | 199 | |
22ac9232 | 200 | /* Disable reset on watchdog */ |
fc723856 | 201 | atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0); |
22ac9232 SB |
202 | |
203 | /* Disable watchdog timer */ | |
fc723856 | 204 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); |
6d0f0dfd | 205 | |
0dd6e484 | 206 | return 0; |
6d0f0dfd WVS |
207 | } |
208 | ||
ebf5cf76 EG |
209 | static int armada370_stop(struct watchdog_device *wdt_dev) |
210 | { | |
211 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
212 | u32 reg; | |
213 | ||
214 | /* Disable reset on watchdog */ | |
215 | reg = readl(dev->rstout); | |
216 | reg &= ~dev->data->rstout_enable_bit; | |
217 | writel(reg, dev->rstout); | |
218 | ||
219 | /* Disable watchdog timer */ | |
220 | atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static int orion_wdt_stop(struct watchdog_device *wdt_dev) | |
226 | { | |
227 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
228 | ||
229 | return dev->data->stop(wdt_dev); | |
230 | } | |
231 | ||
b89a9c40 | 232 | static int orion_wdt_enabled(struct orion_watchdog *dev) |
6d0f0dfd | 233 | { |
d9d0c53d EG |
234 | bool enabled, running; |
235 | ||
fc723856 EG |
236 | enabled = readl(dev->rstout) & dev->data->rstout_enable_bit; |
237 | running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; | |
0dd6e484 | 238 | |
d9d0c53d EG |
239 | return enabled && running; |
240 | } | |
22ac9232 | 241 | |
0dd6e484 | 242 | static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev) |
6d0f0dfd | 243 | { |
b89a9c40 | 244 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); |
fc723856 | 245 | return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate; |
22ac9232 SB |
246 | } |
247 | ||
0dd6e484 AL |
248 | static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev, |
249 | unsigned int timeout) | |
22ac9232 | 250 | { |
0dd6e484 | 251 | wdt_dev->timeout = timeout; |
df6707b2 TR |
252 | return 0; |
253 | } | |
254 | ||
0dd6e484 AL |
255 | static const struct watchdog_info orion_wdt_info = { |
256 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, | |
257 | .identity = "Orion Watchdog", | |
22ac9232 SB |
258 | }; |
259 | ||
0dd6e484 AL |
260 | static const struct watchdog_ops orion_wdt_ops = { |
261 | .owner = THIS_MODULE, | |
262 | .start = orion_wdt_start, | |
263 | .stop = orion_wdt_stop, | |
264 | .ping = orion_wdt_ping, | |
265 | .set_timeout = orion_wdt_set_timeout, | |
266 | .get_timeleft = orion_wdt_get_timeleft, | |
22ac9232 SB |
267 | }; |
268 | ||
e97662e1 EG |
269 | static irqreturn_t orion_wdt_irq(int irq, void *devid) |
270 | { | |
271 | panic("Watchdog Timeout"); | |
272 | return IRQ_HANDLED; | |
273 | } | |
274 | ||
868eb616 EG |
275 | /* |
276 | * The original devicetree binding for this driver specified only | |
277 | * one memory resource, so in order to keep DT backwards compatibility | |
278 | * we try to fallback to a hardcoded register address, if the resource | |
279 | * is missing from the devicetree. | |
280 | */ | |
281 | static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev, | |
282 | phys_addr_t internal_regs) | |
283 | { | |
284 | struct resource *res; | |
285 | phys_addr_t rstout; | |
286 | ||
287 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
288 | if (res) | |
289 | return devm_ioremap(&pdev->dev, res->start, | |
290 | resource_size(res)); | |
291 | ||
868eb616 EG |
292 | rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET; |
293 | ||
edd9d3cf | 294 | WARN(1, FW_BUG "falling back to harcoded RSTOUT reg %pa\n", &rstout); |
868eb616 EG |
295 | return devm_ioremap(&pdev->dev, rstout, 0x4); |
296 | } | |
297 | ||
fc723856 EG |
298 | static const struct orion_watchdog_data orion_data = { |
299 | .rstout_enable_bit = BIT(1), | |
300 | .wdt_enable_bit = BIT(4), | |
301 | .wdt_counter_offset = 0x24, | |
1924227b | 302 | .clock_init = orion_wdt_clock_init, |
490d8e3c | 303 | .start = orion_start, |
ebf5cf76 | 304 | .stop = orion_stop, |
fc723856 EG |
305 | }; |
306 | ||
463f96e0 EG |
307 | static const struct orion_watchdog_data armada370_data = { |
308 | .rstout_enable_bit = BIT(8), | |
309 | .wdt_enable_bit = BIT(8), | |
310 | .wdt_counter_offset = 0x34, | |
311 | .clock_init = armada370_wdt_clock_init, | |
312 | .start = armada370_start, | |
ebf5cf76 | 313 | .stop = armada370_stop, |
22ac9232 SB |
314 | }; |
315 | ||
463f96e0 EG |
316 | static const struct orion_watchdog_data armadaxp_data = { |
317 | .rstout_enable_bit = BIT(8), | |
318 | .wdt_enable_bit = BIT(8), | |
319 | .wdt_counter_offset = 0x34, | |
320 | .clock_init = armadaxp_wdt_clock_init, | |
321 | .start = armada370_start, | |
ebf5cf76 | 322 | .stop = armada370_stop, |
463f96e0 EG |
323 | }; |
324 | ||
fc723856 EG |
325 | static const struct of_device_id orion_wdt_of_match_table[] = { |
326 | { | |
327 | .compatible = "marvell,orion-wdt", | |
328 | .data = &orion_data, | |
329 | }, | |
463f96e0 EG |
330 | { |
331 | .compatible = "marvell,armada-370-wdt", | |
332 | .data = &armada370_data, | |
333 | }, | |
334 | { | |
335 | .compatible = "marvell,armada-xp-wdt", | |
336 | .data = &armadaxp_data, | |
337 | }, | |
fc723856 EG |
338 | {}, |
339 | }; | |
340 | MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table); | |
341 | ||
aaaac9ec EG |
342 | static int orion_wdt_get_regs(struct platform_device *pdev, |
343 | struct orion_watchdog *dev) | |
344 | { | |
92d4fc1a | 345 | struct device_node *node = pdev->dev.of_node; |
aaaac9ec EG |
346 | struct resource *res; |
347 | ||
348 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
349 | if (!res) | |
350 | return -ENODEV; | |
351 | dev->reg = devm_ioremap(&pdev->dev, res->start, | |
352 | resource_size(res)); | |
353 | if (!dev->reg) | |
354 | return -ENOMEM; | |
355 | ||
92d4fc1a EG |
356 | /* Each supported compatible has some RSTOUT register quirk */ |
357 | if (of_device_is_compatible(node, "marvell,orion-wdt")) { | |
358 | ||
359 | dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start & | |
360 | INTERNAL_REGS_MASK); | |
361 | if (!dev->rstout) | |
362 | return -ENODEV; | |
363 | ||
364 | } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") || | |
365 | of_device_is_compatible(node, "marvell,armada-xp-wdt")) { | |
366 | ||
367 | /* Dedicated RSTOUT register, can be requested. */ | |
368 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
369 | dev->rstout = devm_ioremap_resource(&pdev->dev, res); | |
370 | if (IS_ERR(dev->rstout)) | |
371 | return PTR_ERR(dev->rstout); | |
372 | ||
373 | } else { | |
aaaac9ec | 374 | return -ENODEV; |
92d4fc1a | 375 | } |
aaaac9ec EG |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
2d991a16 | 380 | static int orion_wdt_probe(struct platform_device *pdev) |
22ac9232 | 381 | { |
b89a9c40 | 382 | struct orion_watchdog *dev; |
fc723856 | 383 | const struct of_device_id *match; |
b89a9c40 | 384 | unsigned int wdt_max_duration; /* (seconds) */ |
e97662e1 | 385 | int ret, irq; |
22ac9232 | 386 | |
b89a9c40 EG |
387 | dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog), |
388 | GFP_KERNEL); | |
389 | if (!dev) | |
390 | return -ENOMEM; | |
391 | ||
fc723856 EG |
392 | match = of_match_device(orion_wdt_of_match_table, &pdev->dev); |
393 | if (!match) | |
394 | /* Default legacy match */ | |
395 | match = &orion_wdt_of_match_table[0]; | |
396 | ||
b89a9c40 EG |
397 | dev->wdt.info = &orion_wdt_info; |
398 | dev->wdt.ops = &orion_wdt_ops; | |
399 | dev->wdt.min_timeout = 1; | |
fc723856 | 400 | dev->data = match->data; |
9e058d4f | 401 | |
aaaac9ec EG |
402 | ret = orion_wdt_get_regs(pdev, dev); |
403 | if (ret) | |
404 | return ret; | |
0dd6e484 | 405 | |
1924227b | 406 | ret = dev->data->clock_init(pdev, dev); |
0dd6e484 | 407 | if (ret) { |
1924227b | 408 | dev_err(&pdev->dev, "cannot initialize clock\n"); |
9e058d4f | 409 | return ret; |
0dd6e484 | 410 | } |
9e058d4f | 411 | |
b89a9c40 EG |
412 | wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate; |
413 | ||
414 | dev->wdt.timeout = wdt_max_duration; | |
415 | dev->wdt.max_timeout = wdt_max_duration; | |
416 | watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev); | |
0dd6e484 | 417 | |
b89a9c40 EG |
418 | platform_set_drvdata(pdev, &dev->wdt); |
419 | watchdog_set_drvdata(&dev->wdt, dev); | |
0dd6e484 | 420 | |
d9d0c53d EG |
421 | /* |
422 | * Let's make sure the watchdog is fully stopped, unless it's | |
423 | * explicitly enabled. This may be the case if the module was | |
424 | * removed and re-insterted, or if the bootloader explicitly | |
425 | * set a running watchdog before booting the kernel. | |
426 | */ | |
b89a9c40 EG |
427 | if (!orion_wdt_enabled(dev)) |
428 | orion_wdt_stop(&dev->wdt); | |
d9d0c53d | 429 | |
e97662e1 EG |
430 | /* Request the IRQ only after the watchdog is disabled */ |
431 | irq = platform_get_irq(pdev, 0); | |
432 | if (irq > 0) { | |
433 | /* | |
434 | * Not all supported platforms specify an interrupt for the | |
435 | * watchdog, so let's make it optional. | |
436 | */ | |
437 | ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0, | |
b89a9c40 | 438 | pdev->name, dev); |
e97662e1 EG |
439 | if (ret < 0) { |
440 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
441 | goto disable_clk; | |
442 | } | |
443 | } | |
444 | ||
b89a9c40 EG |
445 | watchdog_set_nowayout(&dev->wdt, nowayout); |
446 | ret = watchdog_register_device(&dev->wdt); | |
bb02c662 EG |
447 | if (ret) |
448 | goto disable_clk; | |
9e058d4f | 449 | |
27c766aa | 450 | pr_info("Initial timeout %d sec%s\n", |
b89a9c40 | 451 | dev->wdt.timeout, nowayout ? ", nowayout" : ""); |
9e058d4f | 452 | return 0; |
bb02c662 EG |
453 | |
454 | disable_clk: | |
b89a9c40 | 455 | clk_disable_unprepare(dev->clk); |
463f96e0 | 456 | clk_put(dev->clk); |
bb02c662 | 457 | return ret; |
9e058d4f TR |
458 | } |
459 | ||
4b12b896 | 460 | static int orion_wdt_remove(struct platform_device *pdev) |
9e058d4f | 461 | { |
b89a9c40 EG |
462 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
463 | struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev); | |
464 | ||
465 | watchdog_unregister_device(wdt_dev); | |
466 | clk_disable_unprepare(dev->clk); | |
463f96e0 | 467 | clk_put(dev->clk); |
0dd6e484 | 468 | return 0; |
22ac9232 SB |
469 | } |
470 | ||
3b937a7d | 471 | static void orion_wdt_shutdown(struct platform_device *pdev) |
df6707b2 | 472 | { |
b89a9c40 EG |
473 | struct watchdog_device *wdt_dev = platform_get_drvdata(pdev); |
474 | orion_wdt_stop(wdt_dev); | |
df6707b2 TR |
475 | } |
476 | ||
3b937a7d NP |
477 | static struct platform_driver orion_wdt_driver = { |
478 | .probe = orion_wdt_probe, | |
82268714 | 479 | .remove = orion_wdt_remove, |
3b937a7d | 480 | .shutdown = orion_wdt_shutdown, |
9e058d4f TR |
481 | .driver = { |
482 | .owner = THIS_MODULE, | |
3b937a7d | 483 | .name = "orion_wdt", |
85eee819 | 484 | .of_match_table = orion_wdt_of_match_table, |
9e058d4f TR |
485 | }, |
486 | }; | |
487 | ||
b8ec6118 | 488 | module_platform_driver(orion_wdt_driver); |
22ac9232 SB |
489 | |
490 | MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>"); | |
3b937a7d | 491 | MODULE_DESCRIPTION("Orion Processor Watchdog"); |
22ac9232 SB |
492 | |
493 | module_param(heartbeat, int, 0); | |
df6707b2 | 494 | MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds"); |
22ac9232 | 495 | |
86a1e189 | 496 | module_param(nowayout, bool, 0); |
df6707b2 TR |
497 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
498 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
22ac9232 SB |
499 | |
500 | MODULE_LICENSE("GPL"); | |
f3ea733e | 501 | MODULE_ALIAS("platform:orion_wdt"); |