]>
Commit | Line | Data |
---|---|---|
9325fa36 VW |
1 | /* |
2 | * drivers/char/watchdog/pnx4008_wdt.c | |
3 | * | |
4 | * Watchdog driver for PNX4008 board | |
5 | * | |
6 | * Authors: Dmitry Chigirev <source@mvista.com>, | |
5f3b2756 | 7 | * Vitaly Wool <vitalywool@gmail.com> |
9325fa36 VW |
8 | * Based on sa1100 driver, |
9 | * Copyright (C) 2000 Oleg Drokin <green@crimea.edu> | |
10 | * | |
6b1e8386 WS |
11 | * 2005-2006 (c) MontaVista Software, Inc. |
12 | * | |
13 | * (C) 2012 Wolfram Sang, Pengutronix | |
14 | * | |
15 | * This file is licensed under the terms of the GNU General Public License | |
16 | * version 2. This program is licensed "as is" without any warranty of any | |
17 | * kind, whether express or implied. | |
9325fa36 VW |
18 | */ |
19 | ||
27c766aa JP |
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
21 | ||
9325fa36 VW |
22 | #include <linux/module.h> |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/kernel.h> | |
9325fa36 VW |
26 | #include <linux/miscdevice.h> |
27 | #include <linux/watchdog.h> | |
28 | #include <linux/init.h> | |
9325fa36 VW |
29 | #include <linux/platform_device.h> |
30 | #include <linux/clk.h> | |
99d2853a | 31 | #include <linux/spinlock.h> |
84ca995c | 32 | #include <linux/io.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
6b1e8386 | 34 | #include <linux/err.h> |
a09e64fb | 35 | #include <mach/hardware.h> |
9325fa36 | 36 | |
9325fa36 VW |
37 | /* WatchDog Timer - Chapter 23 Page 207 */ |
38 | ||
39 | #define DEFAULT_HEARTBEAT 19 | |
40 | #define MAX_HEARTBEAT 60 | |
41 | ||
42 | /* Watchdog timer register set definition */ | |
43 | #define WDTIM_INT(p) ((p) + 0x0) | |
44 | #define WDTIM_CTRL(p) ((p) + 0x4) | |
45 | #define WDTIM_COUNTER(p) ((p) + 0x8) | |
46 | #define WDTIM_MCTRL(p) ((p) + 0xC) | |
47 | #define WDTIM_MATCH0(p) ((p) + 0x10) | |
48 | #define WDTIM_EMR(p) ((p) + 0x14) | |
49 | #define WDTIM_PULSE(p) ((p) + 0x18) | |
50 | #define WDTIM_RES(p) ((p) + 0x1C) | |
51 | ||
52 | /* WDTIM_INT bit definitions */ | |
53 | #define MATCH_INT 1 | |
54 | ||
55 | /* WDTIM_CTRL bit definitions */ | |
56 | #define COUNT_ENAB 1 | |
143a2e54 WVS |
57 | #define RESET_COUNT (1 << 1) |
58 | #define DEBUG_EN (1 << 2) | |
9325fa36 VW |
59 | |
60 | /* WDTIM_MCTRL bit definitions */ | |
61 | #define MR0_INT 1 | |
62 | #undef RESET_COUNT0 | |
143a2e54 WVS |
63 | #define RESET_COUNT0 (1 << 2) |
64 | #define STOP_COUNT0 (1 << 2) | |
65 | #define M_RES1 (1 << 3) | |
66 | #define M_RES2 (1 << 4) | |
67 | #define RESFRC1 (1 << 5) | |
68 | #define RESFRC2 (1 << 6) | |
9325fa36 VW |
69 | |
70 | /* WDTIM_EMR bit definitions */ | |
71 | #define EXT_MATCH0 1 | |
143a2e54 | 72 | #define MATCH_OUTPUT_HIGH (2 << 4) /*a MATCH_CTRL setting */ |
9325fa36 VW |
73 | |
74 | /* WDTIM_RES bit definitions */ | |
75 | #define WDOG_RESET 1 /* read only */ | |
76 | ||
77 | #define WDOG_COUNTER_RATE 13000000 /*the counter clock is 13 MHz fixed */ | |
78 | ||
86a1e189 | 79 | static bool nowayout = WATCHDOG_NOWAYOUT; |
6b1e8386 | 80 | static unsigned int heartbeat = DEFAULT_HEARTBEAT; |
9325fa36 | 81 | |
c7dfd0cc | 82 | static DEFINE_SPINLOCK(io_lock); |
9325fa36 VW |
83 | static void __iomem *wdt_base; |
84 | struct clk *wdt_clk; | |
85 | ||
6b1e8386 | 86 | static int pnx4008_wdt_start(struct watchdog_device *wdd) |
9325fa36 | 87 | { |
99d2853a WVS |
88 | spin_lock(&io_lock); |
89 | ||
9325fa36 | 90 | /* stop counter, initiate counter reset */ |
7cbc3535 | 91 | writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); |
9325fa36 | 92 | /*wait for reset to complete. 100% guarantee event */ |
7cbc3535 | 93 | while (readl(WDTIM_COUNTER(wdt_base))) |
65a64ec3 | 94 | cpu_relax(); |
9325fa36 | 95 | /* internal and external reset, stop after that */ |
7cbc3535 | 96 | writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); |
9325fa36 | 97 | /* configure match output */ |
7cbc3535 | 98 | writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); |
9325fa36 | 99 | /* clear interrupt, just in case */ |
7cbc3535 | 100 | writel(MATCH_INT, WDTIM_INT(wdt_base)); |
9325fa36 | 101 | /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ |
7cbc3535 | 102 | writel(0xFFFF, WDTIM_PULSE(wdt_base)); |
6b1e8386 | 103 | writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); |
9325fa36 | 104 | /*enable counter, stop when debugger active */ |
7cbc3535 | 105 | writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); |
99d2853a WVS |
106 | |
107 | spin_unlock(&io_lock); | |
6b1e8386 | 108 | return 0; |
9325fa36 VW |
109 | } |
110 | ||
6b1e8386 | 111 | static int pnx4008_wdt_stop(struct watchdog_device *wdd) |
9325fa36 | 112 | { |
99d2853a WVS |
113 | spin_lock(&io_lock); |
114 | ||
7cbc3535 | 115 | writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
99d2853a WVS |
116 | |
117 | spin_unlock(&io_lock); | |
6b1e8386 | 118 | return 0; |
9325fa36 VW |
119 | } |
120 | ||
6b1e8386 WS |
121 | static int pnx4008_wdt_set_timeout(struct watchdog_device *wdd, |
122 | unsigned int new_timeout) | |
9325fa36 | 123 | { |
6b1e8386 | 124 | return 0; |
9325fa36 VW |
125 | } |
126 | ||
6b1e8386 | 127 | static const struct watchdog_info pnx4008_wdt_ident = { |
9325fa36 VW |
128 | .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | |
129 | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, | |
130 | .identity = "PNX4008 Watchdog", | |
131 | }; | |
132 | ||
6b1e8386 | 133 | static const struct watchdog_ops pnx4008_wdt_ops = { |
9325fa36 | 134 | .owner = THIS_MODULE, |
6b1e8386 WS |
135 | .start = pnx4008_wdt_start, |
136 | .stop = pnx4008_wdt_stop, | |
137 | .set_timeout = pnx4008_wdt_set_timeout, | |
9325fa36 VW |
138 | }; |
139 | ||
6b1e8386 WS |
140 | static struct watchdog_device pnx4008_wdd = { |
141 | .info = &pnx4008_wdt_ident, | |
142 | .ops = &pnx4008_wdt_ops, | |
143 | .min_timeout = 1, | |
144 | .max_timeout = MAX_HEARTBEAT, | |
9325fa36 VW |
145 | }; |
146 | ||
b6bf291f | 147 | static int __devinit pnx4008_wdt_probe(struct platform_device *pdev) |
9325fa36 | 148 | { |
19f505f0 WS |
149 | struct resource *r; |
150 | int ret = 0; | |
9325fa36 VW |
151 | |
152 | if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT) | |
153 | heartbeat = DEFAULT_HEARTBEAT; | |
154 | ||
19f505f0 WS |
155 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
156 | wdt_base = devm_request_and_ioremap(&pdev->dev, r); | |
157 | if (!wdt_base) | |
158 | return -EADDRINUSE; | |
9325fa36 | 159 | |
9bb787f4 | 160 | wdt_clk = clk_get(&pdev->dev, NULL); |
19f505f0 WS |
161 | if (IS_ERR(wdt_clk)) |
162 | return PTR_ERR(wdt_clk); | |
24fd1eda RK |
163 | |
164 | ret = clk_enable(wdt_clk); | |
19f505f0 | 165 | if (ret) |
24fd1eda | 166 | goto out; |
19f505f0 | 167 | |
6b1e8386 WS |
168 | pnx4008_wdd.timeout = heartbeat; |
169 | pnx4008_wdd.bootstatus = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? | |
7cbc3535 | 170 | WDIOF_CARDRESET : 0; |
6b1e8386 WS |
171 | watchdog_set_nowayout(&pnx4008_wdd, nowayout); |
172 | ||
173 | pnx4008_wdt_stop(&pnx4008_wdd); /* disable for now */ | |
9325fa36 | 174 | |
6b1e8386 | 175 | ret = watchdog_register_device(&pnx4008_wdd); |
9325fa36 | 176 | if (ret < 0) { |
6b1e8386 WS |
177 | dev_err(&pdev->dev, "cannot register watchdog device\n"); |
178 | goto disable_clk; | |
9325fa36 VW |
179 | } |
180 | ||
19f505f0 WS |
181 | dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n", |
182 | heartbeat); | |
183 | ||
184 | return 0; | |
185 | ||
6b1e8386 WS |
186 | disable_clk: |
187 | clk_disable(wdt_clk); | |
9325fa36 | 188 | out: |
19f505f0 | 189 | clk_put(wdt_clk); |
9325fa36 VW |
190 | return ret; |
191 | } | |
192 | ||
b6bf291f | 193 | static int __devexit pnx4008_wdt_remove(struct platform_device *pdev) |
9325fa36 | 194 | { |
6b1e8386 | 195 | watchdog_unregister_device(&pnx4008_wdd); |
24fd1eda RK |
196 | |
197 | clk_disable(wdt_clk); | |
198 | clk_put(wdt_clk); | |
199 | ||
9325fa36 VW |
200 | return 0; |
201 | } | |
202 | ||
203 | static struct platform_driver platform_wdt_driver = { | |
204 | .driver = { | |
1508c995 | 205 | .name = "pnx4008-watchdog", |
f37d193c | 206 | .owner = THIS_MODULE, |
9325fa36 VW |
207 | }, |
208 | .probe = pnx4008_wdt_probe, | |
b6bf291f | 209 | .remove = __devexit_p(pnx4008_wdt_remove), |
9325fa36 VW |
210 | }; |
211 | ||
b8ec6118 | 212 | module_platform_driver(platform_wdt_driver); |
9325fa36 VW |
213 | |
214 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
6b1e8386 | 215 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); |
9325fa36 VW |
216 | MODULE_DESCRIPTION("PNX4008 Watchdog Driver"); |
217 | ||
6b1e8386 | 218 | module_param(heartbeat, uint, 0); |
9325fa36 VW |
219 | MODULE_PARM_DESC(heartbeat, |
220 | "Watchdog heartbeat period in seconds from 1 to " | |
221 | __MODULE_STRING(MAX_HEARTBEAT) ", default " | |
222 | __MODULE_STRING(DEFAULT_HEARTBEAT)); | |
223 | ||
86a1e189 | 224 | module_param(nowayout, bool, 0); |
9325fa36 VW |
225 | MODULE_PARM_DESC(nowayout, |
226 | "Set to 1 to keep watchdog running after device release"); | |
227 | ||
228 | MODULE_LICENSE("GPL"); | |
229 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
1508c995 | 230 | MODULE_ALIAS("platform:pnx4008-watchdog"); |